Switched-Capacitor Techniques for High-Accuracy Filter and ADC Design

259 Pages·2007·9.07 MB·English

by  Abraham Pressman

Switched-Capacitor Techniques for
High-Accuracy Filter and ADC Design
By
PATRICK J. QUINN
Xilinx, Dublin, Ireland
and
ARTHUR H.M. VAN ROERMUND
Technical University of Eindhoven,
The Netherlands
AC.I.P. Catalogue record for this book is available from the Library of Congress.
ISBN 978-1-4020-6257-5 (HB)
ISBN 978-1-4020-6258-2 (e-book)
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© 2007 Springer
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To Siobhán
A
BSTRACT
Abstract
In this book, switched-capacitor (SC) techniques are proposed which allow the attainment of
higher intrinsic analogue accuracies than previously possible in such application areas as
analogue filter and analogue-to-digital converter (ADC) design. The design philosophy is to
create the required functionality without relying on trimming or digital calibration means but
instead to develop methods which have reduced dependence on both component matching
(especially capacitor matching) and parasitic effects (especially parasitic capacitance).
At a system level, orthogonal design procedures are employed which ensure that
artefacts due to expected circuit imperfections are avoided in the system transfer function. For
instance, in SC filter design, orthogonal-hardware-modulation helps alleviate the effects of N-
path mismatch through the introduction of an extra degree of freedom, where the number of
hardware paths N (hardware modulation) is decoupled from the functional modulation factor
n, as introduced by the transformation zÆzn. In algorithmic ADC design, both cyclic and
pipelined, conventional techniques make use of multiplying digital-to-analogue converters (or
MDACs) which require SC circuits with accurate capacitor ratios to implement accurate signal
multiplication. On the other hand, in this book, the ADC function is decomposed into the
simple sub-functions of signal addition and level shifting which can be implemented using SC
techniques which don’t rely on accurate capacitor ratios.
At circuit level, delta-charge flow (d-Q) techniques are employed to realize SC circuits
with more accurate transfers than their conventional charge-transfer (QT) counterparts. Unlike
QT SC circuits, d-Q SC circuits do not require signal charge transfer from capacitor to capaci-
tor via the amplifier virtual earth node. Instead, only a delta charge dQ flows in the virtual
earth node due to the presence of parasitic capacitors at the amplifier input terminals. In SC fil-
ter design, delta-charge-redistribution (d-QR) is a means for the accurate implementation of
filter transfer functions using passive charge redistribution between capacitors in the feedback
path of an amplifier, instead of active charge transfer between capacitors through the active
intervention of an amplifier in QT SC filters. In ADC design, a highly accurate method (C+C)
for the stacking of capacitor voltages is proposed which uses a floating-hold-buffer for imple-
mentation. The accuracy of signal addition is practically insensitive to the matching and linear-
ity of the signal capacitors as well as the presence of parasitic terminal capacitance.
A number of other innovative circuit techniques have been included in the book, such as:
a versatile accurate track-and-hold (T&H) which is re-programmable for unipolar, bipolar and
vii
viii Abstract
differential modes; clock-skew insensitive sampling; a common-mode-feedback circuit which
significantly boosts the common-mode rejection ratio of single-ended amplifiers; high-effi-
ciency dual-input transconductance amplifiers which make use of the level shift properties of
switched capacitors; a low-reference dynamic comparator.
The validity of the concepts developed and analyzed in the book has been demonstrated
in practice with the design of CMOS SC bandpass filters and algorithmic ADC stages (both
cyclic and pipelined). The intrinsic accuracies achieved go beyond those achieved with previ-
ous state-of-the-art solutions with a consequent reduction in power consumption for the same
speed applications. For example, a 10.7MHz radio IF selectivity filter integrated in standard
CMOS, employing the proposed methods, achieves an accuracy greater than ceramic filters.
Another example is an ADC with better than 12-bit intrinsic performance, albeit capacitors
with only 9-bits matching accuracy were used in the realization. The ADC architecture is also
very robust and has proven itself in an embedded digital VLSI application in the very newest
65nm CMOS. The power consumptions and silicon areas of the solutions proposed here are
lower than other known solutions from the literature.
C
ONTENTS
Contents
Abstract vii
1
Symbols and Abbreviations xv
3
Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x vii
Chapter 1: Introduction 1
1
1.1 Cost-Performance Trade-offs in IC Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Modern IC Design Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2.1 Digital IC Design Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.2 Analogue IC Design Challenges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.3 Test Challenges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.4 Process and Design Work-Arounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Switched Capacitors for Analogue Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Key Points for High Performance SC Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.5 Scope of Book. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.6 Book Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2: Key Concepts for Accurate SC Design 9
2
2.1 Orthogonal Design Procedures in Filter and ADC Realizations . . . . . . . . . . . . . . . 10
2.2 Delta Charge Flow SC Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1 The Sample-And-Hold Stage: Voltage Buffer . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.2 The Delta-Charge-Redistribution Stage: Voltage Down-Scaler. . . . . . . . . . 13
2.2.3 C+C Concept: Voltage Up-Scaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3 The Floating-Hold-Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chapter 3: SC Amplifier Design at Black-Box Level 17
3
3.1 Amplifier Design Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ix
x Contents
3.2 The Settling Error Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.1 Static Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.2 Dynamic Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 Design Procedure for Optimized Settling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3.1 Single-Ended or Fully-Differential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3.2 Capacitor Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.3 OTA Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.4 Choice of V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
on
3.3.4.1 OTA Transconductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.4.2 Matching Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3.4.3 Influence of Channel Mobility Factor. . . . . . . . . . . . . . . . . . . . . . . 28
3.3.4.4 Choice of Gate Lengths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3.5 Minimum Settling Time Constant and Bias Current . . . . . . . . . . . . . . . . . . 29
3.4 OTA Slewing Requirement in SC Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4.1 The Slew Rate Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4.2 Minimum OTA Tail Current for No Slewing . . . . . . . . . . . . . . . . . . . . . . . 32
3.4.3 Calculation of Slew Time, tslew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.4.4 Dynamic Settling Error including OTA Slewing . . . . . . . . . . . . . . . . . . . . . 35
3.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Chapter 4: Amplifier Architectures for SC Applications 37
4
4.1 Review of Amplifier Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1.1 Primary OTA Stages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1.1.1 Telescopic OTA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.1.1.2 Current Mirror OTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.1.3 Folded OTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1.1.4 General Conclusions for the Three Primary OTA Stages. . . . . . . . 42
4.1.2 OTA Cascade Stages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.1.2.1 Pre-buffer Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.1.2.2 Pre-gain Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.1.2.3 Miller Output Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.1.2.4 Ahuja Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.2 The Dual-Input Telescopic OTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.2.1 The SC Single-Input Telescopic OTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.2.2 SC DITO Architectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.2.3 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.2.4 Amplifier Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.2.5 Signal Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.3 Cascode Frequency Response Design Issues. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.3.1 The Effect of Cascoding on the Closed-Loop Settling Response. . . . . . . . . 55
4.3.2 Low Frequency Miller Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.3.3 Neutralization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Contents xi
4.4 Boosting the g of a Cascode Stage using Active Feedback . . . . . . . . . . . . . . . . . . 60
m
4.4.1 The RGC with High Frequency Design Considerations . . . . . . . . . . . . . . 60
4.4.2 Reducing Low Frequency Miller Multiplication . . . . . . . . . . . . . . . . . . . . . 63
4.5 Low Voltage High Frequency RGC Architectures. . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.5.1 Suitability of RGCs for Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.5.2 LV RGC using Level Shift Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.5.3 LV RGC using Folded Cascode Voltage Sensing. . . . . . . . . . . . . . . . . . . . . 65
4.5.4 LV RGC using Dynamic Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.6 OTA DC Gain Improvement using Partial Positive Feedback. . . . . . . . . . . . . . . . . 67
4.6.1 OTA Design Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.6.2 Circuit Implementation of Partial Positive Feedback . . . . . . . . . . . . . . . . . 69
4.7 Optimization of SC Settling Response with Inclusion of Feedback Loop Switches 70
4.7.1 Effect on Settling of Switch Resistance in OTA Feedback Loop. . . . . . . . . 71
4.7.2 Switch Design Strategy for Speed-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.8 Conclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Chapter 5: Low-Sensitivity SC BPF Concepts 77
5
5.1 Sensitivity comparison of SC and CT Filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.2 BPF Function Including Hardware Imperfections . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.3 SC BPF Based on Modified N-Path Design Technique. . . . . . . . . . . . . . . . . . . . . . 81
5.3.1 High-Q BPF Construction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.3.2 N-Path Design Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.3.3 Modified N-Path Technique using Orthogonal Hardware Modulation. . . . . 82
5.4 Delta Charge Redistribution (δ-QR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.4.1 δ-QR for Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.4.2 δ-QR vs. QT SC Integrators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.5 δ-QR N-path SC BPFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.5.1 QT SC BPF Via State-Of-The-Art Biquad . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.5.2 Hybrid N-Path SC BPF (QT/δ-QR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.5.3 δ-QR T ype I N-path SC BPF (δ-QR-I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.5.4 δ-QR Type II N-path SC BPF (δ-QR-II) .. ... . . . . . . . . . . . . . . . . . . . . . . 99
5.5.5 Performance Comparison of N-path SC BPF Stages . . . . . . . . . . . . . . . . . 102
5.6 Conclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Chapter 6: High-Accuracy δ-QR SC BPF Design and Measurements 107
6
6.1 SC Video BPF - the TV Cloche Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.1.1 System Level Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.1.2 Design of SC Cloche Filter Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.1.2.1 Filter Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.1.2.2 SC BPF Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.1.2.3 Common-Mode Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.1.2.4 Chip Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
xii Contents
6.1.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.2 10.7MHz SC Radio IF BPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.2.1 System Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.2.2 Design of Radio IF Filter Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.2.2.1 SC Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.2.2.2 Selectable Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.2.2.3 Track-and-Hold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.2.2.4 Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.2.2.5 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.2.2.6 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.2.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.4 Appendix: Bandwidth Shrinkage of Cascaded Filter Stages . . . . . . . . . . . . . . . . . 133
Chapter 7: ADC Design at Black-Box Level 135
7
7.1 ADC Black Box Representation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
7.2 Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.2.1 Static Error Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.2.1.1 Offset and Gain Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.2.1.2 Differential Non-linearity (DNL) . . . . . . . . . . . . . . . . . . . . . . . . . 138
7.2.1.3 Integral Non-linearity (INL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
7.2.2 Dynamic Error Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7.2.2.1 Signal-to-Noise Ratio (SNR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
7.2.2.2 Effective Number of Bits (ENOB). . . . . . . . . . . . . . . . . . . . . . . . . 140
7.2.2.3 Total Harmonic Distortion (THD). . . . . . . . . . . . . . . . . . . . . . . . . 140
7.2.2.4 Spurious Free Dynamic Range (SFDR). . . . . . . . . . . . . . . . . . . . . 140
7.2.2.5 Intermodulation Distortion (IMD). . . . . . . . . . . . . . . . . . . . . . . . . 141
7.3 Anti-Aliasing Pre-Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
7.4 Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
7.4.1 Sampling Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
7.4.2 Sample Clock Phase Noise Related to Allowable Sampling Jitter. . . . . . . 146
7.4.3 Sample Clock Noise Spectrum. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
7.5 Quantization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
7.5.1 Quantization Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
7.5.1.1 Uniform coding model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
7.5.1.2 Long and short coding model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
7.5.1.3 Signal-to-Quantization Noise Ratios. . . . . . . . . . . . . . . . . . . . . . . 152
7.5.2 Quantizer Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
7.6 Effective Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
7.7 ADC Conversion Efficiency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
7.7.1 Minimum SNR Limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
7.7.2 Minimum Power Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162