SVA: The Power of Assertions in SystemVerilog

589 Pages·2015·5.89 MB·English

by  Eduard Cerny

Eduard Cerny · Surrendra Dudani
John Havlicek · Dmitry Korchemny
SVA: The Power
of Assertions in
SystemVerilog
Second Edition
SVA: The Power of Assertions in SystemVerilog

Eduard Cerny • Surrendra Dudani (cid:129) John Havlicek
Dmitry Korchemny
SVA: The Power of
Assertions in SystemVerilog
Second Edition
123
EduardCerny SurrendraDudani
Synopsys,Inc. Synopsys,Inc.
Worcester Newton,MA,USA
MA,USA
DmitryKorchemny
JohnHavlicek Intel,KfarSaba,Israel
CadenceDesignSystems
Austin,TX,USA
ISBN978-3-319-07138-1 ISBN978-3-319-07139-8(eBook)
DOI10.1007/978-3-319-07139-8
SpringerChamHeidelbergNewYorkDordrechtLondon
LibraryofCongressControlNumber:2014942642
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Preface
Thisbookistheresultofthedeepinvolvementoftheauthorsinthedevelopmentof
EDA tools, SystemVerilog Assertion standardization, and many years of practical
experience.Oneofthegoalsofthisbookistoexposetheoralknowhowcirculated
among design and verification engineers which has never been written down in
its full extent. The book thus contains many practical examples and exercises
illustrating the various concepts and semantics of the SystemVerilog assertion
language. Much attention is given to discussing efficiency of assertion forms in
simulationandformalverification.Wedidourbesttovalidatealltheexamples,but
there are hundreds of them and not all features could be validated since they have
notyetbeenimplementedinEDAtools.Therefore,wewillbegratefultoreadersfor
pointingtousanyneededcorrections.Thebookiswritteninawaythatwebelieve
serveswellboththeusersofSystemVerilogassertionsinsimulationandalsothose
who practice formal verification (model checking). Compared to previous books
covering SystemVerilog assertions we include in detail the most recent features
that appeared in the IEEE 1800–2009 SystemVerilog Standard and were further
improved and enhanced in the recent IEEE 1800–2012 Standard. In particular, it
concerns the new encapsulation construct “checker” and checker libraries, Linear
TemporalLogicoperators,andsemanticsandusageinformalverification.However,
forintegralunderstandingwepresenttheassertionlanguageanditsapplicationsin
fulldetail.
This second edition of the book not only introduces the enhancements and
corrections present in the 2012 SystemVerilog standard, but also it is reorganized
inawaythatfacilitatesbasicassertionunderstanding,initialdeploymentinsimple
forms, fully detailed exposition of the power of the language, and deployment in
simulationandformalverification.Nottomentioncorrectionstoseveralerrorsand
inconsistenciesinthefirstedition.
The book is divided into sixparts.These parts are organized from introductory
toadvanced,aswellasseparatingasmuchaspossibleaspectsrelatedtosimulation
andformalverification.PartIisenoughtogetbasicunderstandingofSystemVerilog
v
vi Preface
Assertions.By adding Part II,the reader should be able to write typical assertions
and use them in simulation. Parts III and IV provide deep understanding of the
assertion language. Part V is dedicated to formal verification and provides formal
semanticsofthelanguage.Finally,PartVIdealswiththedesignofcheckerlibraries
and the use of checkers in formal verification. The Appendix concisely describes
samplingofvariables,asitisdifferentthanintheprevious2009Standardandthus
the1steditionofthisbook.
Part I, Opening, is an extended introduction to assertions, their use in simula-
tion,formalverificationandothertools,andtheirmeaninginrelationtotherestof
theSystemVeriloglanguage.
Chapter 1 introduces the concept of assertions, their place in history of design
verification,anddiscussestheuseofassertionsinhardwaredesignandverification
flow.
Chapter 2 introduces minimal necessary concepts from the SystemVerilog
language,otherthanassertions,thatareusefulforunderstandingassertionsandtheir
usage.
Chapter 3 provides the basics of SystemVerilog simulation semantics. It dis-
cusseshowSystemVerilogprocessesareexecutedinthevariousschedulingregions
andhowassertionsinteractwiththesimulationofthedesignmodel.
PartII,BasicAssertions,goes intosufficientdetailsoftheassertionlanguage
tounderstandandwritesimpleassertions.
Chapter4describesthedifferentassertionstatementsthatcanbeusedtoascertain
correctness, provide constraints and collect coverage, both in clocked concurrent
andunclockedimmediate(simpleanddeferred)forms.
Chapters5and6providethebasicinformationonhowtowritesimpleproperties
andsequencesthatformtheoperationalcoreofassertions.
Chapter7exposessystemfunctionsthathelptowriteassertionswithouthaving
to resort to additional procedural code and introduces several system tasks for
controlling assertion and action block execution. The main difference with the
earlier version of the standard is the introduction of a more powerful function to
detect the presence of x and z signal values and a unified task for controlling the
executionofassertions.
PartIIIMetalanguageConstructs
Chapter 8 considers reusability of assertion bodies by showing how Boolean
expressions, sequences, and properties can be defined and parameterized for later
reuse.
Chapter9providesadetailedexpositionoftheencapsulationconstruct“checker.”
Thisconstructisthebasisforformingwhatcouldbecalledasuperassertion,that
is, an assertion entity that combines procedural code, modeling variables, variable
assignments, coverage, assertion and assumption statements into one reusable
parameterized unit. Checkers now allow different kinds of procedures as well as
continuousassignmentswhichwereillegalpreviously.Samplingasdescribedinthe
Appendixhasalsochangedincheckers.
Preface vii
PartIVAdvancedAssertions
Chapters 10 and 11 delve into the full intricacies of property and sequence
operators. The former chapter also defines precisely the notions of vacuous and
non-vacuousevaluationsofassertions.
Chapter 12 describes sampling clocks, clock flow through assertions, and
multiclockedassertions.
Chapter 13 provides information on the ways synchronous property evaluation
canbeterminatedwithsuccessorfailureusingasynchronousandsynchronousabort
operators.
Chapter 14 shows how to use concurrent assertions inside always procedures,
andhowtheleadingclockisinferred.Italsodescribeshowevaluationattemptsare
starteddependingontheconditionalandloopingstatementsinsideprocedures.
Chapter15apologizesforlocalvariables,butinfactshowshowlocalvariables
providemuchflexibilitytoassertions,especiallyinsimulation.
Chapter16exposesthevariousformsoflocalvariabledeclarationsandrulesof
deployment,includingspeciallocalvariableargumentstopropertiesandsequences.
Chapter 17 shows another facet of SystemVerilog assertions, that of recursive
properties. They provide an alternate and succinct form for expressing complex
properties.
Chapter 18 discusses coverage collection that is needed to measure the verifi-
cation progress. Two forms are described, using assertion cover statements alone
andincombinationwithtestbenchcovergroupstoformpowerfuldatacollection
constructs.
Chapter 19 briefly introduces some techniques for debugging assertions, inde-
pendently of services provided by specific EDA tools, and then discusses the
efficiencyofvariousassertionformsinsimulationandformalverification.
PartVFormalVerification
Chapter 20 provides an introduction to the treatment of assertions in formal
verification by discussing the different ways formal verification can proceed and
itsroleintheverificationprocess.
Chapter 21 exposes details of the models and algorithms used in formal
verification,inparticular,modelchecking.
Chapter 22 gives the theoretical base for full and precise understanding of
the meaning of assertions. This chapter is particularly important to anyone who
implementssomeformofanassertionverificationengine,simulationorformal.
PartVI,AdvancedCheckers,isprimarilyconcernedwithdevelopingeffective
reusableverificationobjects.
Chapter 23 shows how checkers can be used effectively in formal verification.
Thechapteralsoprovidesdeeperunderstandingofthebehaviorofcheckervariables.
Chapter24discusseshowtocreatelibrariesofverificationstatementsbasedon
assertions, from simple let or property based forms, to the complex ones using
checkerencapsulation.
We did our best to verify and compile each and every example and verify the
text, however, not all SystemVerilog constructs introduced in the 2009 and 2012
standardsaresupportedbycommercialtools.Inspiteofthegreatimprovementsin
viii Preface
the 2012 SystemVerilog LRM there are still some incomplete or ambiguous points
in the language. We do not guarantee correctness and do not assume any liability
andresponsibilityforissuesresultingfromapplyingthetechniquesdescribedinthe
book.
Acknowledgments
The authors wish to express their gratefulness to many people who reviewed
sections of the draft of the first edition of the book which served as the basis for
thisimprovededition,inparticular,toShalomBresticker(Intel),LenaKorchemny
(Inango), Jacob Katz (Intel),ScottLittle(Freescale),Zeljko Zilic(McGillUniver-
sity), Christian Berthet (ST Microelectronics), Chris Spear (Synopsys), and Erik
Seligman (Intel). Furthermore, the book was mostly written over the weekends,
vacations,andevenings,hencewearethankfultoourspousesandfamiliesfortheir
patienceandunderstanding.Wealsoacknowledgethesupportofouremployersin
thisendeavor.
Worcester,MA,USA EduardCerny
Newton,MA,USA SurrendraDudani
Austin,TX,USA JohnHavlicek
KfarSaba,Israel DmitryKorchemny
Contents
PartI Opening
1 Introduction................................................................. 3
1.1 TheConceptofAssertion............................................ 4
1.2 AssertionsinDesignMethodology.................................. 9
1.2.1 UsingAssertionsforHighLevelModel................... 10
1.2.2 UsingAssertionsforRTLModels......................... 14
1.2.3 UsingAssertionsBeyondRTL............................. 17
1.3 AssertionsinSystemVerilog......................................... 18
1.4 CheckingAssertions ................................................. 21
1.4.1 CheckingAssertionsinSimulation........................ 21
1.4.2 CheckingAssertionsUsingHardwareAcceleration...... 22
1.4.3 CheckingAssertionsUsingFormalVerification.......... 23
1.4.4 AssertionEfficiency........................................ 24
1.5 AssertionReuse ...................................................... 24
1.6 SVAandPSL......................................................... 27
Exercises ..................................................................... 28
2 SystemVerilogLanguageOverview....................................... 31
2.1 CompilationandElaboration ........................................ 31
2.2 SystemVerilogProcedures........................................... 33
2.2.1 SpecializedAlwaysProcedures............................ 33
2.2.2 FinalProcedure............................................. 35
2.3 ClockingBlocks...................................................... 36
2.3.1 ClockingBlockDeclaration................................ 36
2.3.2 DefaultClocking............................................ 37
2.4 Interfaces ............................................................. 38
2.5 Programs.............................................................. 40
2.6 Packages.............................................................. 41
Exercises ..................................................................... 43
ix