Suitability of Tile-Based Rendering for Low-Power 3D Graphics Accelerators

163 Pages·2007·1.38 MB·English

Suitability of Tile-Based Rendering for
Low-Power 3D Graphics Accelerators

Suitability of Tile-Based Rendering for
Low-Power 3D Graphics Accelerators
PROEFSCHRIFT
terverkrijging vandegraadvandoctor
aandeTechnischeUniversiteit Delft,
opgezagvandeRectorMagnificusprof.dr.ir. J.T.Fokkema,
voorzittervanhetCollegevoorPromoties,
inhetopenbaarteverdedigen
opmaandag29oktober2007om12:30uur
door
IosifANTOCHI
inginer
Universitatea Politehnica Bucures¸ti
geboren teBoekarest, Roemenie
Ditproefschrift isgoedgekeurd doordepromotoren:
Prof.dr.S.Vassiliadis†
Prof.dr.K.G.W.Goossens
Samenstelling promotiecommissie:
RectorMagnificus, voorzitter Technische UniversiteitDelft
Prof. dr.S.Vassiliadis†, promotor Technische UniversiteitDelft
Prof. dr.K.G.W.Goossens, promotor Technische UniversiteitDelft
Dr.B.H.H.Juurlink Technische UniversiteitDelft
Prof. dr.L.K.Nanver Technische UniversiteitDelft
Prof. dr.H.A.G.Wijshoff Universiteit Leiden
Prof. dr.J.Takala TampereUniversityofTechnology
Dr.A.Pimentel Universiteit vanAmsterdam
Dr.K.Pulli NokiaResearchCenter,PaloAlto
Dr. B.H.H. Juurlink heeft als begeleider in belangrijke mate aan de totstand-
komingvanhetproefschrift bijgedragen.
ISBN:978-90-807957-6-1
Keywords: 3D Graphics Accelerators, Tile-based Rendering, Low-Power
GraphicsArchitectures
Copyright (cid:13)c 2007I.Antochi
All rights reserved. No part of this publication may be reproduced, stored in
a retrieval system, or transmitted, in any form or by any means, electronic,
mechanical, photocopying, recording, orotherwise, without permission ofthe
author.
PrintedintheNetherlands
Thisdissertationisdedicatedto Claudia
and myfamily,
foralltheirunderstandingandsupportover theyears.

Suitability of Tile-Based Rendering for
Low-Power 3D Graphics Accelerators
IosifANTOCHI
Abstract
I
n this dissertation, we address low-power high performance 3D graphics
accelerator architectures. The purpose of these accelerators is to relieve
theburdenofgraphicalcomputations fromthemainprocessorandalsoto
achieveabetterenergyefficiencythancanbeachievedbyexecutingthesecom-
putations on the main processor. Since external data traffic is a major source
of power consumption and because usually the rasterization stage of the 3D
graphics pipeline requires the highest amount of data traffic, in this disserta-
tionweespeciallyfocusonthisstageofthegraphics pipeline. Anotherreason
forfocusingontherasterizationstageisthatitrequiresmoreprocessingpower
thantheotherstagesbecausetheoperationsarepixel-based. Apromisingtech-
niquetoreducetheexternaldatatrafficintherasterizationstageofthegraphics
pipeline is tile-based rendering. This technique decomposes ascene into tiles
and renders thetiles one by one. Thisallows the colorcomponents and zval-
ues of one tile to be stored in small, on-chip buffers, so that only the pixels
visible in the final scene need to be stored in the external framebuffer. Tile-
basedaccelerators, however,require largescenebufferstostoretheprimitives
to be rendered. While there have been studies related to the tile-based ren-
dering paradigm forhighperformance systems, wearespecifically discussing
thesuitabilityoftile-based3Dgraphicsacceleratorsforlow-powerdevices. In
ordertoevaluatevariouslow-power3Dgraphicsarchitectures wefirstpresent
GraalBench, a set of 3D graphics workloads representative for contemporary
and emerging mobile devices. Furthermore, we propose several scene and
state management algorithms fortile-based renderers. Thereafter, weanalyze
theperformance oftile-based rendererscomparedtothatof traditional render-
ers and we also determine the influence of the tile size on the amount of the
data-trafficrequiredfortherasterizationstageofatile-basedrenderer. Inorder
to reduce even more the data traffic between the main memory and graphics
accelerators, and to exploit the high temporal and spatial locality of texture
accesses, wehavealsoinvestigated severalcache structures. Ourresults show
that the proposed algorithms for tile-based renderers can effectively decrease
the data traffic and computational requirements for the rasterization stage of
the3Dgraphicspipeline.
i

Acknowledgments
During the time that I was performing the research described in this disserta-
tion, Icameacross manypeople whohave supported andassisted mewithout
whomitwouldhavebeenmuchhardertoproducethisdissertation.
First of all, I would like to thank my supervisor Ben Juurlink and my pro-
motors Stamatis Vassiliadis and Kees Goossens for their endless support and
guidance. They succeeded to provide me not only research knowledge, but
alsoabetterunderstanding ofreallife. AlthoughStamatis isnolongeramong
us,hispresence livesonthrough eachCEmember.
Furthermore, I would like to thank my officemates, Dan and Pepijn for our
inspiring technical and also less technical discussions. I would like to thank
Elena for her encouragement and positive thinking that helped me over the
years.
Ihadalsofounditveryenjoyabletoworkwithandtotalktoeverymemberof
the Computer Engineering Laboratory. I am in debt to the “older” generation
(Pyrrhos, Casper, Stephan) for introducing me into the geeky spirit of Com-
puterEngineering, andalso tothenewergeneration which kept meuptodate
withvariousinteresting topics.
I am also indebted to the small Romanian community from the Netherlands
thathelpedmeovercomemyhomesickness andalsoforbeingwithmewhenI
stumbledacrossvariousproblems.
Finally, special thanks go to Claudia for her understanding and support over
theyears.
I.Antochi Delft,TheNetherlands, 2007
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