STUDIES ON CMOS DIGITAL-TO-ANALOG CONVERTERS

276 Pages·2000·3.97 MB·English

Linköping Studies in Science and Technology
Dissertation No. 667
STUDIES ON CMOS
DIGITAL-TO-ANALOG CONVERTERS
J Jacob Wikner
Department of Electrical Engineering
Linköpings universitet, SE-581 83 Linköping, Sweden
Linköping 2001

Linköping Studies in Science and Technology
Dissertation No. 667
STUDIES ON CMOS
DIGITAL-TO-ANALOG CONVERTERS
J Jacob Wikner
Department of Electrical Engineering
Linköpings universitet, SE-581 83 Linköping, Sweden
Linköping 2001
Studies on CMOS Digital-to-Analog Converters
Copyright © 2001 J Jacob Wikner
Department of Electrical Engineering
Linköpings universitet,
SE-581 83 Linköping
ISBN91-7219-910-5 ISSN 0345-7524
Printed in Sweden by UniTryck, Linköping, 2001
Abstract
In this thesis we present an overview and study on digital-to-analog converters (DAC), mainly
for communications applications. Especially, we look at some digital subscriber line (DSL)
specificationsandcommunicationovertwisted-pairchannels.Itispointedoutthattherequired
resolution on the DACs in such systems is in the order of 12 to 14 bits of resolution. At the
same time the bandwidth stretches from below MHz to several tens of MHz. These figures are
the guiding specification throughout the thesis.
In this work we consider many of converter architectures and chips. The current-steering DAC
is pointed out as a suitable converter for both high speed and high resolution. We also investi-
gate the oversampling DAC (OSDAC) and discuss its properties in detail.
The performance of the converters is limited by both static and dynamic errors. The static
errors are usually caused by mismatch of the components and limit the accuracy at low speed.
The static performance is often described by measures of differential and integral nonlineari-
ties, (DNL and INL). For communication applications these measures are not especially used
for characterization of the DACs. Instead, the dynamic errors, such as settling errors, glitches,
etc., are more important since they increase with higher sample rates and signal frequencies.
To analyze the effect of errors it is usually easier to consider the DAC’s behavior in frequency
domain using measures, such as the spurious-free dynamic range (SFDR) and signal-to-noise-
and-distortion ratio (SFDR). These measures are normally derived from the output spectrum
when a sinusoidal input signal is used. In some applications it may be necessary to use several
sinusoidal tones to get relevant measures. Two common measures are the multi-tone power
ratio (MTPR) and the peak-to-average ratio (PAR). The PAR of the input signal affects the
maximum signal-to-noise ratio (SNR) of the converter and a small PAR is preferred since it
maximizes the SNR.
To help us understand how to design a converter several models and algorithmic expressions
are presented. The models are verified through simulations and partially through measure-
ments and experiments. Some of the most dominating error sources in converters, such as lim-
ited output impedance, device mismatch, and noise, are highlighted. We give suggestions on
how to reduce and minimize the influence of these types of error sources. These techniques
involve calibration and randomization, as well as cancellation through for example pre-distor-
tion algorithms. We also present the basics of dynamic element matching techniques (DEM).
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Abstract 6
The usage of the models is to reduce the design time and get a good understanding for funda-
mental limitations on performence. Instead of time-consuming circuit-level simulations, we
point out the behavioral-level and algorithmic-level simulation of the converters. Most of the
models have been described in languages, such as Matlab and Mathematica.
Several chips have been implementated in CMOS and some improvement in performance has
been measured from generation to generation. By comparing two similar DACs with small
variations, we show how the performance of the converter depends on typical mismatches in
the layout. The measurement results are analyzed by using simulation results from the pro-
posed DAC models. By identifying distortion terms we can partially determine matching
errors, output impedance, and parasitic impedance.
Often the design of DACs is focused on the actual converter alone. We emphasize the need for
a broad view, where a more integrated digital/analog design is considered. The typical mixed-
signal andanalogcircuits, e.g.,DAC,ADC, filters,amplifiers.Ine.g.atransceivermustbeco-
optimized. Analog circuits mix with digital circuits and signal processing algorithms on the
same chip and we have to carefully investigate how the different subcircuits interact.
We discuss the design and implementation of current-steering DACs for wideband applica-
tions. Different architectures are outlined and we emphasize the segmented DAC as the most
suitable converter structure for high speed and high resolution. Here, a key design issue is to
find the proper number of bits to encode into a thermometer code. This increases the digital
contents of the DAC, but reduces the glitches.
Further,wediscussissuesinvolvingdesignofOSDACs.Weusethesigma-deltamodulatorsto
reducethenumberofbitsrepresentingthedigitalsignalandthenweusesmallandsimpleana-
log circuits, which can be optimized with respect to the device. As a design case, we select an
OSDAC for ADSL applications. It is found that the requirements on the OSDAC are tough. It
is emphasized that the design of an oversampling converter essentially is a filter design prob-
lem. There is a large number of possible trade-offs that can be made between the different
building blocks in the OSDAC. Here, the key design issue is to define a proper cost function
that lets us find a good overall solution.
The thesis also presents some special converter architectures. A DAC’s behavior for different
inputcodesisexamined.Thethermometercodeistheoptimumcodeintermsofglitchesandis
simplestforallowinginterdigitizedlayoutstructures.However,forlargernumberofbitsinthe
encoder becomes rather large and complex. In the thesis we presentmore work where a linear
codeisused.Thiscodeendsupin-betweenthethermometercodeandthebinarycodeinterms
of performance and complexity.
Acknowledgment
Therearesomanytothankforsupportingtheworkthathasbeencompressedintothisthesis.I
thank all the members that have co-worked with me at Electronics Systems and Electronic
Devices at Linköping University and Ericsson Microelectronics AB, Ericsson Radio Systems
AB, and Ericsson Telecom AB. The head of the Electronics Systems group at the Department
of Electrical Engineering, Linköping University, Prof. Dr. Lars Wanhammar, is acknowledged
for the support and the encouragement.
I especially want to thank Dr. Mikael Gustavsson and Dr. Nianxiong Tan, Globespan, Inc., for
their help and the needed boost throughout my work. Thanks to Dr. Yonghong Gao, Ericsson
Radio Systems AB, for the great help with oversampling converters. Thanks to Peter Peters-
son, Ericsson Radio Systems AB, for the help with measurements on my first chips. I want to
thank Dr. Gunnar Björklund at the Ericsson Microelectronics Research Center for his indus-
trialcompetenceandclearviewonresearchissues.Furtheron,IwanttothankthesmallErics-
son Microelectronics group at Linköping with which I have been working.
A large portion of Thank You to my parents, Christina and Lars-Erik, who – I guess – have
always believed in (although not understood) what I have been doing. Thanks for all the com-
puters you have given me throughout the years.
Thank you, Ulrica, for still letting me come home after all long working nights.
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Acknowledgment 8
Abbreviations and Acronyms
AC Alternating current
A/D Analog-to-digital
ADSL Asymmetric digital subscriber line
ADC Analog-to-digital converter
AFE Analog front-end
AHDL Analog high-level description language
AP Allpass
APK Amplitude-phase keying
ASK Amplitude-shift keying
ATM Asynchronous transfer mode
AWGN Additive white Gaussian noise
BER Bit error rate
bit Binary digit
BP Bandpass
BSIM Simulation model
CAP Carrierless amplitude and phase
CD Compact disc
CDMA Carrierless division multiplexing access
CFT Clock feedthrough
CMOS Complementary metal-oxide semiconductor
CO Central office
CPE Customer’s premises equipment
CSFR Clock-to-signal frequency ratio
D/A Digital-to-analog
DAC Digital-to-analog converter
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Abbreviations and Acronyms 10
dB Decibel
dBFS Decibel with respect to the full scale level
DC Direct current
DCVSL Differential clocking style logic
DEM Dynamic element matching
DMT Discrete multi-tone
DR Dynamic range
DSL Digital subscriber line
DSP Digital signal processor
EDGE Enhanced data for GSM evolution
ENOB Effective number of bits
ERB Effective resolution bandwidth
FDM Frequency-division multiplexing
FEXT Far-end crosstalk
FFT Fast Fourier transform
FIR Finite-length impulse response
FRDEM Full randomization dynamic element matching
FS Full scale
FSK Freqsuency-shift keying
GCN General cubic network
GPRS General packet radio service
GSM Global system mobile telephony
GPIB General Purpose Interface Bus
GPRS General packet radio service
HD Harmonic distortion
HDL High-level description language
HDTV High-definition television
HP High pass
IFFT Inverse fast Fourier transform
IFIR Interpolated finite-length impulse response filter
IIR Infinite-length impulse response
IMD Intermodulation distortion
I/O Input / output
I/Q In-phase and quadrature-phase
ISDN Integrated services digital network
LP Lowpass