Stratix II GX Device Handbook

1486 Pages·2009·13.84 MB·English

by  Altera Corporation

Stratix II GX Device Handbook, Volume 1
101 Innovation Drive
San Jose, CA 95134
www.altera.com
SIIGX5V1-4.4
Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-
ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al-
tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liabil-
ity arising out of the application or use of any information, product, or service described herein except as
expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest ver-
sion of device specifications before relying on any published information and before placing orders for
products or services.
ii Altera Corporation
Contents
Section I. Stratix II GX Device Data Sheet
Chapter 1. Introduction
Features ...................................................................................................................................................1–1
Referenced Document...........................................................................................................................1–5
Document Revision History.................................................................................................................1–5
Chapter 2. Stratix II GX Architecture
Transceivers............................................................................................................................................2–1
Transmitter Path ...............................................................................................................................2–4
Receiver Path...................................................................................................................................2–14
Loopback Modes ............................................................................................................................2–30
Transceiver Clocking .....................................................................................................................2–35
Other Transceiver Features...........................................................................................................2–41
Logic Array Blocks ..............................................................................................................................2–44
LAB Interconnects ..........................................................................................................................2–45
LAB Control Signals.......................................................................................................................2–46
Adaptive Logic Modules ....................................................................................................................2–48
ALM Operating Modes .................................................................................................................2–50
Arithmetic Mode ............................................................................................................................2–55
Shared Arithmetic Mode ...............................................................................................................2–58
Shared Arithmetic Chain...............................................................................................................2–60
Register Chain.................................................................................................................................2–61
Clear and Preset Logic Control ....................................................................................................2–63
MultiTrack Interconnect .....................................................................................................................2–63
TriMatrix Memory...............................................................................................................................2–69
M512 RAM Block............................................................................................................................2–70
M4K RAM Blocks ...........................................................................................................................2–73
M-RAM Block .................................................................................................................................2–75
Digital Signal Processing (DSP) Block ..............................................................................................2–81
Modes of Operation .......................................................................................................................2–85
DSP Block Interface ........................................................................................................................2–85
PLLs and Clock Networks..................................................................................................................2–89
Global and Hierarchical Clocking................................................................................................2–89
Enhanced and Fast PLLs ...............................................................................................................2–97
Enhanced PLLs .............................................................................................................................2–109
Fast PLLs........................................................................................................................................2–109
I/O Structure ......................................................................................................................................2–110
Double Data Rate I/O Pins .........................................................................................................2–118
External RAM Interfacing ...........................................................................................................2–122
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Contents Stratix II GX Device Handbook, Volume 1
Programmable Drive Strength ...................................................................................................2–124
Open-Drain Output......................................................................................................................2–125
Bus Hold ........................................................................................................................................2–125
Programmable Pull-Up Resistor ................................................................................................2–126
Advanced I/O Standard Support ..............................................................................................2–126
On-Chip Termination ..................................................................................................................2–130
MultiVolt I/O Interface ...............................................................................................................2–133
High-Speed Differential I/O with DPA Support..........................................................................2–136
Dedicated Circuitry with DPA Support....................................................................................2–138
Fast PLL and Channel Layout ....................................................................................................2–141
Referenced Documents .....................................................................................................................2–142
Document Revision History.............................................................................................................2–143
Chapter 3. Configuration & Testing
IEEE Std. 1149.1 JTAG Boundary-Scan Support ...............................................................................3–1
SignalTap II Embedded Logic Analyzer ............................................................................................3–3
Configuration .........................................................................................................................................3–3
Operating Modes..............................................................................................................................3–4
Configuration Schemes ...................................................................................................................3–6
Device Security Using Configuration Bitstream Encryption .....................................................3–7
Device Configuration Data Decompression.................................................................................3–7
Remote System Upgrades ...............................................................................................................3–8
Configuring Stratix II GX FPGAs with JRunner ..........................................................................3–8
Programming Serial Configuration Devices with SRunner.......................................................3–9
Configuring Stratix II FPGAs with the MicroBlaster Driver .....................................................3–9
PLL Reconfiguration ........................................................................................................................3–9
Temperature Sensing Diode (TSD) ...................................................................................................3–10
Automated Single Event Upset (SEU) Detection ............................................................................3–12
Custom-Built Circuitry ..................................................................................................................3–12
Software Interface...........................................................................................................................3–12
Referenced Documents .......................................................................................................................3–13
Document Revision History...............................................................................................................3–13
Chapter 4. DC and Switching Characteristics
Operating Conditions ...........................................................................................................................4–1
Absolute Maximum Ratings ...........................................................................................................4–1
Recommended Operating Conditions ..........................................................................................4–2
Transceiver Block Characteristics ..................................................................................................4–3
DC Electrical Characteristics ........................................................................................................4–42
I/O Standard Specifications .........................................................................................................4–43
Bus Hold Specifications.................................................................................................................4–56
On-Chip Termination Specifications ...........................................................................................4–56
Pin Capacitance ..............................................................................................................................4–58
Power Consumption ...........................................................................................................................4–59
Timing Model.......................................................................................................................................4–59
Preliminary and Final Timing ......................................................................................................4–59
I/O Timing Measurement Methodology....................................................................................4–60
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Stratix II GX Device Handbook, Volume 1 Contents
Internal Timing Parameters ..........................................................................................................4–69
StratixIIGX Clock Timing Parameters .......................................................................................4–76
Clock Network Skew Adders .......................................................................................................4–81
IOE Programmable Delay .............................................................................................................4–82
Default Capacitive Loading of Different I/O Standards..........................................................4–83
I/O Delays.......................................................................................................................................4–84
Maximum Input and Output Clock Toggle Rate.......................................................................4–98
Duty Cycle Distortion .......................................................................................................................4–118
DCD Measurement Techniques .................................................................................................4–118
High-Speed I/O Specifications........................................................................................................4–126
PLL Timing Specifications................................................................................................................4–130
External Memory Interface Specifications .....................................................................................4–132
JTAG Timing Specifications .............................................................................................................4–134
Referenced Documents .....................................................................................................................4–136
Document Revision History.............................................................................................................4–137
Chapter 5. Reference and Ordering Information
Device Pin-Outs .....................................................................................................................................5–1
Ordering Information ...........................................................................................................................5–1
Referenced Documents .........................................................................................................................5–2
Document Revision History.................................................................................................................5–2
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Contents Stratix II GX Device Handbook, Volume 1
vi Altera Corporation
Chapter Revision Dates
The chapters in this book, Stratix II GX Device Handbook, Volume1, were revised on the following
dates. Where chapters or groups of chapters are available separately, part numbers are listed.
Chapter 1. Introduction
Revised: October 2007
Part number: SIIGX51001-1.6
Chapter 2. Stratix II GX Architecture
Revised: October 2007
Part number: SIIGX51003-2.2
Chapter 3. Configuration & Testing
Revised: October 2007
Part number: SIIGX51005-1.4
Chapter 4. DC and Switching Characteristics
Revised: June 2009
Part number: SIIGX51006-4.6
Chapter 5. Reference and Ordering Information
Revised: August 2007
Part number: SIIGX51007-1.3
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Chapter Revision Dates Stratix II GX Device Handbook, Volume1
viii Altera Corporation
About this Handbook
This handbook provides comprehensive information about the Altera®
Stratix II GX family of devices.
How to Contact For the most up-to-date information about Altera products, refer to the
following table.
Altera
Contact
Contact (1) Address
Method
Technical support Website www.altera.com/support
Technical training Website www.altera.com/training
Email [email protected]
Product literature Email www.altera.com/literature
Altera literature services Website [email protected]
Non-technical support (General) Email [email protected]
(Software Licensing)
Email [email protected]
Note to table:
(1) You can also contact your local Altera sales office or sales representative.
Typographic This document uses the typographic conventions shown below.
Conventions
Visual Cue Meaning
Bold Type with Initial Command names, dialog box titles, checkbox options, and dialog box options are
Capital Letters shown in bold, initial capital letters. Example: Save As dialog box.
bold type External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold
type. Examples: f , \qdesigns directory, d: drive, chiptrip.gdf file.
MAX
Italic Type with Initial Capital Document titles are shown in italic type with initial capital letters. Example: AN 75:
Letters High-Speed Board Design.
Altera Corporation ix
Preliminary
Typographic Conventions Stratix II GX Device Handbook, Volume 1
Visual Cue Meaning
Italic type Internal timing parameters and variables are shown in italic type.
Examples: t , n + 1.
PIA
Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example: <file name>, <project name>.pof file.
Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title” References to sections within a document and titles of on-line help topics are
shown in quotation marks. Example: “Typographic Conventions.”
Courier type Signal and port names are shown in lowercase Courier type. Examples: data1,
tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an
actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in
Courier.
1., 2., 3., and Numbered steps are used in a list of items when the sequence of the items is
a., b., c., etc. important, such as the steps listed in a procedure.
■ ● (cid:129) Bullets are used in a list of items when the sequence of the items is not important.
v The checkmark indicates a procedure that consists of one step only.
1 The hand points to information that requires special attention.
c A caution calls attention to a condition or possible situation that can damage or
destroy the product or the user’s work.
w A warning calls attention to a condition or possible situation that can cause injury
to the user.
r The angled arrow indicates you should press the Enter key.
f The feet direct you to more information on a particular topic.
x Altera Corporation
Preliminary