Step-by-step Functional Verification with SystemVerilog and OVM PDF
520 Pages·2008·26.371 MB·English
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NOTE: Examples in this book can be downloaded from SiMantis Inc. website.BACK-COVER QUOTES:"This detailed, step-by-step guide provides a thorough introduction to SystemVerilog and the Open Verification Methodology (OVM). With many examples and clear descriptions, it should be helpful to anyone involved in IC functional verification." Richard Goering, Editor-in-Chief , SCDsource "Dr. Iman brings together all the essential elements to understand the use and application of OVM. Those with limited SystemVerilog knowledge will find Step-by-Step Functional Verification with SystemVerilog and OVM offers a complete introduction to SystemVerilog, and the SystemVerilog-savvy will find this a comprehensive OVM reference. This book has everything design and verification engineers would want to know to apply OVM to their most pressing challenges." Dennis Brophy , Director of Strategic Business Development , Mentor Graphics "The author of this book is well known in the design community as a leader in the verification space. SystemVerilog has provided a major step in our capability to verify our designs, especially in today’s world of 40 million gate SoCs. The combination has produced a very thorough step by step guide to the latest in verification methodology." Gary Smith, Chief Analyst, Gary Smith EDA "The Open Verification Methodology (OVM) is one of the most quickly and widely adopted new solutions ever for verifying complex chips. This book walks the reader through the OVM as well as the SystemVerilog language constructs upon which it is built. The breadth of Step-by-Step Functional Verification with SystemVerilog and OVM and its pragmatic approach make it an invaluable resource for both novice and experienced verification engineers." Ted Vucurevich, CTO, Cadence
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