Stand-Alone USB Transceiver Chip Silicon (Rev - Texas Instruments

66 Pages·2016·1.15 MB·English

TUSB1210
ZHCSKM0J – NOVEMBER 2009 – REVISED JULY 2021
TUSB1210 独立 USB 收发器硅芯片
1 特性 2 应用
• USB2.0 PHY 收发器芯片，可通过 ULPI 接口连接 • 手机
USB 控制器，完全符合： • 便携式计算机
• 平板电脑设备
– 通用串行总线规范 2.0 版
• 视频游戏机
– USB 2.0 规范移动附录 1.3 版
• 台式机
– UTMI+ 低引脚接口 (ULPI) 规范 1.1 版
• 便携式音乐播放器
– ULPI 12 引脚 SDR 接口
• DP/DM 线路外部元件补偿（专利号 US7965100 3 说明
B1）
TUSB1210 是一款 USB2.0 收发器芯片，可通过 ULPI
• 具有连接主机、外设和 OTG 器件内核的接口；针
接口连接到 USB 控制器。该器件支持所有 USB2.0 数
对便携式设备或具有内置 USB OTG 器件内核的系
据速率（高速 480Mbps、全速 12Mbps 以及低速
统 ASIC 进行了优化
1.5Mbps），且兼容主机和外设模式。该器件还支持
• 完整的 USB OTG 物理前端，支持主机协商协议
UART 模式和传统的 ULPI 串行模式。TUSB1210 还支
(HNP) 和会话请求协议 (SRP)
持 USB2.0 规范的 OTG（1.3 版）可选附录，包括
• V 过压保护电路系统可在 –2V 至 20V 的电压范
BUS HNP 和 SRP。
围内保护 V 引脚
BUS
• 内部 5V 短路保护功能，可防止 DP、DM 和 ID 引 发送器中的 DP/DM 外部元件补偿可对串联阻抗中的变
脚通过电缆短接至 V 引脚 化进行补偿，以匹配数据线路阻抗和接收器输入端阻
BUS
• ULPI 接口： 抗，限制数据反射，从而改善眼图。
– I/O 接口 (1.8V) 针对无端接 50Ω 线路阻抗进行 器件信息(1)
了优化
器件型号 封装 封装尺寸（标称值）
– ULPI 时钟引脚 (60MHz) 支持输入和输出时钟配
TUSB1210 VQFN (32) 5.00mm × 5.00mm
置
– 符合 ULPI 标准的完全可编程寄存器集 (1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
• 完全工业级工作温度范围：–40°C 至 85°C 录。
• 采用 32 引脚 Quad Flat No Lead [QFN (RHB)] 封
装
TUSB1210
(PHY)
ULPI Interface
USB 2.0 USB 2.0 HOST,
LINK OTG, or Device
图
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSE09
TUSB1210
ZHCSKM0J – NOVEMBER 2009 – REVISED JULY 2021 www.ti.com.cn
Table of Contents
1 特性...................................................................................1 7.5 Register Map.............................................................22
2 应用...................................................................................1 8 Application and Implementation..................................53
3 说明...................................................................................1 8.1 Application Information.............................................53
4 Revision History..............................................................2 8.2 Typical Application....................................................53
5 Pin Configuration and Functions...................................4 8.3 External Components...............................................57
6 Specifications..................................................................6 9 Power Supply Recommendations................................58
6.1 Absolute Maximum Ratings........................................6 9.1 TUSB1210 Power Supply.........................................58
6.2 ESD Ratings...............................................................6 9.2 Ground......................................................................58
6.3 Recommended Operating Conditions.........................6 9.3 Power Providers........................................................58
6.4 Thermal Information....................................................7 9.4 Power Modules.........................................................58
6.5 Analog I/O Electrical Characteristics...........................7 9.5 Power Consumption..................................................59
6.6 Digital I/O Electrical Characteristics............................7 10 Layout...........................................................................60
6.7 Digital IO Pins (Non-ULPI)..........................................7 10.1 TUSB121x USB2.0 Product Family Board
6.8 PHY Electrical Characteristics....................................8 Layout Recommendations...........................................60
6.9 Pullup/Pulldown Resistors........................................10 10.2 Layout Guidelines...................................................62
6.10 OTG Electrical Characteristics................................10 10.3 Layout Example......................................................62
6.11 OTG ID Electrical.....................................................11 11 Device and Documentation Support..........................63
6.12 Power Characteristics.............................................11 11.1 Device Support........................................................63
6.13 Switching Characteristics........................................12 11.2 Documentation Support..........................................63
6.14 Timing Requirements..............................................13 11.3 接收文档更新通知...................................................63
6.15 Typical Characteristics............................................15 11.4 支持资源..................................................................63
7 Detailed Description......................................................16 11.5 Trademarks.............................................................63
7.1 Overview...................................................................16 11.6 Electrostatic Discharge Caution..............................63
7.2 Functional Block Diagram.........................................16 11.7 术语表.....................................................................63
7.3 Feature Description...................................................17 12 Mechanical, Packaging, and Orderable
7.4 Device Functional Modes..........................................20 Information....................................................................63
4 Revision History
Changes from Revision I (December 2019) to Revision J (July 2021) Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Changed the t , t OUTPUT CLOCK delay value From: MAX = 9 ns To: MAX = 5 ns in the Timing
DC DD
Requirements ..................................................................................................................................................13
• Changed the t , t OUTPUT CLOCK delay value From: MIN = blank To: MIN = 1.2 ns in the Timing
DC DD
Requirements ..................................................................................................................................................13
• Added the Related Documentation section......................................................................................................63
Changes from Revision H (June 2015) to Revision I (December 2019) Page
• 将文档从数据手册格式更改为 TI 数据表格式......................................................................................................1
• Changed RHB Package 32-Pin OFN To: RHB Package 32-Pin VQFN in Pin Configuration and Functions .....4
• Changed the HBM value From: ±2 V To : ±2000 V in the ESD Ratings ............................................................6
• Changed the t , t INPUT CLOCK value From: MAX = 3 ns To: MIN = 3 ns in the Timing Requirements ..13
SC SD
• Changed the t , t OUTPUT CLOCK value From: MAX = 6 ns To: MIN = 6 ns in the Timing Requirements ..
SC SD
13
• Deleted section Via Channel from the Mechanical Packaging and Orderable Information section .................63
Changes from Revision G (October 2014) to Revision H (June 2015) Page
• Move Storage Temperature From: ESD Ratings To: Absolute Maximum Ratings .............................................6
• Changed the Handling Ratings table To: ESD Ratings ......................................................................................6
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Changes from Revision F (July 2013) to Revision G (October 2014) Page
• 添加了引脚配置和功能 部分、ESD 等级 表、特性说明 部分、器件功能模式、应用和实施 部分、电源相关建
议 部分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分.................................................1
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5 Pin Configuration and Functions
VDDIO DIR VDD18 STP VDD18 RESETB CLOCK N/C
2 1 0 9 8 7 6 5
3 3 3 2 2 2 2 2
REFCLK 1 24 N/C
NXT 2 23 ID
DATA0 3 22 VBUS
DATA1 4 21 VBAT
GND
DATA2 5 20 VDD33
DATA3 6 19 DM
DATA4 7 18 DP
N/C 8 17 CPEN
0 1 2 3 4 5 6
9 1 1 1 1 1 1 1
5 6 S 5 7 G C C
TA TA C D1 TA CF N/ N/ Not to scale
A A D A
D D V D
图 5-1. RHB Package Top View
表 5-1. Pin Functions
PIN
A/D TYPE LEVEL DESCRIPTION
NAME NO.
REFCLK clock frequency configuration pin. Two frequencies are supported: 19.2 MHz
CFG 14 D I VDDIO when 0, or 26 MHz when 1.
ULPI 60 MHz clock on which ULPI data is synchronized.
Two modes are possible:
CLOCK 26 D O VDDIO Input Mode: CLOCK defaults as an input.
Output Mode: When an input clock is detected on REFCLK pin (after 4 rising edges)
then CLOCK will change to an output.
CPEN 17 D O VDD33 CMOS active-high digital output control of external 5 V VBUS supply
Active-high chip select pin. When low the IC is in power down and ULPI bus is tri-
CS 11 D I VDDIO stated. When high normal operation. Tie to VDDIO if unused.
DATA0 3 D I/O VDDIO ULPI DATA input or output signal 0 synchronized to CLOCK
DATA1 4 D I/O VDDIO ULPI DATA input or output signal 1 synchronized to CLOCK
DATA2 5 D I/O VDDIO ULPI DATA input or output signal 2 synchronized to CLOCK
DATA3 6 D I/O VDDIO ULPI DATA input or output signal 3 synchronized to CLOCK
DATA4 7 D I/O VDDIO ULPI DATA input or output signal 4 synchronized to CLOCK
DATA5 9 D I/O VDDIO ULPI DATA input or output signal 5 synchronized to CLOCK
DATA6 10 D I/O VDDIO ULPI DATA input or output signal 6 synchronized to CLOCK
DATA7 13 D I/O VDDIO ULPI DATA input or output signal 7 synchronized to CLOCK
DIR 31 D O VDDIO ULPI DIR output signal
DM 19 A I/O VDD33 DM pin of the USB connector
DP 18 A I/O VDD33 DP pin of the USB connector
ID 23 A I/O VDD33 Identification (ID) pin of the USB connector
8, 15,16,
N/C — — — No connection
24, 25
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表 5-1. Pin Functions (continued)
PIN
A/D TYPE LEVEL DESCRIPTION
NAME NO.
NXT 2 D O VDDIO ULPI NXT output signal
VDD33 Reference clock input (square-wave only). Tie to GND when pin 26 (CLOCK) is
required to be Input mode. Connect to square-wave reference clock of amplitude in
REFCLK 1 A I 3.3 V
the range of 3 V to 3.6 V when Pin 26 (CLOCK) is required to be Output mode. See
pin 14 (CFG) description for REFCLK input frequency settings.
When low, all digital logic (except 32 kHz logic required for power up sequencing)
RESETB 27 D I VDDIO including registers are reset to their default values, and ULPI bus is tri-stated. When
high, normal USB operation.
STP 29 D I VDDIO ULPI STP input signal
VBAT 21 A power VBAT Input supply voltage or battery source
VBUS 22 A power VBUS VBUS pin of the USB connector
VDD15 12 A power 1.5 V internal LDO output. Connect to external filtering capacitor.
VDD18 28, 30 A power VDD18 External 1.8 V supply input. Connect to external filtering capacitor.
VDD33 20 A power VDD33 3.3 V internal LDO output. Connect to external filtering capacitor.
VDDIO 32 A I VDDIO External 1.8 V supply input for digital I/Os. Connect to external filtering capacitor.
Thermal
GND A power — Reference Ground
Pad
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Main battery supply voltage (2) 0 5 V
Where supply represents the voltage applied
Voltage on any input(3) to the power supply pin associated with the –0.3 1 × VCC +0.3 V
input
VBUS input –2 20 V
ID, DP, DM inputs Stress condition guaranteed 24h –0.3 5.25 V
V IO supply voltage Continuous 1.98 V
DDIO
TA Ambient temperature range –40 85 °C
Absolute maximum rating –40 150
T Ambient temperature range °C
J
For parametric compliance –40 125
Ambient temperature for parametric With max 125°C as junction temperature
–40 85 °C
compliance
DP, DM or ID pins short circuited to V
BUS
DP, DM, ID high voltage short circuit supply, in any mode of TUSB1210 operation, 5.25 V
continuously for 24 hours
DP, DM or ID pins short circuited to GND in
DP, DM, ID low voltage short circuit any mode of TUSB1210 operation, 0 V
continuously for 24 hours
Tstg Storage temperature range –55 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under 节 6.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The product will have negligible reliability impact if voltage spikes of 5.5 V occur for a total (cumulative over lifetime) duration of 5
milliseconds.
(3) Except V input, V , ID, DP, and DM pads
BAT BUS
6.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS001(1) ±2000
Electrostatic discharge (ESD)
V(ESD) performance: Charged device model (CDM), per JESD22-C101 or ANSI/ ±500 V
ESDA/JEDEC JS-002(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
V Battery supply voltage 2.7 3.6 4.8 V
BAT
Battery supply voltage for USB 2.0 compliancy When VDD33 is supplied internally 3.15
V V
BAT CERT (USB 2.0 certification) When V is shorted to V externally 3.05
DD33 BAT
V Digital IO pin supply 1.71 1.98 V
DDIO
TA Ambient temperature range –40 85 °C
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6.4 Thermal Information
RHB
THERMAL METRIC(1) UNIT
(16 Pins)
RθJA Junction-to-ambient thermal resistance 34.72 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 37.3 °C/W
RθJB Junction-to-board thermal resistance 10.3 °C/W
ψ Junction-to-top characterization parameter 0.5 °C/W
JT
ψ Junction-to-board characterization parameter 10.5 °C/W
JB
RθJC(bottom) Junction-to-case(bottom) thermal resistance 3.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Analog I/O Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
CPEN Output Pin
V CPEN low-level output voltage I = 3 mA 0.3 V
OL OL
VOH CPEN high-level output voltage IOH = –3 mA VDD33 – 0.3 V
6.6 Digital I/O Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CLOCK
V Low-level output voltage 0.45 V
OL
Frequency = 60 MHz, Load = 10 pF
V High-level output voltage V - 0.45 V
OH DDIO
STP, DIR, NXT, DATA0 to DATA7
V Low-level output voltage 0.45 V
OL
Frequency = 30 MHz, Load = 10 pF
V High-level output voltage V - 0.45 V
OH DDIO
6.7 Digital IO Pins (Non-ULPI)
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CS, CFG, RESETB Input Pins
V Maximum low-level input voltage 0.35 x V V
IL DDIO
V Minimum high-level input voltage 0.65 x V V
IH DDIO
RESETB Input Pin Timing Spec
t Internal power-on reset pulse
w(POR) 0.2 μs
width
t Applied to external RESETB pin CLOCK
w(RESET) External RESETB pulse width 8
when CLOCK is toggling. cycles
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6.8 PHY Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER COMMENTS MIN TYP MAX UNIT
LS/FS Single-Ended Receivers
USB single-ended receivers
SKWVP_VM Skew between VP and VM Driver outputs unloaded –2 0 2 ns
VSE_HYS Single-ended hysteresis 50 mV
VIH High (driven) 2 V
VIL Low 0.8 V
VTH Switching threshold 0.8 2 V
LS/FS Differential Receiver
VDI Differential input sensitivity Ref. USB2.0 200 mV
VCM Differential Common mode range Ref. USB2.0 0.8 2.5 V
LS Transmitter
VOL Low Ref. USB2.0 0 300 mV
VOH High (driven) Ref. USB2.0 2.8 3.6 V
Ref. USB2.0, covered by eye
VCRS Output signal crossover voltage diagram 1.3 2 V
Ref. USB2.0, covered by eye
tr Rise time diagram 75 300 ns
tf Fall time 75 300 ns
tFRFM Differential rise and fall time matching 80% 125%
Ref. USB2.0, covered by eye
tFDRATE Low-speed data rate diagram 1.4775 1.5225 Mb/s
tDJ1 To next transition –25 25
Source jitter total (including frequency Ref. USB2.0, covered by eye
tDJ2 tolerance) Ftroarn spiatiiorends diagram –10 10 ns
Ref. USB2.0, covered by eye
tFEOPT Source SE0 interval of EOP diagram 1.25 1.5 µs
Ref. USB2.0, covered by eye
Downstream eye diagram
diagram
VCM Differential common mode range Ref. USB2.0 0.8 2.5 V
FS Transmitter
VOL Low Ref. USB2.0 0 300 mV
VOH High (driven) Ref. USB2.0 2.8 3.6 V
Ref. USB2.0, covered by eye
VCRS Output signal crossover voltage 1.3 2 V
diagram
tFR Rise time Ref. USB2.0 4 20 ns
tFF Fall time Ref. USB2.0 4 20 ns
Ref. USB2.0, covered by eye
tFRFM Differential rise and fall time matching diagram 90% 111.11%
ZDRV Driver output resistance Ref. USB2.0 28 44 Ω
Ref. USB2.0, covered by eye
TFDRATE Full-speed data rate 11.97 12.03 Mb/s
diagram
tDJ1 To next transition –2 2
Source jitter total (including frequency Ref. USB2.0, covered by eye
tDJ2 tolerance) Ftroarn spiatiiorends diagram –1 1 ns
Ref. USB2.0, covered by eye
TFEOPT Source SE0 interval of EOP 160 175 ns
diagram
Ref. USB2.0, covered by eye
Downstream eye diagram
diagram
Upstream eye diagram
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6.8 PHY Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER COMMENTS MIN TYP MAX UNIT
HS Differential Receiver
High-speed squelch detection threshold (differential signal
VHSSQ Ref. USB2.0 100 150 mV
amplitude)
High-speed disconnect detection threshold (differential signal
VHSDSC Ref. USB2.0 525 625 mV
amplitude)
Ref. USB2.0, specified by eye
High-speed differential input signaling levels mV
pattern templates
High-speed data signaling common mode voltage range
VHSCM Ref. USB2.0 –50 500 mV
(guidelines for receiver)
Ref. USB2.0, specified by eye
Receiver jitter tolerance 150 ps
pattern templates
HS Transmitter
VHSOI High-speed idle level Ref. USB2.0 –10 10 mV
VHSOH High-speed data signaling high Ref. USB2.0 360 440 mV
VHSOL High-speed data signaling low Ref. USB2.0 –10 10 mV
VCHIRPJ Chirp J level (differential voltage) Ref. USB2.0 700 1100 mV
VCHIRPK Chirp K level (differential voltage) Ref. USB2.0 -900 -500 mV
Ref. USB2.0, covered by eye
tr Rise Time (10% - 90%) diagram 500 ps
Ref. USB2.0, covered by eye
tf Fall time (10% - 90%) diagram 500 ps
Driver output resistance (which also serves as high-speed
ZHSDRV Ref. USB2.0 40.5 49.5 Ω
termination)
Ref. USB2.0, covered by eye
THSDRAT High-speed data range 479.76 480.24 Mb/s
diagram
Ref. USB2.0, covered by eye
Data source jitter
diagram
Ref. USB2.0, covered by eye
Downstream eye diagram
diagram
Ref. USB2.0, covered by eye
Upstream eye diagram
diagram
CEA-2011/UART Transceiver
UART Transmitter CEA-2011
tPH_UART_EDGE Phone UART edge rates DP_PULLDOWN asserted 1 Μs
VOH_SER Serial interface output high ISOURCE = 4 mA 2.4 3.3 3.6 V
VOL_SER Serial interface output low ISINK = –4 mA 0 0.1 0.4 V
UART Receiver CEA-2011
VIH_SER Serial interface input high DP_PULLDOWN asserted 2 V
VIL_SER Serial interface input low DP_PULLDOWN asserted 0.8 V
VTH Switching threshold 0.8 2 V
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6.9 Pullup/Pulldown Resistors
over operating free-air temperature range (unless otherwise noted)
PARAMETER COMMENTS MIN TYP MAX UNIT
Bus pullup resistor on upstream port
RPUI Bus idle 0.9 1.1 1.575 kΩ
(idle bus)
Bus pullup resistor on upstream port
RPUA Bus driven/driver's outputs unloaded 1.425 2.2 3.09
(receiving)
Pullups/pulldowns on both DP and DM
VIHZ High (floating) 2.7 3.6 V
lines
VPH_DP_UP Phone D+ pullup voltage Driver's outputs unloaded 3 3.3 3.6 V
Pulldown resistors
RPH_DP_DWN Phone D+/– pulldown Driver's outputs unloaded 14.25 18 24.8 kΩ
RPH_DM_DWN
Pullups/pulldowns on both DP and DM
V High (floating) 2.7 3.6 V
IHZ lines
D+/– Data line
C Upstream facing port [1.0] 22 75 pF
INUB
V On-the-go device leakage [2] 0.342 V
OTG_DATA_LKG
Input impedance exclusive of pullup/
ZINP pulldown Driver's outputs unloaded 300 kΩ
6.10 OTG Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER COMMENTS MIN TYP MAX UNIT
OTG V Electrical
BUS
V Comparators
BUS
VA_SESS_VLD A-device session valid 0.8 1.4 2.0 V
VA_VBUS_VLD A-device V valid 4.4 4.5 4.625 V
BUS
VB_SESS_END B-device session end 0.2 0.5 0.8 V
VB_SESS_VLD B-device session valid 2.1 2.4 2.7 V
V Line
BUS
A-device V input impedance SRP (V pulsing) capable A-device not driving
RA_BUS_IN BUS BUS 40 70 100 kΩ
to ground V
BUS
RB_SRP_DWN B-device VBUS SRP pulldown 5.25 V / 8 mA, Pullup voltage = 3 V 0.656 10 kΩ
RB_SRP_UP B-device VBUS SRP pullup (5.25 V – 3 V) / 8 mA, Pullup voltage = 3 V 0.281 1 2 kΩ
RV = 0 Ω
BUS 31.4
and R1KSERIES = '0'
RV = 1000 Ω ±10%
B-device VBUS SRP rise time 0 to 2.1 V with < 13 μF andB URS1KSERIES = '1' 57.8
t maximum for OTG-A ms
RISE_SRP_UP_MAX communication load RVBUS = 1200 Ω ±10% 64
and R1KSERIES = '1'
RV = 1800 Ω ±10%
BUS 85.4
and R1KSERIES = '1'
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