Stand-Alone CAN Controller with SPI Interface

76 Pages·2002·1.1 MB·English

by  Microchip Technology Inc.

M
MCP2510
™
Stand-Alone CAN Controller with SPI Interface
Features Description
• Implements Full CAN V2.0A and V2.0B at 1Mb/s: The Microchip Technology Inc. MCP2510 is a Full Con-
- 0 - 8 byte message length troller Area Network (CAN) protocol controller imple-
menting CAN specification V2.0 A/B. It supports CAN
- Standard and extended data frames
1.2, CAN 2.0A, CAN 2.0B Passive, and CAN 2.0B
- Programmable bit rate up to 1Mb/s
Active versions of the protocol, and is capable of trans-
- Support for remote frames mitting and receiving standard and extended mes-
- Two receive buffers with prioritized message sages. It is also capable of both acceptance filtering
storage and message management. It includes three transmit
- Six full acceptance filters buffers and two receive buffers that reduce the amount
- Two full acceptance filter masks of microcontroller (MCU) management required. The
MCU communication is implemented via an industry
- Three transmit buffers with prioritization and
standard Serial Peripheral Interface (SPI) with data
abort features
rates up to 5Mb/s.
- Loop-back mode for self test operation
• Hardware Features: Package Types
- High Speed SPI Interface
18 L EAD PDIP/SOIC
(5MHz at 4.5V I temp)
- Supports SPI modes 0,0 and 1,1 TXCAN 1 18 VDD
- Clock out pin with programmable prescaler RXCAN 2 17 RESET
- Interrupt output pin with selectable enables CLKOUT 3 16 CS
- ‘Buffer full’ output pins configureable as inter- M
TX0RTS 4 15 SO
rupt pins for each receive buffer or as general C
P
purpose digital outputs TX1RTS 5 2 14 SI
5
1
- ‘Request to Send’ input pins configureable as TX2RTS 6 0 13 SCK
control pins to request immediate message OSC2 7 12 INT
transmission for each transmit buffer or as
OSC1 8 11 RX0BF
general purpose digital inputs
- Low Power Sleep mode VSS 9 10 RX1BF
• Low power CMOS technology:
20 LEAD TSSOP
- Operates from 3.0V to 5.5V
- 5mA active current typical TXCAN 1 20 VDD
• 1-81-p0inµ AP DstIaPn/SdObyI Cc uarnredn 2t 0ty-ppiinc aTl SaSt 5O.P5V packages CTRLXKX0OCRAUTNST 234 M 111987 CRSOSESET
• Temperature ranges supported: C
TX1RTS 5 P 16 SI
- Industrial (I): -40°C to +85°C NC 6 25 15 NC
- Extended (E): -40°C to +125°C TX2RTS 7 10 14 SCK
OSC2 8 13 INT
OSC1 9 12 RX0BF
VSS 10 11 RX1BF
 2002 Microchip Technology Inc. DS21291E-page 1
MCP2510
Table of Contents
1.0 Device Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.0 Can Message Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.0 Message Transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.0 Message Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.0 Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.0 Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.0 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.0 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.0 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.0 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.0 SPI Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.0 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
13.0 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
On-Line Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Reader Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Product Identification System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Worldwide Sales and Service. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
To Our Valued Customers
Most Current Data Sheet
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Errata
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workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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Corrections to this Data Sheet
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DS21291E-page 2  2002 Microchip Technology Inc.
MCP2510
1.0 DEVICE FUNCTIONALITY checked for errors and then matched against the user
defined filters to see if it should be moved into one of
1.1 Overview the two receive buffers.
The MCU interfaces to the device via the SPI interface.
The MCP2510 is a stand-alone CAN controller devel-
Writing to and reading from all registers is done using
oped to simplify applications that require interfacing
standard SPI read and write commands.
with a CAN bus. A simple block diagram of the
MCP2510 is shown in Figure1-1. The device consists Interrupt pins are provided to allow greater system flex-
of three main blocks: ibility. There is one multi-purpose interrupt pin as well
as specific interrupt pins for each of the receive regis-
1. The CAN protocol engine.
ters that can be used to indicate when a valid message
2. The control logic and SRAM registers that are
has been received and loaded into one of the receive
used to configure the device and its operation.
buffers. Use of the specific interrupt pins is optional,
3. The SPI protocol block. and the general purpose interrupt pin as well as status
A typical system implementation using the device is registers (accessed via the SPI interface) can also be
shown in Figure1-2. used to determine when a valid message has been
received.
The CAN protocol engine handles all functions for
receiving and transmitting messages on the bus. Mes- There are also three pins available to initiate immediate
sages are transmitted by first loading the appropriate transmission of a message that has been loaded into
message buffer and control registers. Transmission is one of the three transmit registers. Use of these pins is
initiated by using control register bits, via the SPI inter- optional and initiating message transmission can also
face, or by using the transmit enable pins. Status and be done by utilizing control registers accessed via the
errors can be checked by reading the appropriate reg- SPI interface.
isters. Any message detected on the CAN bus is Table1-1 gives a complete list of all of the pins on the
MCP2510.
FIGURE 1-1: BLOCK DIAGRAM
RXCAN 2 RX Buffers
CAN SPI CS
3 TX 6 Acceptance
Protocol Interface SCK SPI
Buffers Filters
Engine Logic SI Bus
Message Assembly
TXCAN SO
Buffer
Control Logic
INT
RX0BF
RX1BF
TX0RTS
TX1RTS
TX2RTS
 2002 Microchip Technology Inc. DS21291E-page 3
MCP2510
FIGURE 1-2: TYPICAL SYSTEM IMPLEMENTATION
Main
System
Controller
MCP2510
CAN
Transceiver
CAN
BUS
CAN CAN CAN CAN
Transceiver Transceiver Transceiver Transceiver
MCP2510 MCP2510 MCP2510 MCP2510
SPI

INTERFACE
Node Node Node Node
Controller Controller Controller Controller
TABLE 1-1: PIN DESCRIPTIONS
DIP/
TSSOP I/O/P
Name SOIC Description
Pin # Type
Pin #
TXCAN 1 1 O Transmit output pin to CAN bus
RXCAN 2 2 I Receive input pin from CAN bus
CLKOUT 3 3 O Clock output pin with programmable prescaler
TX0RTS 4 4 I Transmit buffer TXB0 request to send or general purpose digital input. 100kΩ
internal pullup to VDD
TX1RTS 5 5 I Transmit buffer TXB1 request to send or general purpose digital input. 100kΩ
internal pullup to VDD
TX2RTS 6 7 I Transmit buffer TXB2 request to send or general purpose digital input. 100kΩ
internal pullup to VDD
OSC2 7 8 O Oscillator output
OSC1 8 9 I Oscillator input
VSS 9 10 P Ground reference for logic and I/O pins
RX1BF 10 11 O Receive buffer RXB1 interrupt pin or general purpose digital output
RX0BF 11 12 O Receive buffer RXB0 interrupt pin or general purpose digital output
INT 12 13 O Interrupt output pin
SCK 13 14 I Clock input pin for SPI interface
SI 14 16 I Data input pin for SPI interface
SO 15 17 O Data output pin for SPI interface
CS 16 18 I Chip select input pin for SPI interface
RESET 17 19 I Active low device reset input
VDD 18 20 P Positive supply for logic and I/O pins
NC — 6,15 — No internal connection
Note: Type Identification: I=Input; O=Output; P=Power
DS21291E-page 4  2002 Microchip Technology Inc.
MCP2510
1.2 Transmit/Receive Buffers
The MCP2510 has three transmit and two receive buffers, two acceptance masks (one for each receive buffer), and a
total of six acceptance filters. Figure 1-3 is a block diagram of these buffers and their connection to the protocol engine.
FIGURE 1-3: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM
Acceptance Mask
BUFFERS RXM1
Acceptance Filter
RXF2
Acceptance Mask Acceptance Filter A
TXB0 TXB1 TXB2 A RXM0 RXF3 c
c c
E E E
G G G c Acceptance Filter Acceptance Filter e
EQFARR SA EQFARR SA EQFARR SA e RXF0 RXF4 p
RTOE S RTOE S RTOE S p t
TXABMLTX ME TXABMLTX ME TXABMLTX ME t Acceptance Filter Acceptance Filter
RXF1 RXF5
R R
M
X Identifier Identifier X
Message A
B B
Queue B
0 1
Control
Transmit Byte Sequencer Data Field Data Field
Receive REC
Error
PROTOCOL Counter TEC
ENGINE
Transmit ErrPas
Error BusOff
Counter
Transmit<7:0> Receive<7:0>
Shift<14:0>
{Transmit<5:0>, Receive<8:0>}
Comparator
Protocol
Finite
State
CRC<14:0> Machine
Bit
Transmit
Timing Clock
Logic
Logic Generator
TX RX
Configuration
Registers
 2002 Microchip Technology Inc. DS21291E-page 5
MCP2510
1.3 CAN Protocol Engine 1.6 Error Management Logic
The CAN protocol engine combines several functional The Error Management Logic is responsible for the
blocks, shown in Figure1-4. These blocks and their fault confinement of the CAN device. Its two counters,
functions are described below. the Receive Error Counter (REC) and the Transmit
Error Counter (TEC), are incremented and decre-
1.4 Protocol Finite State Machine mented by commands from the Bit Stream Processor.
According to the values of the error counters, the CAN
The heart of the engine is the Finite State Machine
controller is set into the states error-active, error-pas-
(FSM). This state machine sequences through mes-
sive or bus-off.
sages on a bit by bit basis, changing states as the fields
of the various frame types are transmitted or received. 1.7 Bit Timing Logic
The FSM is a sequencer controlling the sequential data
stream between the TX/RX Shift Register, the CRC The Bit Timing Logic (BTL) monitors the bus line input
Register, and the bus line. The FSM also controls the and handles the bus related bit timing according to the
Error Management Logic (EML) and the parallel data CAN protocol. The BTL synchronizes on a recessive to
stream between the TX/RX Shift Registers and the dominant bus transition at Start of Frame (hard syn-
buffers. The FSM insures that the processes of recep- chronization) and on any further recessive to dominant
tion, arbitration, transmission, and error signaling are bus line transition if the CAN controller itself does not
performed according to the CAN protocol. The auto- transmit a dominant bit (resynchronization). The BTL
matic retransmission of messages on the bus line is also provides programmable time segments to com-
also handled by the FSM. pensate for the propagation delay time, phase shifts,
and to define the position of the Sample Point within the
1.5 Cyclic Redundancy Check bit time. The programming of the BTL depends upon
the baud rate and external physical delay times.
The Cyclic Redundancy Check Register generates the
Cyclic Redundancy Check (CRC) code which is trans-
mitted after either the Control Field (for messages with
0 data bytes) or the Data Field, and is used to check the
CRC field of incoming messages.
FIGURE 1-4: CAN PROTOCOL ENGINE BLOCK DIAGRAM
RX TX
Bit Timing Logic Transmit Logic
SAM
REC
Sample<2:0> Receive
Error Counter
TEC
StuffReg<5:0>
Transmit
ErrPas
Majority
Error Counter
Decision BusOff
BusMon
Comparator
CRC<14:0>
Protocol
FSM
Comparator
Shift<14:0>
(Transmit<5:0>, Receive<7:0>)
Receive<7:0> Transmit<7:0>
RecData<7:0> TrmData<7:0>
Interface to Standard Buffer Rec/Trm Addr.
DS21291E-page 6  2002 Microchip Technology Inc.
MCP2510
2.0 CAN MESSAGE FRAMES dard CAN frame will win arbitration due to the assertion
of a dominant lDE bit. Also, the SRR bit in an extended
The MCP2510 supports Standard Data Frames, CAN frame must be recessive to allow the assertion of
Extended Data Frames, and Remote Frames (Stan- a dominant RTR bit by a node that is sending a stan-
dard and Extended) as defined in the CAN 2.0B speci- dard CAN remote frame.
fication.
The SRR and lDE bits are followed by the remaining 18
2.1 Standard Data Frame bits of the identifier (Extended lD) and the remote trans-
mission request bit.
The CAN Standard Data Frame is shown in Figure2-1.
To enable standard and extended frames to be sent
In common with all other frames, the frame begins with
across a shared network, it is necessary to split the 29-
a Start Of Frame (SOF) bit, which is of the dominant
bit extended message identifier into 11-bit (most signif-
state, which allows hard synchronization of all nodes.
icant) and 18-bit (least significant) sections. This split
The SOF is followed by the arbitration field, consisting ensures that the lDE bit can remain at the same bit
of 12 bits; the 11-bit ldentifier and the Remote Trans- position in both standard and extended frames.
mission Request (RTR) bit. The RTR bit is used to dis-
Following the arbitration field is the six-bit control field.
tinguish a data frame (RTR bit dominant) from a remote
the first two bits of this field are reserved and must be
frame (RTR bit recessive).
dominant. the remaining four bits of the control field are
Following the arbitration field is the control field, con- the Data Length Code (DLC) which specifies the num-
sisting of six bits. The first bit of this field is the Identifier ber of data bytes contained in the message.
Extension (IDE) bit which must be dominant to specify
The remaining portion of the frame (data field, CRC
a standard frame. The following bit, Reserved Bit Zero
field, acknowledge field, end of frame and lntermission)
(RB0), is reserved and is defined to be a dominant bit
is constructed in the same way as for a standard data
by the can protocol. the remaining four bits of the con-
frame (see Section2.1).
trol field are the Data Length Code (DLC) which speci-
fies the number of bytes of data contained in the 2.3 Remote Frame
message.
Normally, data transmission is performed on an auton-
After the control field is the data field, which contains
omous basis by the data source node (e.g. a sensor
any data bytes that are being sent, and is of the length
sending out a data frame). It is possible, however, for a
defined by the DLC above (0-8 bytes).
destination node to request data from the source. To
The Cyclic Redundancy Check (CRC) Field follows the accomplish this, the destination node sends a remote
data field and is used to detect transmission errors. The frame with an identifier that matches the identifier of the
CRC Field consists of a 15-bit CRC sequence, followed required data frame. The appropriate data source node
by the recessive CRC Delimiter bit. will then send a data frame in response to the remote
The final field is the two-bit acknowledge field. During frame request.
the ACK Slot bit, the transmitting node sends out a There are two differences between a remote frame
recessive bit. Any node that has received an error free (shown in Figure2-3) and a data frame. First, the RTR
frame acknowledges the correct reception of the frame bit is at the recessive state, and second, there is no
by sending back a dominant bit (regardless of whether data field. In the event of a data frame and a remote
the node is configured to accept that specific message frame with the same identifier being transmitted at the
or not). The recessive acknowledge delimiter com- same time, the data frame wins arbitration due to the
pletes the acknowledge field and may not be overwrit- dominant RTR bit following the identifier. In this way,
ten by a dominant bit. the node that transmitted the remote frame receives
the desired data immediately.
2.2 Extended Data Frame
2.4 Error Frame
In the Extended CAN Data Frame, the SOF bit is fol-
lowed by the arbitration field which consists of 32 bits, An Error Frame is generated by any node that detects
as shown in Figure2-2. The first 11 bits are the most a bus error. An error frame, shown in Figure2-4, con-
significant bits (Base-lD) of the 29-bit identifier. These sists of two fields, an error flag field followed by an error
11 bits are followed by the Substitute Remote Request delimiter field. There are two types of error flag fields.
(SRR) bit which is defined to be recessive. The SRR bit Which type of error flag field is sent depends upon the
is followed by the lDE bit which is recessive to denote error status of the node that detects and generates the
an extended CAN frame. error flag field.
It should be noted that if arbitration remains unresolved If an error-active node detects a bus error then the
after transmission of the first 11 bits of the identifier, and node interrupts transmission of the current message by
one of the nodes involved in the arbitration is sending generating an active error flag. The active error flag is
a standard CAN frame (11-bit identifier), then the stan- composed of six consecutive dominant bits. This bit
 2002 Microchip Technology Inc. DS21291E-page 7
MCP2510
sequence actively violates the bit stuffing rule. All other 2.5 Overload Frame
stations recognize the resulting bit stuffing error and in
An Overload Frame, shown in Figure2-5, has the
turn generate error frames themselves, called error
echo flags. The error flag field, therefore, consists of same format as an active error frame. An overload
between six and twelve consecutive dominant bits frame, however can only be generated during an lnter-
(generated by one or more nodes). The error delimiter frame space. In this way an overload frame can be dif-
ferentiated from an error frame (an error frame is sent
field completes the error frame. After completion of the
during the transmission of a message). The overload
error frame, bus activity returns to normal and the inter-
frame consists of two fields, an overload flag followed
rupted node attempts to resend the aborted message.
by an overload delimiter. The overload flag consists of
If an error-passive node detects a bus error then the
six dominant bits followed by overload flags generated
node transmits an error-passive flag followed by the
by other nodes (and, as for an active error flag, giving
error delimiter field. The error-passive flag consists of
a maximum of twelve dominant bits). The overload
six consecutive recessive bits, and the error frame for
delimiter consists of eight recessive bits. An overload
an error-passive node consists of 14 recessive bits.
frame can be generated by a node as a result of two
From this, it follows that unless the bus error is
conditions. First, the node detects a dominant bit during
detected by the node that is actually transmitting, the
the interframe space which is an illegal condition. Sec-
transmission of an error frame by an error-passive
ond, due to internal conditions the node is not yet able
node will not affect any other node on the network. If
to start reception of the next message. A node may
the transmitting node generates an error-passive flag
generate a maximum of two sequential overload
then this will cause other nodes to generate error
frames to delay the start of the next message.
frames due to the resulting bit stuffing violation. After
transmission of an error frame, an error-passive node 2.6 Interframe Space
must wait for six consecutive recessive bits on the bus
before attempting to rejoin bus communications. The lnterframe Space separates a preceeding frame
(of any type) from a subsequent data or remote frame.
The error delimiter consists of eight recessive bits and
The interframe space is composed of at least three
allows the bus nodes to restart bus communications
recessive bits called the Intermission. This is provided
cleanly after an error has occurred.
to allow nodes time for internal processing before the
start of the next message frame. After the intermission,
the bus line remains in the recessive state (bus idle)
until the next transmission starts.
DS21291E-page 8  2002 Microchip Technology Inc.
 FIGURE 2-1: STANDARD DATA FRAME
2
0
0
2
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Data Frame (number of bits = 44 + 8N)
12 6 8N (0≤N≤8) 16 7
Arbitration Field Control Data Field CRC Field
e
m Field End of
Start of FraD 10 11 D3 D0RTRDERB0DLC3 4 DLC0 8 8 C1R5C CRC DelAck Slot BitACK Del Frame IFS
I I I I
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Identifier Bit Data
ed Length
v
Message er Code
s
Filtering e
R
Stored in Transmit/Receive Buffers
Stored in Buffers
Bit Stuffing
M
C
DS P
2
12 2
9
1 5
E
-p 1
a
g
e 0
9
 FIGURE 2-2: EXTENDED DATA FRAME
2
0
0
2
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lo
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Data Frame (number of bits = 64 + 8N)
32 6 8N (0≤N≤8) 16 7
e Arbitration Field Control Data Field CRC Field
Start of FramID10 11 ID3 ID0SRRIDEEID17 18 EID0RTRRB1RB0FDLC3ield4 DLC0 8 8 C1R5C CRC DelAck Slot BitACK Del EFrnadm oef IFS
0 11 000 1 11111111111
s
Identifier Extended Identifier bit Data
d Length
e
Message erv Code
Filtering s
e
Stored in Buffers R Stored in Transmit/Receive Buffers
Bit Stuffing
M
C
D
S P
2
1
29 2
1
E 5
-p
a 1
g
e
1 0
0