Siskos Aris

67 Pages·2017·5.79 MB·English

MASTER THESIS
Design of an integrated power management system using
reconfigurable storage scheme for batteryless wireless sensor
nodes

Siskos Aris
Supervised by: Prof. Laopoulos Theodore

Thessaloniki
March 2018
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Abstract

In this thesis an integrated power management system is implemented, using a reconfigurable
supercapacitors (SCs) structure with four SCs, which requires a control unit that is used to alter the
different SCs structure configurations. The different configurations of the SCs structure are when all SCs
are connected in series, a combination between series and parallel connection and all the SCs connected
in parallel. These different states of SCs structure offer enhancements in charging and discharging phase,
where a simple SC is not able to provide.
The system is mandatory to be very low power, autonomous and as generic as possible. Regarding these
challenges, there was a research about the possibilities that exist for an architecture. After this step, an
architecture is proposed, which is implemented in AMS 0.35μm CMOS. The process family that is selected
is C35B3L3, which includes low threshold voltage transistors that benefit the design of the system.
Furthermore, the SCs that are selected, have a rated voltage at 5.5V and 100mF capacitance. Low
threshold voltage transistors were used for the switches of the reconfigurable SCs structure because of
the low on-resistance. The choice of the switches provide the ability of self-startup for the system.
The proposed architecture has various circuit blocks. The control unit consists of two comparators and
the power management unit consists of an LDO. A bandgap reference circuit is needed to generate a
voltage reference for the LDO and the control unit. These circuits must follow the specifications that were
extracted from the proposed architecture. The most crucial specification is the high PSRR that the circuits
demand.
The circuits are implemented in physical design and post-layout simulation and corner analysis are
performed. A post-layout and corner analysis are also realized for the total system, which presents the
desired behavior. The power management and the control unit demand 45μA and when the supply
voltage is 5.5V they consume 248μW. The switches consume less than 500μW, when the discharging
current is maximum. A right charging unit can support this system, which can operate properly and be
autonomous.
This system was redesigned in AMS 0.35μm CMOS with the flavor C35B4C3, which is available to the
universities via Europractice and CMP organizations. Although, this technology does not provide low
threshold voltage transistors the whole system presents almost the same behavior with narrower range
of operation. This design was sent for fabrication.

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Περίληψη

Στην παρούσα διπλωματική εργασία υλοποιήθηκε ένα ολοκληρωμένο σύστημα διαχείρισης ενέργειας
μίας επαναδιατασσόμενης δομής με τέσσερις supercapacitors (SCs), η οποία απαιτεί μία μονάδα ελέγχου
που χρησιμοποιείται για να αλλάζει την δομή των SCs σε διαφορετικές συνδεσμολογίες. Η πρώτη
συνδεσμολογία είναι με τους SCs συνδεμένους σε σειρά, η δεύτερη είναι ένας συνδυασμός μεταξύ
παράλληλης και σειράς σύνδεσης και τέλος η τρίτη συνδεσμολογία είναι όταν όλοι οι SCs βρίσκονται σε
παράλληλη σύνδεση. Αυτές οι διαφορετικές συνδεσμολογίες της δομής των SCs προσφέρουν βελτιώσεις
στην φάση φόρτισης και εκφόρτισης, όπου ένας μόνο SC δεν είναι ικανός να παρέχει.
Το σύστημα είναι υποχρεωτικό να είναι πολύς χαμηλής ενέργειας, αυτόνομο και όσο το δυνατόν πιο
γενικό. Δεδομένων αυτών των προκλήσεων, έγινε μία έρευνα για τις δυνατότητες που υπάρχουν για μία
αρχιτεκτονική που να υλοποιεί αυτό το σύστημα. Μετά από αυτό το βήμα, προτάθηκε μία αρχιτεκτονική,
η οποία υλοποιήθηκε σε τεχνολογία AMS 0.35μm CMOS C35B3L3. Αυτή η τεχνολογία που επιλέχθηκε,
περιλαμβάνει τρανζίστορ χαμηλής τάσης κατωφλίου, τα οποία είναι τα πλέον κατάλληλα για το
σχεδιασμό του συστήματος. Επιπλέον, οι SCs που επιλέχθηκαν στη δομή, έχουν ονομαστική τάση στα
5.5V και χωρητικότητα 100mF. Τα χαμηλής τάσης κατωφλίου τρανζίστορ χρησιμοποιήθηκαν για τους
διακόπτες της επαναδιατασόμενης δομής με SCs, γιατί παρουσιάζουν μικρότερη αντίσταση. Επίσης, η
επιλογή των διακοπτών έγινε ώστε το σύστημα να έχει τη δυνατότητα να εκκινεί χωρίς τη χρήση
μπαταρίας.
Η προτεινόμενη αρχιτεκτονική έχει διάφορα κυκλώματα. Η μονάδα ελέγχου αποτελείται από δύο
συγκριτές, ενώ η μονάδα διαχείρισης ενέργειας αποτελείται από έναν LDO. Ένακύκλωμα τάσης
αναφοράς (bandgap reference) χρειάζεται για να δημιουργεί τις κατάλληλες τάσεις αναφοράς στον
LDOκαι στη μονάδα ελέγχου. Αυτά τα κυκλώματα πρέπει να ακολουθούν τις προδιαγραφές, οι οποίες
εξήχθησαν από την προτεινόμενη αρχιτεκτονική. Η κυριότερη προδιαγραφή είναι το υψηλό PSRR, το
οποίο απαιτείται να διαθέτουν τα κυκλώματα, λόγω των απότομων μεταβολών στην τροφοδοσία τους.
Τα κυκλώματα υλοποιήθηκαν στο φυσικό σχέδιο και εκτελέστηκε προσομοίωση για αυτά μετά το φυσικό
σχεδιασμό συμπεριλαμβανομένων και των παρασιτικών τους και ανάλυση ακραίων συνθηκών. Οι ίδιες
προσομοιώσεις έγιναν επίσης για το συνολικό κύκλωμα, το οποίο παρουσιάζει την επιθυμητή
συμπεριφορά. Η μονάδα διαχείρισης ενέργειας και η μονάδα ελέγχου απαιτούν 45μA ρεύμα και η
κατανάλωση τους είναι περίπου 248uW στην περίπτωση που η τάση τροφοδοσίας είναι 5.5V. Οι
διακόπτες καταναλώνουν μέχρι και 500μW στην περίπτωση που το ρεύμα εκφόρτισης είναι το
μεγαλύτερο δυνατό (50mA). Ένα σύστημα συγκομιδής ενέργειας και μία κατάλληλη μονάδα φόρτισης
μπορεί να υποστηρίξει το σύστημα, ώστε αυτό να λειτουργεί απολύτως αυτόνομα.
Το σύστημα επανασχεδιάστηκε στην τεχνολογία AMS 0.35μm CMOS C35B4C3, η οποία είναι διαθέσιμη
στα πανεπιστήμια μέσω των οργανισμών Europractice και CMP. Παρόλο που η τεχνολογία δεν παρέχει
χαμηλής τάσης κατωφλίου τρανζίστορ, το συνολικό σύστημα παρουσιάζει σχεδόν την ίδια συμπεριφορά
με πιο περιορισμένα όρια λειτουργίας. Η σχεδίαση του συστήματος στάλθηκε για κατασκευή.
Acknowledgments

First of all, I am really grateful to my supervisor in Greece Dr. Theodore Laopoulos, Professor at the Section
of Electronics and Computers, Physics Department, Aristotle University of Thessaloniki, as well as to Dr.
Marise Bafleur, Head of ESE group in LAAS-CNRS, Toulouse, France for their valuable support, guidance
and motivation. They offer me the opportunity to work on a very interesting subject in analog electronics
and they guide me in the total process of this thesis. I would like to show my best appreciation and express
my deepest gratitude to them.
Moreover, I would like to give special thanks the Ph.D. student Firdaous El Mahboubi, who helped me
understand the SCs structure and the discrete solution that she has implemented. She also advised me
with the challenges and the issues that occurred, while I was designing the system.
Finally, I would like to thank my family and my friend Angeliki for their support throughout my master
studies.

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Contents
Abstract ........................................................................................................................................................ iv
Περίληψη ...................................................................................................................................................... v
Acknowledgments ........................................................................................................................................ vi
CHAPTER 1 .................................................................................................................................................... 1
1 Introduction .......................................................................................................................................... 1
1.1 Simple Storage Media ................................................................................................................... 2
1.1.1 Batteries ................................................................................................................................ 2
1.1.2 Supercapacitors ..................................................................................................................... 3
1.2 Complex structures as storage media ........................................................................................... 5
1.2.1 Hybrid battery-SC structure .................................................................................................. 5
1.2.2 Reconfigurable SCs banks ..................................................................................................... 6
1.3 Thesis Contribution ....................................................................................................................... 8
CHAPTER 2 .................................................................................................................................................. 10
2 System Description and Proposed Solution ........................................................................................ 10
2.1 System Specifications and Challenges ........................................................................................ 10
2.1.1 Challenges ........................................................................................................................... 10
2.1.2 Specifications and restrictions ............................................................................................ 11
2.2 Proposed Architecture ................................................................................................................ 12
2.2.1 Power management unit .................................................................................................... 13
2.2.2 Control unit ......................................................................................................................... 13
2.2.3 Complementary circuits. ..................................................................................................... 14
3 Circuit blocks ....................................................................................................................................... 15
3.1 Switches ...................................................................................................................................... 15
3.2 Bias circuit ................................................................................................................................... 16
3.2.1 Bias circuit design ................................................................................................................ 16
3.2.2 Bias circuit simulation results ............................................................................................. 17
3.3 Comparators and delay lines ...................................................................................................... 18
3.3.1 Comparator design .............................................................................................................. 18
3.3.2 Comparator simulation results ........................................................................................... 19
3.3.3 Delay line ............................................................................................................................. 20
3.4 LDO .............................................................................................................................................. 21
3.4.1 LDO design .......................................................................................................................... 22
3.4.2 LDO simulation results ........................................................................................................ 24
3.5 Bandgap reference and Buffer .................................................................................................... 30
3.5.1 Bandgap reference design .................................................................................................. 31
3.5.2 Bandgap reference simulation results ................................................................................ 32
3.5.3 Buffer design ....................................................................................................................... 35
3.5.4 Buffer simulation results ..................................................................................................... 36
4 System architecture and layout design ............................................................................................... 38
4.1 System architecture design. ........................................................................................................ 38
4.1.1 Delay capacitors .................................................................................................................. 39
4.1.2 Voltage divider for threshold voltages ................................................................................ 40
4.1.3 Reference node of comparators ......................................................................................... 40
4.2 Physical design (layout) ............................................................................................................... 41
4.2.1 Switch Interconnections ..................................................................................................... 42
4.2.2 Matching techniques. ......................................................................................................... 42
4.3 System simulation ....................................................................................................................... 45
4.3.1 Charging .............................................................................................................................. 45
4.3.2 Discharging .......................................................................................................................... 48
4.4 Chip redesign .............................................................................................................................. 50
5 Conclusions and future work .............................................................................................................. 52

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List of tables

Table 1. Comparison of batteries and SCs [8]. .............................................................................................. 4
Table 2. Results of LDO in typical condition. ............................................................................................... 24
Table 3. Results of LDO in worst power condition. ..................................................................................... 24
Table 4. Results of LDO in worst speed condition. ..................................................................................... 25
Table 5. Results of LDO in worst one condition. ......................................................................................... 25
Table 6. Results of LDO in worst zero condition. ........................................................................................ 25
Table 7. Typical performance of the bandgap reference circuit ................................................................. 32
Table 8. Performance of the bandgap reference circuit in the worst power condition (low temperature)
.................................................................................................................................................................... 32
Table 9. Performance of the bandgap reference circuit in the worst speed condition (high temperature)
.................................................................................................................................................................... 33
Table 10. Performance of the bandgap reference circuit in the worst one condition ............................... 33
Table 11. Performance of the bandgap reference circuit in the worst case zero ...................................... 33
List of figures

Figure 1. Internet of Things architecture for healthcare [1]. ........................................................................ 1
Figure 2. Power and energy density of SCs and batteries [6]. ...................................................................... 3
Figure 3. Categories and materials of supercapacitors [9]. .......................................................................... 4
Figure 4. Architecture of hybrid storage media [10]. ................................................................................... 5
Figure 5. General model of 2N SCs structure [21]. ........................................................................................ 6
Figure 6. Four SCs structure with the switches derived from the general model [22]. ................................ 7
Figure 7. Charging phase of the SCs structured compared with fixed C/4 and fixed C*4 capacitors [22]. .. 7
Figure 8. Discharging phase of the SCs structured compared with fixed C/4 and fixed C*4 capacitors [22].
...................................................................................................................................................................... 8
Figure 9. General architecture of the system. ............................................................................................ 10
Figure 10. Proposed architecture of the system. ........................................................................................ 12
Figure 11. Bulk regulation technique for PMOS switch. ............................................................................. 16
Figure 12. Bias circuit architecture. ............................................................................................................ 17
Figure 13. Power consumption of bias circuit for different supply voltages and temperatures in typical
condition. .................................................................................................................................................... 17
Figure 14. Power consumption of the bias circuit for different supply voltages and temperatures in worst
speed condition. ......................................................................................................................................... 18
Figure 15. Proposed architecture for both comparators. ........................................................................... 19
Figure 16. Transient response of the comparator in the output in typical condition, when a sine at the
input is applied. ........................................................................................................................................... 20
Figure 17. Transient response of the comparator in the output in worst speed condition, when a sine at
the input is applied. .................................................................................................................................... 20
Figure 18. Delay line architecture. .............................................................................................................. 21
Figure 19. Topology of a classic LDO. .......................................................................................................... 21
Figure 20. Operation regions of LDO. ......................................................................................................... 22
Figure 21. Proposed architecture of the error amplifier of LDO with the pass device. .............................. 23
Figure 22. Output of LDO, when supply voltage and temperature vary. ................................................... 26
Figure 23. PSRR of LDO for different supply voltages in typical condition ................................................. 26
Figure 24. PSRR of LDO for different supply voltages in worst one condition ........................................... 27
Figure 25. Gain Bandwidth and Phase Margin of LDO in typical condition. ............................................... 27
Figure 26. Gain Bandwidth and Phase Margin of LDO in worst zero. ......................................................... 28
Figure 27. Transient analysis of LDO when the input voltage V and load current I variations in typical
IN LOAD
condition. .................................................................................................................................................... 29
Figure 28. Transient analysis of LDO when the input voltage V and load currentI variations in worst
IN LOAD
one condition. ............................................................................................................................................. 29
Figure 29. Architecture for the bandgap reference circuit proposed in [29]. ............................................ 31
Figure 30. Temperature dependence of the bandgap reference circuit in typical condition. ................... 34
Figure 31. Temperature dependence of the bandgap reference circuit in worst zero condition. ............. 34
Figure 32. PSRR result of the bandgap reference in typical condition. ...................................................... 35
Figure 33. PSRR result of the bandgap reference in worst speed condition. ............................................. 35
x