Simultaneous Scheduling and Allocation for Cost Constrained

175 Pages·2002·0.73 MB·English

DAC91, Pages 2-7
Simultaneous Scheduling and Allocation for Cost Constrained Optimal Architectural
Synthesis

Catherine H. Gebotys and Mohamed I. Elmasry
Department of Electrical and Computer Engineering,
University of Waterloo, Waterloo, Ontario. N2L 3G1 Canada

An integer programming (IP) model, which simultaneously schedules and allocates functional
units, registers, and busses, is presented for synthesizing cost-constrained globally optimal
architectures. This research is important for industry by providing optimal schedules which
minimize interconnect costs and interface to analog and asynchronous processes, since these are
seen as key to synthesizing high performance architectures. A partially structured tight IP
formulation of the architectural synthesis problem provides globally optimal schedules for
peicewise linear cost functions, using branch and bound, in execution times faster than previous
research. This research breaks new ground by 1. simultaneously scheduling and allocating
hardware resources including interconnect, 2. support for asynchronous and analog interfaces,
and 3. guaranteeing globally optimal solutions in practical execution times.

References
1. P. G. Paulin, "Force Directed Scheduling," IEEE Transactions on CAD, pp. 661-679 (1989).
2. J. Lee, Y. Hsu, and Y. Lin, "A New Integer Linear Programming Formulation for the Scheduling Problem in Data
Path Synthesis," ICCAD, (1989).
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Digital Logic," IEEE Transactions on CAD, (1983).
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on CAD, (1989).
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DAC91, Pages 8-13
Synthesis of Application-Specific Multiprocessor Architectures

Shiv Prakash and Alice C. Parker
Electrical Engineering – Systems, University of Southern California
Los Angeles, CA 90089-0781
Abstract
This paper describes a formal technique for automated synthesis of multiprocessor systems for
given applications. The application task is specified in terms of a graph, and the architecture
synthesized includes a set of processing elements and the interconnection architecture between
them. The technique generates a task execution schedule along with the architecture. The
technique involves creation of a Mixed Integer-Linear Programming (MILP) model and solution
of the model. Synthesis of a few example architectures is reported.

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DAC91, Pages 14-19
Constraint Improvements for MILP-Based Hardware Synthesis

Lou Hafer
School of Computing Science, Simon Fraser University
Burnaby, B.C., V5A 1S6

Abstract
This paper describes work which improves the performance of MILP-based hardware synthesis
by tightening the constraint system. Two improvements are described. The first estimates the
minimum time that a value can usefully exist and adds constraints which express this. The
second reformulates scheduling constraints which prevent component usage conflicts to better
match a novel LP-based branch-and-bound algorithm.

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DAC91, Pages 20-25
ILLIADS: A New Fast MOS Timing Simulator Using Direct Equation-Solving Approach

Y.-H. Shih and S. M. Kang
Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Urbana, Illinois 61801

ABSTRACT
By using a direct equation solver of a new MOS circuit primitive with piecewise-linear
approximation of electrical waveforms, ILLIADS has been shown to be significantly superior to
existing fast MOS timing simulators in both accuracy and speed. For simulation of medium-size
digital circuits containing a few hundred transistors (n), ILLIADS has already achieved an O(n),
about 3n or more, speedup over SPICE with error less than 3%. The sizes of circuits ILLIADS
can handle is not limited by this method and the speedup is expected to grow with the circuit
size. The possibility of generating false waveforms caused by merging of parallel transistors is
reduced. A modified waveform relaxation algorithm is used to handle circuits with feedbacks as
demonstrated through simulation of a ring oscillator and a updown counter.

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DAC91, Pages 26-31
ADAPTS: A Digital Transient Simulation Strategy for Integrated Circuits

Alexander D. Stein, Tuyen V. Nguyen, Binay J. George, Ronald A. Rohrer,
Department of Electrical and Computer Engineering
Carnegie Mellon University, Pittsburgh, Pennsylvania

Abstract
Activity Driven Adaptive Partitioning Transient Simulation (ADAPTS) has been developed to
bridge the gap between circuit and logic simulation. ADAPTS can accept analytical models for
arbitrary multi-terminal elements and can control the accuracy versus efficiency tradeoff
automatically. In addition, ADAPTS can simulate stiff circuits efficiently and accurately.

References
[1] B.R. Chawla, H.K. Gummel, and P. Kozak. "MOTIS - An MOS timing simulator," IEEE Trans. on Circuits and
Systems, CAS-22(12):901-910, December 1975.
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techniques. Prentice Hall, 1975.
[3] Norman P. Jouppi. "Timing Analysis and Performance Improvement of MOS VLSI Designs," IEEE Trans.
Computer-Aided Design, CAD-6(4):650-665, July 1987.
[4] Y. H. Kim, J. E. Kleckner, R. A. Saleh, and A. R. Newton. "Electrical-logic simulation," IEEE Int. Conf. on
CAD, pages 7-10, 1984.
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1965.
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UCB/ERL M520, University of California, Berkeley, May 1975.
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November 1989, pages 248-251.
DAC91, Pages 32-37
Efficient Simulation of Bipolar Digital Ics

Chandramouli Visweswariah
IBM T. J. Watson Research Center, Yorktown Heights, NY 10598

Ronald A. Rohrer
Dept. of ECE, Carnegie Mellon University, Pittsburgh, PA 15213

Abstract
High-performance logic circuitry for mainframe computers is most commonly implemented in
the bipolar emitter-coupled logic (ECL) family. BiCMOS circuits are becoming increasingly
common in digital applications. The simulation of such circuits with a general purpose circuit
analysis tool is very compute-intensive. This paper presents an efficient simulation methodology
for ECL bipolar designs. By using an event-driven scheme to exploit the underlying latency in
the circuit and by using simplified device models, efficient simulation is accomplished while
staying within tolerable error bounds.

References
[1] B. R. Chawla, H. K. Gummel, and P. Kozak. MOTIS - an MOS timing simulator. IEEE Trans. on Circuits and
Systems, CAS-22(12):901-910, December 1975.
[2] C-F. Chen, C-Y. Lo, H. N. Nham, and P. Subramaniam. The second generation MOTIS mixed-mode simulator.
Proc. 21st Design Automation Conference, pages 10-16, 1984.
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of VLSI. Proc. IEEE JCCD, October 1980. Rye, NY.
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Conference on Computer-Aided Design (ICCAD), pages 62-65, November 1988.
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University of California, Berkeley, May 1975.
[7] A. R. Newton and A. L. Sangiovanni-Vincentelli. Relaxation based electrical simulation. IEEE Trans. on CAD of
ICs and Systems, CAD-3(4):308-330, October 1984.
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integrated circuits. Proc. Design Automation Conference, June 1991.
[12] C. Visweswariah and R. A. Rohrer. Piecewise approximate circuit simulation. IEEE International Conference
on Computer-Aided Design (ICCAD), November 1989.
[13] C. Visweswariah and R. A. Rohrer. Piecewise approximate circuit simulation. IEEE Trans. on CAD of ICs and
Systems, June 1991.
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DAC91, Page 38
PANEL: GLOBAL STRATEGIES FOR ELECTRONIC DESIGN

Chair: Harvey Jones - Synopsys, Inc., Mountain View, CA

Electronic industries have arrived at a major crossroads. Is the ASIC business a CAD business or
a "fab" business?

By the end of the decade, Japan estimates that IC manufacturing plants will cost up to ¥1 trillion.
According to some industry estimates, ASIC and ASSP now account for more worldwide
revenues than both memories and microprocessors. In an attempt to avoid the commodity
pressures that erode competitiveness, ASIC vendors are providing proprietary mega-cells,
standard RISC processor cores, and associated software development systems for their ASICs.
Does this development represent ASIC vendor value-added or is it designed to lock in
customers? Do these strategies conflict with the goals of many of today's system companies?

How will both system and semiconductor companies add value to a commercial CAD system?
Will designers be happy with "industry-standard" CAD systems?

Building a chip with 10M transistors is relatively straightforward today. The problem has
become deciding how best to use all the transistors. Is computeraided product design an
important new frontier or is CAD only useful for implementation?

Panel Members:
Thomas Bruggere - Mentor Graphics Corp., Beaverton, OR
Wilfred Corrigan - LSI Logic Corp., Milpitas, CA
Joseph Costello - Cadence Design Systems, Inc., Santa Clara, CA
John East - Actel Corp., Sunnyvale, CA
Susumu Kohyama - Toshiba Corp., Tokyo, Japan
Edward McCracken - Silicon Graphics, Inc., Mountain View, CA
DAC91, Pages 39-44
Topological Routing in SURF: Generating a Rubber-Band Sketch

Wayne Wei-Ming Dai, Tal Dayan, David Staepelaere
Computer Engineering, University of California, Santa Cruz
Santa Cruz, CA 95064 USA

ABSTRACT
A multi-layer topological router for generating rubber-band sketches is described. The router
uses hierarchical top-down partitioning to perform global routing for all nets simultaneously. It
combines this with successive refinement to help correct mistakes made before more detailed
local information is discovered. Layer assignment is performed during the partitioning process to
generate routing that has fewer vias and is not restricted to one-layer one-direction. The local
router uses a region connectivity graph to generate shortest-path rubber-band routing.

References
[1] R.E. Burkhard and U. Derigs. Assignment and Matching Problems: Solution Methods with Fortran-Programs.
Springer Verlag, 1980.
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Foundations of Computer Science, pages 65-73, 1984.
[4] Wayne Wei-Ming Dai, Raymond Kong, Jeffrey Jue, and Masao Sato. Rubber band routing and dynamic data
representation. In IEEE International Conf. on Computer Aided Design, 1990.
[5] Wayne Wei-Ming Dai, Raymond Kong, and Masao Sato. Routability of a rubber-band sketch. In Proceedings of
the 28th Design Automation Conference, 1991.
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DAC91, Pages 45-48
Routability of a Rubber-Band Sketch

Wayne Wei-Ming Dai, Raymond Kong, Masao Sato*
Computer Engineering, University of California, Santa Cruz
Santa Cruz, CA 95064 USA
* Dept. of Information Engineering, Takushoku University, Japan

ABSTRACT
The SURF routing system employs a grid-less flexible routing topology called the rubber-band
sketch, where each wire is treated as a rubber-band. One of the features of the SURF system is to
provide an efficient routability test for this rubber-band topology. This paper presents the key
concepts and necessary algorithms to perform this routability test.

References
[1] R. Cole and A. Siegel. River routing every which way, but loose. In Proceeding of 25th Annual Symposium on
Foundations of Computer Science, pages 65-73, 1984.
[2] Wayne Wei-Ming Dai, Raymond Kong, Jeffrey Jue, and Masao Sato. Rubber band routing and dynamic data
representation. In IEEE International Conf. on Computer Aided Design, 1990.
[3] C.E. Leiserson and F.M. Maley. Algorithms for routing and testing routability of planar VLSI layouts. In
Proceedings of the 17th Annual ACM Symposium on Theory of Computing, pages 69-78, 1985.