Simulated Annealing with min-cut and greedy perturbations

66 Pages·2016·1.33 MB·English

by  Brian J. Cody

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Brian J. Cody
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Simulated Annealing
with
Min-Cut and Greedy Perturbations
by
Brian J Cody
A Thesis Submitted in Partial Fulfillment of the Requirements for the Degree of
Master of Science in Computer Engineering
Supervised by
Assistant Professor of Computer Engineering Dr. Marcin Lukowiak
Department of Computer Engineering
Kate Gleason College of Engineering
Rochester Institute of Technology
Rochester, New York
July 2006
Approved By:
Marcin lukowiak
Dr. Marcin Lukowiak
Assistant Professor of Computer Engineering
Primary Advisor
Stanisfaw Radziszowski
Dr. Stanislaw Radziszowski
Professor of Computer Science
Pratapa V. Reddy
Dr. Pratapa V. Reddy
Professor of Computer Engineering
Thesis Release Permission Form
Rochester Institute of Technology
Kate Gleason College of Engineering
Title: Simulated Annealing with Min-Cut and Greedy Perturbations
I, Brian J Cody, hereby grant permission to the Wallace Memorial Library reporduce
my thesis in whole or part.
Brian Cody
Brian J Cody
I
Date
Dedication
This thesis is dedicatedto my parents, Howard andPat, and to April, fortheir support that
made this possible.
in
Acknowledgments
I'd like to acknowledge Dr. Marcin Lukowiak for his supervision and dedication during
this work. I would also like to thank my committee members Dr. Stanislaw Radziszowski
andDr. Pratapa V. Reddy fortheir supportandguidance.
iv
Abstract
Custom integrated circuit design requires an ever increasing number of elements to be
placed on a physical die. The process of searching for an optimal solution is NP-hard so
heuristics arerequiredto achieve satisfactoryresults undertime constraints.
Simulated Annealing is an algorithm which uses randomly generated perturbations to
adjust a single solution. The effect ofageneratedperturbationis examinedby a costfunc
tion whichevaluates the solution. Iftheperturbationdecreases the cost, it is accepted. Ifit
increases the cost, it is accepted probabilistically. Such an approach allows the algorithm
to avoid local minima and find satisfactory solutions. One problem faced by Simulated
Annealing is that it can take a very large number of iterations to reach a desired result.
Greedyperturbations useknowledge ofthe systemto generate solutions whichmay be sat
isfactory after fewer iterations than non-greedy, howeverprevious work has indicated that
the exclusive use ofgreedy perturbations seems to result in a solution constrained to local
minima.
Min-cutis aprocedure in which a graph is split into twopieces withthe least intercon
nection possible between them. Using this with a placement problem helps to recognize
components whichbelongtothesamefunctionalunitandthusenhanceresultsofSimulated
Annealing. The feasibility ofthis approachhas been assessed.
Hardware, through parallelization, can be used to increase the performance of algo
rithms by decreasing runtime. The possibility of increased performance motivated the
exploration of the ability to model greedy perturbations in hardware. The use of greedy
perturbations while avoiding local minima was also explored.
Contents
Dedication iii
Acknowledgments iv
...
Abstract v
.
1 Introduction 1
....
1.1 Motivation 4
1.2 Priorwork 5
2 Background 6
.......
2.1 Placement 6
2.2 Annealing and SimulatedAnnealing 7
2.2.1 Costfunction 7
2.2.2 Probabilistic criterion 9
2.2.3 Cooling schedule 10
2.3 Greediness in algorithms 11
2.4 Force directedtechnique 12
2.5 Min-cut 14
2.6 Row-based design 16
2.7 Enhancementlimitations 18
2.8 LEF/DEFfile specification 19
2.8.1 Library Exchange Format 19
2.8.2 DesignExchangeFormat 20
2.9 Perturbations 22
3 Software Implementation 23
. .
3.1 Framework 23
3.2 Implementation details 24
3.2.1 Row-based direction 24
vi
3.2.2 Overlap detection 25
3.2.3 Overlap correction 26
3.3 Force directedtechnique 26
3.3.1 Single moves 27
3.3.2 Swaps 28
3.4 Min-cut 30
3.5 Cooling schedule 32
3.6 Results 34
3.6.1 Benchmark selection 34
3.6.2 Row-based implementation 34
3.6.3 Min-cut 35
3.6.4 Force directedtechnique 36
3.6.5 Dynamic cooling schedule 39
3.6.6 Performance comparison 40
4 Hardware Model 42
4.1 Framework 42
4.2 Overlap detection 42
4.3 Force directedtechnique 44
4.3.1 Limiting net information . ... 44
4.3.2 Division 45
4.3.3 Controllerlogic 47
. . .
4.4 Results 48
4.4.1 VHDL dividerlogic 48
4.4.2 Row-based overlap detection 48
4.4.3 Speedup 49
5 Conclusions 51
...
5.1 Discussion 51
5.2 Future work 52
5.2.1 Software implementation 52
Bibliography 54
...
vn
List Figures
of
1.1 The number oftransistors inIntel PC processors by year 4
2.1 A demonstration ofanet's cost and an overlap's cost 8
2.2 Probability that amove is accepted attemperatures 10
2.3 The effectofalphaparameters on temperature 11
2.4 A function with multiple minima 12
2.5 A springrepresentation ofacircuit's internal stresses 13
2.6 Demonstration ofnode combining 15
2.7 Min-cutmethod 16
2.8 Overlap detectionregions 17
3.1 Row implementation 24
3.2 Bounding boxes ofa standard andforcedperturbation 27
3.3 Netversus graphrepresentations 30
3.4 A constantcooling schedule versus avariable one 33
3.5 Mincutresults from ISCAS cl355 37
3.6 Forcedresults from c499 test-bench (202 cells) 38
3.7 Forcedresults from ibmOl test-bench (12028 cells) 38
4.1 Block diagram ofhardware basedrow overlap detection 43
4.2 Division estimation errorwith bestfit 46
4.3 Waveform ofdividerlogic 48
4.4 Row with overlap 49
4.5 Waveform ofrow-based overlap detection logic 49
vni
List Tables
of
3.1 Portion ofSAruntime devotedto costtasks 35
3.2 Min-cutperformanceresults 36
3.3 Min-cuttiming information 36
3.4 Perturbation acceptancepercentage 39
3.5 Effects ofa smartercooling schedule 40
3.6 Placementtool comparison 41
3.7 Comparison toprevious SA implementation 41
4.1 Difference in force directed technique runs by wire length when four nets
used 44
4.2 Numberofdivisions performedforarunon twotestbenches 45
4.3 Divisionestimation chartwith error 46
4.4 Difference in force-directedtechniqueruns when estimation is used 47
....
4.5 Hardwaremodelperformancebetweentheprevious andcurrentimplemen
tation 50
4.6 Hardware modelperformance comparison to software implementation 50
...
IX