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Serial-Data Computation PDF

245 Pages·1987·5.899 MB·English
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SERIAL-DATA COMPUTATION THE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND COMPUTER SCIENCE VLSI, COMPUTER ARCHITECTURE AND DIGITAL SIGNAL PROCESSING Consulting Editor Jonathan Allen Other books in the series: Logic Minimization Algorithms for VLSI Synthesis, R. K. Brayton, G. D. Hachtel, C. T. McMullen, and A. L. Sangiovanni-Vincentelli. ISBN 0-89838-164-9. Adaptive Filters: Structures, Algorithms, and Applications, M. L. Honig and D. G. Messerschmitt. ISBN 0-89838-163-0. Computer-Aided Design and VLSI Device Development, K. M. Cham, S.-Y. Oh, D. Chin and J. L. Moll. ISBN 0-89838-204-1. Introduction to VLSI Silicon Devices: Physics, Technology and Characterization, B. El-Kareh and R. J. Bombard. ISBN 0-89838-210-6. Latchup in CMOS Technology: The Problem and Its Cure, R. R. Troutman. ISBN 0-89838-215-7. Digital CMOS Circuit Design, M. Annaratone. ISBN 0-89838-224-6. The Bounding Approach to VLSI Circuit Simulation, C. A. Zukowski. ISBN 0-89838-176-2. Multi-Level Simulation for VLSI Design, D. D. Hill and D. R. Coelho. ISBN 0-89838-184-3. Relaxation Techniques for the Simulation of VLSI Circuits, J. White and A. Sangiovanni-Vincentelli. ISBN 0-89838-186-X. VLSI CAD Tools and Applications, Wolfgang Fichtner and Martin Morf, Editors. ISBN 0-89838-193-2. A VLSI Architecture for Concurrent Data Structures, W. J. Dally. ISBN 0-89838-235-1. Yield Simulation for Integrated Circuits, D. M. H. Walker. ISBN 0-89838-244-0. VLSI Specification, Verification and Synthesis, Graham Birtwistle and P. A. Subrahmanyam. ISBN 0-89838-246-7. Fundamentals of Computer-Aided Circuit Simulation. W. J. McCalla. ISBN 0-89838-248-3. SERIAL-DATA COMPUTATION Stewart G. Smith University of Edinburgh and Peter B. Denyer University of Edinburgh .... " KLUWER ACADEMIC PUBLISHERS Boston/DordrechtiLancaster Distributors for North America: Kluwer Academic Publishers 101 Philip Drive Assinippi Park Norwell, Massachusetts 02061, USA Distributors for the UK and Ireland: Kluwer Academic Publishers MTP Press Limited Falcon House, Queen Square Lancaster LAI IRN, UNITED KINGDOM Distributors for all other countries: Kluwer Academic Publishers Group Distribution Centre Post Office Box 322 3300 AH Dordrecht, THE NETHERLANDS Library of Congress Cataloging-in-Publication Data Smith, Stewart G. Serial-data computation / by Stewart G. Smith and Peter B. Denyer. p. cm. - (Kluwer international series in engineering and computer science; no. 39) Bibliography: p. Includes index. ISBN-I3: 978-1-4612-9201-2 e-ISBN-13: 978-1-4613-2015-9 DOl: 10.1007/978-1-4613-2015-9 I. Integrated circuits-Very large scale integration-Design and construction-Data processing. 2. Silicon compilers. I. Denyer, P. B. (Peter B.), 1953- II. Title. III. Series: Kluwer international series in engineering and computer science; SECS 39. TK7874.S623 1988 87-24530 621.381 '73-dcI9 CIP Copyright © 1988 by Kluwer Academic Publishers, Boston. Softcover reprint of the hardcover 1st edition 1988 All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means mechanical, photocopying, recording, or otherwise, without the prior written permission of the publishers, Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, MA 02061. Contents Chapter 1: INTRODUCTION........................................... 1 The case for serial-data techniques............................ 1 The case against serial-data techniques ...................... 3 Historical overview of bit-serial techniques ................. 4 Final comments .................................................... 8 Chapter 2: THE FIRST GENERATION ............................. 9 FIRST ................................................................. 10 The FIRST primitive set ......................................... 13 Bit-serial systems design ......................................... 14 Case study ........................................................... 20 FFT subsystem design ............................................ 21 Filterbank subsystem design .......... .................... ...... 24 System specifications .............................................. 25 Initial design issues and decisions ............................. 25 Functional design - the soft model ............................ 30 Physical design - the hard model .............................. 37 Test strategy and confidence levels ............................ 44 A critical appraisal of FIRST .......... ......... ........... ..... 46 Chapter 3: RUDIMENTS ................................................ 49 Issues of space and time ......................................... 49 Control...... ........... ............ ..... .......... ........... ........ 50 Two's complement integer coding ............................. 51 Fundamental building blocks - the atoms ................... 53 Numerical principles of serial-data additive operations.. 63 Partitioning issues ................................................. 68 SERIAL-DATA COMPUTATION VI Chapter 4: TWO'S COMPLEMENT MULTIPLICATION .... 69 Derivation from bit-parallel architectures ................... 71 Scrutiny of two serial-data multipliers ........................ 72 Word-level equivalent architectures........................... 86 Comparison of the SIP and Lyon multipliers ............... 87 SeriaVparallel multiplier environments ....................... 90 Other approaches .................................................. 92 Chapter 5: AREA-SAVING TECHNIQUES ........................ 97 Overview of vector computation ............................... 98 Symmetric-coded seriaVparallel muiltiplier .................. 100 SeriaVparallel inner-product computer ....................... 104 Architectural case studies ....................................... 109 Architectural synthesis ........................................... 114 Distributed arithmetic in context .............................. 116 Cascading DA modules .......................................... 117 Incremental computation of squares/sums of squares ..... 119 Final comments .................................................... 129 Chapter 6: THROUGHPUT ENHANCEMENT ................... 131 Twin-pipe ........................................................... 133 Radix-4 .............................................................. 140 Multi-precision ..................................................... 150 Interfacing between operational domains .................... 153 The automultiplier ................................................ 157 Final comments .................................................... 161 CONTENTS vii Chapter 7: THE SECOND GENERATION ......................... 165 Process-independence ............................................ 169 Overview of SECOND ............................................ 171 PRIMITIVE specification ( design capture) ................. 172 PRIMITIVE verification (behavioural simulation) ....... 174 Semi-custom PRIMITIVE implementation ................. 175 Custom PRIMITIVE implementation ........................ 177 Other approaches.................................................. 186 Final comments .................................................... 187 Chapter 8: CONCLUDING REMARKS ............................. 189 References .................................................................... 193 Appendix A - COMPLEX MULTIPLIER ........................... 211 Appendix B - LOGIC SYNTHESIS .................................... 225 Index ........................................................................... 237 Preface This book is concerned with advances in serial-data computa tional architectures, and the CAD tools for their implementation in silicon. The bit-serial tradition at Edinburgh University (EU) stretches back some 6 years to the conception of the FIRST silicon compiler. FIRST owes much of its inspiration to Dick Lyon, then at Xerox P ARC, who proposed a 'structured-design' methodology for construction of signal processing systems from bit-serial building blocks. Based on an nMOS cell-library, FIRST automates much of Lyon's physical design process. More recently, we began to feel that FIRST should be able to exploit more modern technologies. Before this could be achieved, we were faced with a massive manual re-design task, i.e. the porting of FIRST cell-library to a new technology. As it was to avoid such tasks that FIRST was conceived in the first place, we decided to move the level of user-specification much nearer to the silicon level (while still hiding details of transistor circuit design, place and route etc., from the user), and by so doing, enable the specification of more functionally powerful libraries in technology-free form. The results of this work are in evidence as advances in serial-data design techniques, and the SECOND silicon compiler, introduced later in this book. These achievements could not have been accomplished without help from various sources. We take this opportunity to thank Profs. Jeff Collins and John Mavor, who as successive EE Heads of Department at EU have done so much to create the infrastructure which we take for granted. We wish to acknowledge our EU col leagues who have contributed to the development of the bit-serial tradition here: Dave Renshaw (FIRST), Alan Murray (testability and clocking), and Mike McGregor (single-phase and twin-pipe ideas). x SERIAL-DATA COMPUTATION Next we wish to include special thanks to the researchers at EU who have contributed to the development of the tools detailed in Chapter 7. These are: Michael Keightley (EU) and Shigenori Nagara (NEC Corp.) for full-custom layout synthesis, and Bob Mhar (EU) and Laurence Turner (University of Calgary) for semi-custom netlist generation. We also wish to thank Prof. Kunihiro Asada (University of Tokyo), whose MOSYN tools inspired our work on logic BLOCK synthesis. Thanks also to John McCanny (Queen's University, Belfast) and David Rees (EU) for their constructive cri ticism of the text. Finally we acknowledge financial support from the UK Science and Engineering Research Council (under Grant No. GRC 67333) and the European Space Agency (under Contract No. 6275/85/NLlPP) . List of abbreviations CSA Carry-save adder CSAS Carry-save add-shift DA Distributed arithmetic IP Inner-product JKM Jackson, Kaiser & McDonald LS Least-significant LSB Least-significant bit MB Modified-Booth MS Most -significant MSB Most-significant bit OB Offset -binary PIP Partial inner-product PIPO Parallel-in-parallel-out PISO Parallel-in-serial-out PP Partial product PPP Parallel partial product PPS Partial product sum SIPO Serial-in-parallel-out SISO Serial-in-serial-out SPP Serial partial product SIP SeriaUparallel 2C Two's complement

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