Self-Cal 12-Bit + Serial I/O ADC + MUX & Sample/Hold

52 Pages·2015·2.09 MB·English

ADC12030, ADC12032, ADC12034
ADC12038, ADC12H030, ADC12H032
ADC12H034, ADC12H038
www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013
Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
CheckforSamples:ADC12030,ADC12032,ADC12034,ADC12038,ADC12H030,ADC12H032,ADC12H034,ADC12H038
FEATURES • SingleSupply 5V±10%
1
• SerialI/O(MICROWIRECompatible) • Powerconsumption33mW(max)
2
• 2,4,or8ChanDifferentialor Single-Ended – Powerdown100μW(typ)
Multiplexer
DESCRIPTION
• AnalogInputSample/HoldFunction
NOTE: Some of these devices may be obsolete
• PowerDownMode
and are described and shown here for reference
• VariableResolutionand ConversionRate only.Seeourwebsiteforproduct availability.
• ProgrammableAcquisitionTime
The ADC12030, and ADC12H030 families are 12-bit
• VariableDigitalOutputWordLengthand plus sign successive approximation Analog-to-Digital
Format Converters with serial I/O and configurable input
• NoZeroorFullScaleAdjustmentRequired multiplexers. The ADC12034/ADC12H034 and
ADC12038/ADC12H038 have 4 and 8 channel
• FullyTestedand Ensuredwitha4.096V
multiplexers, respectively. The differential multiplexer
Reference
outputs and ADC inputs are available on the
• 0Vto5VAnalogInputRangewithSingle5V MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2 pins.
PowerSupply The ADC12030/ADC12H030 has a two channel
multiplexer with the multiplexer outputs and ADC
• NoMissingCodesover Temperature
inputs internally connected. The ADC12030 family is
tested with a 5 MHz clock, while the ADC12H030
APPLICATIONS
family is tested with an 8 MHz clock. On request,
• MedicalInstruments these ADCs go through a self calibration process that
adjusts linearity, zero and full-scale errors to less
• ProcessControlSystems
than±1LSBeach.
• TestEquipment
The analog inputs can be configured to operate in
KEY SPECIFICATIONS various combinations of single-ended, differential, or
pseudo-differential modes. A fully differential unipolar
• Resolution12-bitplussign analog input range (0V to +5V) can be
• 12-bitplussignconversiontime accommodated with a single +5V supply. In the
differential modes, valid outputs are obtained even
– ADC12H30family5.5μs(max)
whenthenegativeinputsaregreaterthanthe positive
– ADC12030family8.8 μs(max)
becauseofthe12-bitplussignoutput dataformat.
• 12-bitplussignthroughputtime
The serial I/O is configured to comply with NSC
– ADC12H30family8.6μs(max) MICROWIRE. For voltage references see the
– ADC12030family14 μs(max) LM4040,LM4050orLM4041.
• IntegralLinearityError±1LSB(max)
1
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof
TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
Alltrademarksarethepropertyoftheirrespectiveowners.
2
PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©1999–2013,TexasInstrumentsIncorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarilyincludetestingofallparameters.
ADC12030, ADC12032, ADC12034
ADC12038, ADC12H030, ADC12H032
ADC12H034, ADC12H038
SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com
ADC12038 Simplified Block Diagram
Connection Diagram
TopView TopView
Figure1.16-PinWideBody Figure2. 20-PinWideBody
SOICPackage SOICPackage
SeePackageNumber DW0016B SeePackageNumber DW0020B
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ADC12H038
ADC12030, ADC12032, ADC12034
ADC12038, ADC12H030, ADC12H032
ADC12H034, ADC12H038
www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013
TopView TopView
Figure3. 24-PinWideBody Figure4.28-PinWideBody
SOIC,PDIP,SSOPPackages SOICPackage
SeePackageNumbersDW0024B,NAM0024D, SeePackageNumber DW0028B
DB0024A
PINDESCRIPTIONS
PinName PinDescription
AnalogInputstotheMUX(multiplexer).AchannelinputisselectedbytheaddressinformationattheDIpin,which
isloadedontherisingedgeofSCLKintotheaddressregister(SeeTable2,Table3,andTable4).Thevoltage
CH0thruCH7
appliedtotheseinputsshouldnotexceedV +orgobelowV -orbelowGND.Exceedingthisrangeonan
A A
unselectedchannelmaycorruptthereadingofaselectedchannel.
COM Analoginputpinthatisusedasapseudogroundwhentheanalogmultiplexerissingle-ended.
MUXOUT1 MultiplexerOutputpins.Ifthemultiplexerisused,thesepinsshouldbeconnectedtotheA/DINpins,directlyor
MUXOUT2 throughanamplifierand/offilter.
ConverterInputpins.MUXOUT1isusuallytiedtoA/DIN1.MUXOUT2isusuallytiedtoA/DIN2.Ifexternalcircuitry
A/DIN1
isplacedbetweenMUXOUT1andA/DIN1,orMUXOUT2andA/DIN2,itmaybenecessarytoprotectthesepins
A/DIN2 againstvoltageoverload..ThevoltageatthesepinsshouldnotexceedV +orgobelowAGND(seeFigure60).
A
DataOutputpin.Thispinisanactivepush/pulloutputwhenCSislow.WhenCSishigh,thisoutputisTRI-STATE.
Theconversionresult(D0–D12)andconverterstatusdataareclockedoutbythefallingedgeofSCLKonthispin.
DO
Thewordlengthandformatofthisresultcanvary(seeTable1).Thewordlengthandformatarecontrolledbythe
datashiftedintothemultiplexeraddressandmodeselectregister(seeTable5).
SerialDatainputpin.ThedataappliedtothispinisshiftedbytherisingedgeofSCLKintothemultiplexeraddress
DI andmodeselectregister.Table2throughTable5showtheassignmentofthemultiplexeraddressandthemode
selectdata.
Thispinisanactivepush/pulloutputwhichindicatesthestatusoftheADC12030/2/4/8.Alogiclowonthispin
EOC indicatesthattheADCisbusywithaconversion,AutoCalibration,AutoZeroorpowerdowncycle.Therisingedge
ofEOCsignalstheendofoneofthesecycles.
AlogiclowisrequiredatthispintoprogramanymodeortochangetheADC'sconfigurationaslistedinMode
ProgrammingTable5.Whenthispinishigh,theADCisplacedinthereaddataonlymode.Whileinthereaddata
onlymode,bringingCSlowandpulsingSCLKwillonlyclockoutthedatastoredintheADCsoutputshiftregister.
CONV
ThedataonDIwillbeneglected.AnewconversionwillnotbestartedandtheADCwillremaininthemodeand/or
configurationpreviouslyprogrammed.Readdataonlycannotbeperformedwhileaconversion,AutoCalorAuto
Zeroareinprogress.
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ADC12H038
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ADC12038, ADC12H030, ADC12H032
ADC12H034, ADC12H038
SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com
PINDESCRIPTIONS(continued)
PinName PinDescription
ChipSelectinputpin.Whenalogiclowisappliedtothispin,therisingedgeofSCLKshiftsthedataonDIintothe
addressregister.ThislowalsobringsDOoutofTRI-STATE.WithCSlowthefallingedgeofSCLKshiftsthedata
resultingfromthepreviousADCconversionoutattheDOoutput,withtheexceptionofthefirstbitofdata.When
CSislowcontinuously,thefirstbitofthedataisclockedoutontherisingedgeofEOC(endofconversion).When
CSistoggledthefallingedgeofCSalwaysclocksoutthefirstbitofdata.CSshouldbebroughtlowwhileSCLKis
low.ThefallingedgeofCSinterruptsaconversioninprogressandstartsthesequenceforanewconversion.
CS WhenCSisbroughtbacklowduringaconversion,thatconversionisprematurelyterminated.Thedatainthe
outputlatchesmaybecorrupted.Therefore,whenCSisbroughtlowduringaconversioninprogress,thedata
outputatthattimeshouldbeignored.CSmayalsobeleftcontinuouslylow.Inthiscaseitisimperativethatthe
correctnumberofSCLKpulsesbeappliedtotheADCinordertoremainsynchronous.AftertheADCsupplypower
isappliedthedeviceexpectstosee13clockpulsesforeachI/Osequence.ThenumberofclockpulsestheADC
expectsisthesameasthedigitaloutputwordlength.Thiswordlengthcanbemodifiedbythedatashiftedinonthe
DOpin.Table5detailsthedatarequired.
DataOutputReadypin.Thispinisanactivepush/pulloutputwhichislowwhentheconversionresultisbeing
DOR
shiftedoutandgoeshightosignalthatallthedatahasbeenshiftedout.
SerialDataClockinput.Theclockappliedtothisinputcontrolstherateatwhichtheserialdataexchangeoccurs.
TherisingedgeloadstheinformationontheDIpinintothemultiplexeraddressandmodeselectshiftregister.This
addresscontrolswhichchanneloftheanaloginputmultiplexer(MUX)isselectedandthemodeofoperationforthe
ADC.WithCSlowthefallingedgeofSCLKshiftsthedataresultingfromthepreviousADCconversionoutonDO,
SCLK
withtheexceptionofthefirstbitofdata.WhenCSislowcontinuously,thefirstbitofthedataisclockedoutonthe
risingedgeofEOC(endofconversion).WhenCSistoggledthefallingedgeofCSalwaysclocksoutthefirstbitof
data.CSshouldbebroughtlowwhenSCLKislow.Theriseandfalltimesoftheclockedgesshouldnotexceed
1µs.
ConversionClockinput.Theclockappliedtothisinputcontrolsthesuccessiveapproximationconversiontime
CCLK
intervalandtheacquisitiontime.Theriseandfalltimesoftheclockedgesshouldnotexceed1µs.
Positiveanalogvoltagereferenceinput.Inordertomaintainaccuracy,thevoltagerangeofV (V =V +−
REF REF REF
V + V −)is1V to5.0V andthevoltageatV +cannotexceedV +.SeeFigure59forrecommended
REF REF DC DC REF A
bypassing.
Thenegativeanalogvoltagereferenceinput.Inordertomaintainaccuracy,thevoltageatthispinmustnotgo
V -
REF belowGNDorexceedV +.(SeeFigure59).
A
PowerDownpin.WhenPDishightheADCispowereddown;whenPDislowtheADCispoweredup,oractive.
PD
TheADCtakesamaximumof250µstopowerupafterthecommandisgiven.
V + Thesearetheanaloganddigitalpowersupplypins.VA+andVD+arenotconnectedtogetheronthechip.These
VA+ pinsshouldbetiedtothesamesupplyvoltageandbypassedseparately(seeFigure59).Theoperatingvoltage
D rangeofV +andV +is4.5V to5.5V .
A D DC DC
DGND Thedigitalgroundpin(seeFigure59).
AGND Theanaloggroundpin(seeFigure59).
Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam
duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
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ADC12H038
ADC12030, ADC12032, ADC12034
ADC12038, ADC12H030, ADC12H032
ADC12H034, ADC12H038
www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013
Absolute Maximum Ratings (1)(2)(3)
PositiveSupplyVoltage (V+=V +=V +) 6.5V
A D
VoltageatInputsandOutputs exceptCH0–CH7and −0.3Vto(V++0.3V)
COM
VoltageatAnalogInputs CH0–CH7andCOM GND−5Vto(V++5V)
|V +−V +| 300mV
A D
InputCurrentatAnyPin (4) ±30mA
PackageInputCurrent (4) ±120mA
PackageDissipationat
T =25°C (5) 500mW
A
ESDSusceptibility (6)
HumanBodyModel 1500V
SolderingInformation
PDIPPackage(10seconds) 260°C
SOICPackage (7)
VaporPhase(60seconds) 215°C
Infrared(15seconds) 220°C
StorageTemperature −65°Cto+150°C
(1) AllvoltagesaremeasuredwithrespecttoGND,unlessotherwisespecified.
(2) AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.OperatingRatingsindicateconditionsfor
whichthedeviceisfunctional,butdonotensurespecificperformancelimits.Forensuredspecificationsandtestconditions,seethe
ElectricalCharacteristics.Theensuredspecificationsapplyonlyforthetestconditionslisted.Someperformancecharacteristicsmay
degradewhenthedeviceisnotoperatedunderthelistedtestconditions.
(3) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityand
specifications.
(4) Whentheinputvoltage(V )atanypinexceedsthepowersupplies(V <GNDorV >V +orV +),thecurrentatthatpinshouldbe
IN IN IN A D
limitedto30mA.The120mAmaximumpackageinputcurrentratinglimitsthenumberofpinsthatcansafelyexceedthepower
supplieswithaninputcurrentof30mAtofour.
(5) ThemaximumpowerdissipationmustbederatedatelevatedtemperaturesandisdictatedbyTmax,θ andtheambienttemperature,
J JA
T .ThemaximumallowablepowerdissipationatanytemperatureisP =(Tmax−T )/θ orthenumbergivenintheAbsolute
A D J A JA
MaximumRatings,whicheverislower.
(6) Thehumanbodymodelisa100pFcapacitordischargedthrougha1.5kΩresistorintoeachpin.
(7) SeeAN450“SurfaceMountingMethodsandTheirEffectonProductReliability”orthesectiontitled“SurfaceMount”foundinanypost
1986LinearDataBookforothermethodsofsolderingsurfacemountdevices.
Operating Ratings (1)(2)
OperatingTemperatureRange T ≤T ≤T
MIN A MAX
−40°C≤T ≤+85°C
A
SupplyVoltage(V+=V +=V +) +4.5Vto+5.5V
A D
|V +−V +| ≤100mV
A D
V + 0VtoV +
REF A
V − 0Vto(V +−1V)
REF REF
V (V +−V −) 1VtoV +
REF REF REF A
V CommonModeVoltageRange
REF
[(V +)−(V −)]/2 0.1V +to0.6V +
REF REF A A
A/DIN1,A/DIN2,MUXOUT1andMUXOUT2VoltageRange 0VtoV +
A
INCommonModeVoltageRange
[(V +)−(V −)]/2 0VtoV +
IN IN A
(1) AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.OperatingRatingsindicateconditionsfor
whichthedeviceisfunctional,butdonotensurespecificperformancelimits.Forensuredspecificationsandtestconditions,seethe
ElectricalCharacteristics.Theensuredspecificationsapplyonlyforthetestconditionslisted.Someperformancecharacteristicsmay
degradewhenthedeviceisnotoperatedunderthelistedtestconditions.
(2) AllvoltagesaremeasuredwithrespecttoGND,unlessotherwisespecified.
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ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034
ADC12H038
ADC12030, ADC12032, ADC12034
ADC12038, ADC12H030, ADC12H032
ADC12H034, ADC12H038
SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com
Package Thermal Resistance
PartNumber ThermalResistance(θ )
JA
ADC12(H)030CIWM 70°C/W
ADC12032CIWM 64°C/W
ADC12034CIN 42°C/W
ADC12034CIWM 57°C/W
ADC12H034CIMSA 97°C/W
ADC12(H)038CIWM 50°C/W
NOTE:SomeofthesedevicesmaybeobsoleteoronLifetime Buystatus. Checkourwebsiteforproduct
availability.
Converter Electrical Characteristics
ThefollowingspecificationsapplyforV+=V +=V +=+5.0V ,V +=+4.096V ,V −=0V ,12-bit+sign
A D DC REF DC REF DC
conversionmode,f =f =8MHzfortheADC12H030,ADC12H032,ADC12H034andADC12H038,f =f =5MHzfor
CK SK CK SK
theADC12030,ADC12032,ADC12034andADC12038,R =25Ω,sourceimpedanceforV +andV −≤25Ω,fully-
S REF REF
differentialinputwithfixed2.048Vcommon-modevoltage,and10(t )acquisitiontimeunlessotherwisespecified.Boldface
CK
limitsapplyforT =T =T toT ;allotherlimitsT =T =25°C. (1)(2)(3)
A J MIN MAX A J
Parameter TestConditions Typical (4) Limits (5) Units
(Limits)
STATICCONVERTERCHARACTERISTICS
ResolutionwithNoMissingCodes 12+sign Bits(min)
ILE IntegralLinearityError AfterAutoCal (6)(7) ±1/2 ±1 LSB(max)
DNL DifferentialNon-Linearity AfterAutoCal ±1 LSB(max)
PositiveFull-ScaleError AfterAutoCal (6)(7) ±1/2 ±3.0 LSB(max)
NegativeFull-ScaleError AfterAutoCal (6)(7) ±1/2 ±3.0 LSB(max)
AfterAutoCal (8)(7)
OffsetError ±1/2 ±2 LSB(max)
V (+)=V (−)=2.048V
IN IN
DCCommonModeError AfterAutoCal (9) ±2 ±3.5 LSB(max)
(1) Twoon-chipdiodesaretiedtoeachanaloginputthroughaseriesresistorasshownbelow.Inputvoltagemagnitudeupto5VaboveV +
A
or5VbelowGNDwillnotdamagethisdevice.However,errorsintheconversioncanoccur(ifthesediodesareforwardbiasedbymore
than50mV)iftheinputvoltagemagnitudeofselectedorunselectedanaloginputgoaboveV +orbelowGNDbymorethan50mV.As
A
anexample,ifV +is4.5V ,full-scaleinputvoltagemustbe≤4.55V toensureaccurateconversions.
A DC DC
(2) Toensureaccuracy,itisrequiredthattheV +andV +beconnectedtogethertothesamepowersupplywithseparatebypass
A D
capacitorsateachV+pin.
(3) WiththetestconditionforV (V +−V −)givenas+4.096V,the12-bitLSBis1.0mVandthe8-bitLSBis16.0mV.
REF REF REF
(4) TypicalfiguresareatT =T =25°Candrepresentmostlikelyparametricnorm.
J A
(5) TestedlimitsarespecifiedtoAOQL(AverageOutgoingQualityLevel).
(6) PositiveintegrallinearityErrorisdefinedasthedeviationoftheanalogvalue,expressedinLSBs,fromthestraightlinethatpasses
throughpositivefull-scaleandzero.ForNegativeIntegralLinearityError,thestraightlinepassesthroughnegativefull-scaleandzero
(seeFigure6andFigure7).
(7) TheADC12030family'sself-calibrationtechniqueensureslinearityandoffseterrorsasspecified,butnoiseinherentintheself-
calibrationprocesswillresultinamaximumrepeatabilityuncertaintyof0.2LSB.
(8) Thehumanbodymodelisa100pFcapacitordischargedthrougha1.5kΩresistorintoeachpin.
(9) TheDCcommon-modeerrorismeasuredinthedifferentialmultiplexermodewiththeassignedpositiveandnegativeinputchannels
shortedtogether.
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ADC12038, ADC12H030, ADC12H032
ADC12H034, ADC12H038
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Converter Electrical Characteristics (continued)
ThefollowingspecificationsapplyforV+=V +=V +=+5.0V ,V +=+4.096V ,V −=0V ,12-bit+sign
A D DC REF DC REF DC
conversionmode,f =f =8MHzfortheADC12H030,ADC12H032,ADC12H034andADC12H038,f =f =5MHzfor
CK SK CK SK
theADC12030,ADC12032,ADC12034andADC12038,R =25Ω,sourceimpedanceforV +andV −≤25Ω,fully-
S REF REF
differentialinputwithfixed2.048Vcommon-modevoltage,and10(t )acquisitiontimeunlessotherwisespecified.Boldface
CK
limitsapplyforT =T =T toT ;allotherlimitsT =T =25°C.(1)(2)(3)
A J MIN MAX A J
Parameter TestConditions Typical (4) Limits (5) Units
(Limits)
TUE TotalUnadjustedError AfterAutoCal (6)(10)(11) ±1 LSB
ResolutionwithNoMissingCodes 8-bit+signmode 8+sign Bits(min)
INL IntegralLinearityError 8-bit+signmode (6) ±1/2 LSB(max)
DNL DifferentialNon-Linearity 8-bit+signmode ±3/4 LSB(max)
PositiveFull-ScaleError 8-bit+signmode (6) ±1/2 LSB(max)
NegativeFull-ScaleError 8-bit+signmode (6) ±1/2 LSB(max)
8-bit+signmode,afterAutoZero
OffsetError V (+)=V (−)=+2.048V (10) ±1/2 LSB(max)
IN IN
8-bit+signmodeafterAutoZero
TUE TotalUnadjustedError (6)(10)(11) ±3/4 LSB(max)
MultiplexerChan-to-ChanMatching ±0.05 LSB
PowerSupplySensitivity V+=+5V±10%,V =+4.096V
REF
OffsetError ±0.5 ±1 LSB(max)
+Full-ScaleError ±0.5 ±1.5 LSB(max)
−Full-ScaleError ±0.5 ±1.5 LSB(max)
IntegralLinearityError ±0.5 LSB
OutputDatafrom“12-Bit (seeTable5) (12) +10 LSB(max)
ConversionofOffset” −10 LSB(min)
OutputDatafrom“12-Bit (seeTable5) (12) 4095 LSB(max)
ConversionofFull-Scale” 4093 LSB(min)
UNIPOLARDYNAMICCONVERTERCHARACTERISTICS
f =1kHz,V =5V ,V +=5.0V 69.4 dB
IN IN P-P REF
S/(N+D) Signal-to-NoisePlusDistortionRatio f =20kHz,V =5V ,V +=5.0V 68.3 dB
IN IN P-P REF
f =40kHz,V =5V ,V +=5.0V 65.7 dB
IN IN P-P REF
−3dBFullPowerBandwidth V =5V ,whereS/(N+D)drops3dB 31 kHz
IN P-P
DIFFERENTIALDYNAMICCONVERTERCHARACTERISTICS
f =1kHz,V =±5V,V +=5.0V 77.0 dB
IN IN REF
S/(N+D) Signal-to-NoisePlusDistortionRatio f =20kHz,V =±5V,V +=5.0V 73.9 dB
IN IN REF
f =40kHz,V =±5V,V +=5.0V 67.0 dB
IN IN REF
−3dBFullPowerBandwidth V =±5V,whereS/(N+D)drops3dB 40 kHz
IN
REFERENCEINPUT,ANALOGINPUTSANDMULTIPLEXERCHARACTERISTICS
C ReferenceInputCapacitance 85 pF
REF
A/DIN1,A/DIN2AnalogInput
C 75 pF
A/D Capacitance
A/DIN1,A/DIN2AnalogInput
V =+5.0VorV =0V ±0.1 ±1.0 µA(max)
LeakageCurrent IN IN
GND−0.05 V(min)
CH0–CH7andCOMInputVoltage
(V +)+0.05 V(max)
A
CH0–CH7andCOMInput
C 10 pF
CH Capacitance
C MUXOutputCapacitance 20 pF
MUXOUT
(10) Offseterrorisameasureofthedeviationfromthemid-scalevoltage(acodeofzero),expressedinLSB.Itistheworst-casevalueofthe
codetransitionsbetween1to0and0to+1(seeFigure8).
(11) Totalunadjustederrorincludesoffset,full-scale,linearityandmultiplexererrors.
(12) The“12-BitConversionofOffset”and“12-BitConversionofFull-Scale”modesareintendedtotestthefunctionalityofthedevice.
Therefore,theoutputdatafromthesemodesarenotanindicationoftheaccuracyofaconversionresult.
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ADC12038, ADC12H030, ADC12H032
ADC12H034, ADC12H038
SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com
Converter Electrical Characteristics (continued)
ThefollowingspecificationsapplyforV+=V +=V +=+5.0V ,V +=+4.096V ,V −=0V ,12-bit+sign
A D DC REF DC REF DC
conversionmode,f =f =8MHzfortheADC12H030,ADC12H032,ADC12H034andADC12H038,f =f =5MHzfor
CK SK CK SK
theADC12030,ADC12032,ADC12034andADC12038,R =25Ω,sourceimpedanceforV +andV −≤25Ω,fully-
S REF REF
differentialinputwithfixed2.048Vcommon-modevoltage,and10(t )acquisitiontimeunlessotherwisespecified.Boldface
CK
limitsapplyforT =T =T toT ;allotherlimitsT =T =25°C.(1)(2)(3)
A J MIN MAX A J
Parameter TestConditions Typical (4) Limits (5) Units
(Limits)
OffChannelLeakageCH0–CH7 OnChannel=5VandOffChannel=0V −0.01 −0.3 µA(min)
andCOMPins (13) OnChannel=0VandOffChannel=5V 0.01 0.3 µA(max)
OnChannelLeakageCH0–CH7 OnChannel=5VandOffChannel=0V 0.01 0.3 µA(max)
andCOMPins (13) OnChannel=0VandOffChannel=5V −0.01 −0.3 µA(min)
MUXOUT1andMUXOUT2Leakage
V =5.0VorV =0V 0.01 0.3 µA(max)
Current MUXOUT MUXOUT
R MUXOnResistance V =2.5VandV =2.4V 850 1150 Ω(max)
ON IN MUXOUT
R MatchingChan-to-Chan V =2.5VandV =2.4V 5 %
ON IN MUXOUT
Chan-to-ChanCrosstalk V =5V ,f =40kHz −72 dB
IN P-P IN
MUXBandwidth 90 kHz
(13) Channelleakagecurrentismeasuredafterthechannelselection.
DC and Logic Electrical Characteristics
ThefollowingspecificationsapplyforV+=V +=V +=+5.0V ,V +=+4.096V ,V −=0V ,12-bit+sign
A D DC REF DC REF DC
conversionmode,f =f =8MHzfortheADC12H030,ADC12H032,ADC12H034andADC12H038,f =f =5MHzfor
CK SK CK SK
theADC12030,ADC12032,ADC12034andADC12038,R =25Ω,sourceimpedanceforV +andV −≤25Ω,fully-
S REF REF
differentialinputwithfixed2.048Vcommon-modevoltage,and10(t )acquisitiontimeunlessotherwisespecified.Boldface
CK
limitsapplyforT =T =T toT ;allotherlimitsT =T =25°C. (1)(2)(3)
A J MIN MAX A J
Parameter TestConditions Typical (4) Limits (5) Units
(Limits)
CCLK,CS,CONV,DI,PDANDSCLKINPUTCHARACTERISTICS
V Logical“1”InputVoltage V+=5.5V 2.0 V(min)
IN(1)
V Logical“0”InputVoltage V+=4.5V 0.8 V(max)
IN(0)
I Logical“1”InputCurrent V =5.0V 0.005 1.0 µA(max)
IN(1) IN
I Logical“0”InputCurrent V =0V −0.005 −1.0 µA(min)
IN(0) IN
DO,EOCANDDORDIGITALOUTPUTCHARACTERISTICS
V+=4.5V,I =−360µA 2.4 V(min)
OUT
V Logical“1”OutputVoltage
OUT(1) V+=4.5V,I =−10µA 4.25 V(min)
OUT
(1) Twoon-chipdiodesaretiedtoeachanaloginputthroughaseriesresistorasshownbelow.Inputvoltagemagnitudeupto5VaboveV +
A
or5VbelowGNDwillnotdamagethisdevice.However,errorsintheconversioncanoccur(ifthesediodesareforwardbiasedbymore
than50mV)iftheinputvoltagemagnitudeofselectedorunselectedanaloginputgoaboveV +orbelowGNDbymorethan50mV.As
A
anexample,ifV +is4.5V ,full-scaleinputvoltagemustbe≤4.55V toensureaccurateconversions.
A DC DC
(2) Toensureaccuracy,itisrequiredthattheV +andV +beconnectedtogethertothesamepowersupplywithseparatebypass
A D
capacitorsateachV+pin.
(3) WiththetestconditionforV (V +−V −)givenas+4.096V,the12-bitLSBis1.0mVandthe8-bitLSBis16.0mV.
REF REF REF
(4) TypicalfiguresareatT =T =25°Candrepresentmostlikelyparametricnorm.
J A
(5) TestedlimitsarespecifiedtoAOQL(AverageOutgoingQualityLevel).
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ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034
ADC12H038
ADC12030, ADC12032, ADC12034
ADC12038, ADC12H030, ADC12H032
ADC12H034, ADC12H038
www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013
DC and Logic Electrical Characteristics (continued)
ThefollowingspecificationsapplyforV+=V +=V +=+5.0V ,V +=+4.096V ,V −=0V ,12-bit+sign
A D DC REF DC REF DC
conversionmode,f =f =8MHzfortheADC12H030,ADC12H032,ADC12H034andADC12H038,f =f =5MHzfor
CK SK CK SK
theADC12030,ADC12032,ADC12034andADC12038,R =25Ω,sourceimpedanceforV +andV −≤25Ω,fully-
S REF REF
differentialinputwithfixed2.048Vcommon-modevoltage,and10(t )acquisitiontimeunlessotherwisespecified.Boldface
CK
limitsapplyforT =T =T toT ;allotherlimitsT =T =25°C.(1)(2)(3)
A J MIN MAX A J
Parameter TestConditions Typical (4) Limits (5) Units
(Limits)
V Logical“0”OutputVoltage V+=4.5V,I =1.6mA 0.4 V(max)
OUT(0) OUT
V =0V −0.1 −3.0 µA(max)
OUT
I TRI-STATEOutputCurrent
OUT
V =5V 0.1 3.0 µA(max)
OUT
+I OutputShortCircuitSourceCurrent V =0V 14 6.5 mA(min)
SC OUT
−I OutputShortCircuitSinkCurrent V =V + 16 8.0 mA(min)
SC OUT D
POWERSUPPLYCHARACTERISTICS
DigitalSupplyCurrent Awake 1.6 2.5 mA(max)
ADC12030,ADC12032,ADC12034and CS=HIGH,PoweredDown,CCLKon 600 µA
ADC12038 CS=HIGH,PoweredDown,CCLKoff 20 µA
I +
D
DigitalSupplyCurrent Awake 2.3 3.2 mA
ADC12H030,ADC12H032,ADC12H034 CS=HIGH,PoweredDown,CCLKon 0.9 mA
andADC12H038 CS=HIGH,PoweredDown,CCLKoff 20 µA
Awake 2.7 4.0 mA(max)
I + PositiveAnalogSupplyCurrent CS=HIGH,PoweredDown,CCLKon 10 µA
A
CS=HIGH,PoweredDown,CCLKoff 0.1 µA
Awake 70 µA
I ReferenceInputCurrent
REF CS=HIGH,PoweredDown 0.1 µA
AC Electrical Characteristics
ThefollowingspecificationsapplyforV+=V +=V +=+5.0V ,V +=+4.096V ,V −=0V ,12-bit+sign
A D DC REF DC REF DC
conversionmode,t =t =3ns,f =f =8MHzfortheADC12H030,ADC12H032,ADC12H034andADC12H038,f =f
r f CK SK CK SK
=5MHzfortheADC12030,ADC12032,ADC12034andADC12038,R =25Ω,sourceimpedanceforV +andV −≤
S REF REF
25Ω,fully-differentialinputwithfixed2.048Vcommon-modevoltage,and10(t )acquisitiontimeunlessotherwisespecified.
CK
BoldfacelimitsapplyforT =T =T toT ;allotherlimitsT =T =25°C. (1)
A J MIN MAX A J
Typical ADC12H030/2/4/8 ADC12030/2/4/8 Units
Parameter TestConditions (2) Limits (3) Limits (3) (Limits)
f ConversionClock(CCLK) 10 8 5 MHz(max)
CK
Frequency 1 MHz(min)
SerialDataClockSCLKFrequency 10 8 5 MHz(max)
f
SK 0 Hz(min)
40 40 %(min)
ConversionClockDutyCycle
60 60 %(max)
40 40 %(min)
SerialDataClockDutyCycle
60 60 %(max)
12-Bit+Signor12- 44(t ) 44(t ) (max)
44(t ) CK CK
Bit CK 5.5 8.8 µs(max)
t ConversionTime
C
21(t ) 21(t ) (max)
8-Bit+Signor8-Bit 21(t ) CK CK
CK 2.625 4.2 µs(max)
(1) TimingspecificationsaretestedattheTTLlogiclevels,V =0.4VforafallingedgeandV =2.4Vforarisingedge.TRI-STATEoutput
IL IH
voltageisforcedto1.4V.
(2) TypicalfiguresareatT =T =25°Candrepresentmostlikelyparametricnorm.
J A
(3) TestedlimitsarespecifiedtoAOQL(AverageOutgoingQualityLevel).
Copyright©1999–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9
ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034
ADC12H038
ADC12030, ADC12032, ADC12034
ADC12038, ADC12H030, ADC12H032
ADC12H034, ADC12H038
SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com
AC Electrical Characteristics (continued)
ThefollowingspecificationsapplyforV+=V +=V +=+5.0V ,V +=+4.096V ,V −=0V ,12-bit+sign
A D DC REF DC REF DC
conversionmode,t =t =3ns,f =f =8MHzfortheADC12H030,ADC12H032,ADC12H034andADC12H038,f =f
r f CK SK CK SK
=5MHzfortheADC12030,ADC12032,ADC12034andADC12038,R =25Ω,sourceimpedanceforV +andV −≤
S REF REF
25Ω,fully-differentialinputwithfixed2.048Vcommon-modevoltage,and10(t )acquisitiontimeunlessotherwisespecified.
CK
BoldfacelimitsapplyforT =T =T toT ;allotherlimitsT =T =25°C.(1)
A J MIN MAX A J
Typical ADC12H030/2/4/8 ADC12030/2/4/8 Units
Parameter TestConditions (2) Limits (3) Limits (3) (Limits)
6(t ) 6(t ) (min)
CK CK
6(t )
CK
6Cycles 7(tCK) 7(tCK) (max)
Programmed 0.75 1.2 µs(min)
0.875 1.4 µs(max)
10(t ) 10(t ) (min)
CK CK
10(t )
CK
10Cycles 11(tCK) 11(tCK) (max)
Programmed 1.25 2.0 µs(min)
1.375 2.2 µs(max)
t AcquisitionTime (4)
A
18(t ) 18(t ) (min)
CK CK
18(t )
CK
18Cycles 19(tCK) 19(tCK) (max)
Programmed 2.25 3.6 µs(min)
2.375 3.8 µs(max)
34(t ) 34(t ) (min)
CK CK
34(t )
CK
34Cycles 35(tCK) 35(tCK) (max)
Programmed 4.25 6.8 µs(min)
4.375 7.0 µs(max)
4944(t ) 4944(t ) 4944(t ) (max)
CK CK CK
t Self-CalibrationTime
CKAL
618.0 988.8 µs(max)
76(t ) 76(t ) 76(t ) (max)
CK CK CK
t AutoZeroTime
AZ
9.5 15.2 µs(max)
2(t ) 2(t ) 2(t ) (min)
CK CK CK
Self-CalibrationorAutoZero 3(tCK) 3(tCK) (max)
t
SYNC SynchronizationTimefromDOR 0.250 0.40 µs(min)
0.375 0.60 µs(max)
DORHighTimewhenCSisLow
t ContinuouslyforReadDataand 9(t ) 9(t ) 9(t ) (max)
DOR SK SK SK
SoftwarePowerUp/Down 1.125 1.8 µs(max)
8(t ) 8(t ) 8(t ) (max)
SK SK SK
t CONVValidDataTime
CONV
1.0 1.6 µs(max)
(4) IfSCLKandCCLKaredrivenfromthesameclocksource,thent is6,10,18or34clockperiodsminimumandmaximum.
A
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