Scanning Probe Lithography

211 Pages·2001·8.237 MB·English

by  Hyongsok T. Soh, Kathryn Wilder Guarini, Calvin F. Quate (auth.)

SCANNING PROBE LITHOGRAPHY
MICROSYSTEMS
Series Editor
Stephen D. Senturia
Massachusetts Institute of Technology
Editorial Board
Roger T. Howe, University o/California, Berkeley
D. Jed Harrison, University ofA lberta
Hiroyuki Fujita, University of Tokyo
Jan-Ake Schweitz, Uppsala University
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SCANNING PROBE LITHOGRAPHY
by
Hyongsok T. Soh
Kathryn Wilder Guarini
Calvin F. Quate
Stanford University, Stanford, California
SPRINGER SCIENCE+BUSINESS MEDIA, LLC
Library of Congress Cataloging-in-Publication Data
Soh, Hyongsok T.
Scanning Probe Lithography 1 by Hyongsok T. Soh, Kathryn Wilder Guarini, Calvin F.
Quate
p. cm. (Microsystems series)
Includes bibliographical references and index.
ISBN 978-1-4419-4894-6 ISBN 978-1-4757-3331-0 (eBook)
DOI 10.1007/978-1-4757-3331-0
1. Integrated circuits-Design and Construction. 2. Microlithography. 3. Scanning
probe microscopy
TK7874 .S648 2001
621.3815/3121
01-029782
Copyright © 2001 by Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers in 2001
Softcover reprint of the hardcover 1st edition 2001
All rights reserved. No part of this publication may be reproduced, stored in a retrieval
system or transmitted in any form or by any means, mechanical, photo-copying, recording,
or otherwise, without the prior written permission of the publisher,
Springer Science+Business Media, LLC
Printed on acid-free paper.
Table of Contents
Table of Contents
List of Figures ..................................................................................................... ix
List of Tables ...................................................................................................... xv
Glossary ............................................................................................................ xvii
Foreword ............................................................................................................ xix
Preface ............................................................................................................... xxi
Acknowledgments .......................................................................................... xxiii
Chapter 1: Introduction to Scanning Probe Lithography 1
1.1 The Scanning Probe Microscope .............................. 1
1.1.1 The Scanning Tunneling Microscope ........................ 2
1.1.2 The Atomic Force Microscope ............................. 3
1.1.3 Innovations Through Integration ........................... .4
1.2 High-Resolution Patterning Using Scanning Probes ............... 6
1.2.2 Mechanical & Thermomechanical Patterning .................. 7
1.2.3 Local Oxidation ......................................... 8
1.2.4 Electron Exposure of Resist ............................... 9
1.3 Semiconductor Lithography .................................. 9
1.4 Book Overview ........................................... 15
1.5 References ............................................... 16
Chapter 2: SPL by Electric-Field-Enhanced Oxidation 23
2.1 Field-Enhanced Oxidation of Silicon .......................... 23
2.2 Amorphous Silicon as a Resist Material. ....................... 24
2.3 Fabrication ofa 100 nm nMOSFET ........................... 26
2.4 Results and Discussion ..................................... 32
2.5 References ............................................... 34
Chapter 3: Resist Exposure Using Field-Emitted Electrons 37
3.1 Field-Emitted Electron Exposure ............................. 37
3.2 Current-Controlled Exposures in Contact Mode ................ .48
3.3 Current-Controlled Exposures in Noncontact Mode .............. 60
3.3.2 Patterning in the Noncontact Mode ......................... 62
3.3.3 Line Width Control ............................ ; ........ 65
3.3.4 Comparison of Contact and Noncontact Mode Results ......... 66
3.3.5 Summary of Noncontact Mode SPL ........................ 67
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Scanning Probe Lithography
3.4 Simulations of Electron Field Emission and Electron Trajectories ... 67
3.4.1 Initial Beam Size in the Contact Configuration ............... 68
3.4.2 Comparison of Contact and Noncontact Configurations ........ 71
3.4.3 Beam Spreading ....................................... 75
3.4.4 Summary of Simulation Results ........................... 75
3.5 References ............................................... 77
Chapter 4: SPL Linewidth Control 81
4.1 Exposure Tools and Samples ................................ 81
4.2 Sensitivity and Exposure Latitude ............................ 84
4.3 Energy Density Distribution in the Resist ...................... 85
4.4 Patterning Linearity Using a Pixel Writing Scheme ............... 88
4.5 Proximity Effects ......................................... 91
4.6 Exposure Mechanisms of High-and Low-Energy Electrons ........ 97
4.7 Summary ................................................ 99
4.8 References ............................................... 99
Chapter 5: Critical Dimension Patterning Using SPL 103
5.1 100 nm pMOSFET Device Fabrication ....................... 103
5.2 Gate Level Lithography Using SPL .......................... 105
5.2.1 Overlay Registration ................................... 106
5.2.2 Patterning Over Topography ............................. 106
5.3 PMOSFET Device Characteristics ........................... 110
5.4 Summary of "Mix and Match" Lithography .................... 112
5.5 References .............................................. 112
Chapter 6: High Speed Resist Exposure With a Single Tip 115
6.1 High Speed Patterning of Siloxane SOG ...................... 115
6.1.1 Mechanism of Exposure ................................ 115
6.1.2 Experimental Procedure ................................ 117
6.1.3 Results of SOG Patterning .............................. 118
6.1.4 Discussion ........................................... 119
6.2 Current-Controlled SPL at High Speeds ....................... 119
6.2.1 Control of the Tip-Sample Force or Spacing at High Speeds .... 120
6.2.2 Control of the Emission Current at High Speeds ............. 121
6.2.3 High Speed Lithography ................................ 125
6.2.4 Summary of High Speed SPL Using a Single Tip ............ 126
6.3 References .............................................. 129
vi
Table of Contents
Chapter 7: On-Chip Lithography Control 131
7.1 Background and Motivation ................................ 131
7.2 MOSFET Design Considerations ............................ 132
7.2.1 Saturation Current. .................................... 134
7.2.2 Threshold Voltage ..................................... 134
7.2.3 Junction Breakdown ................................... 135
7.2.4 Off Current .......................................... 136
7.2.5 Switching Speed ...................................... 137
7.3 Cantilever and Tip Design Parameters ........................ 138
7.4 Fabrication Process ....................................... 140
7.4.1 Tip Formation and Cantilever Definition ................... 142
7.4.2 Front-End Transistor Fabrication ......................... 143
7.4.3 Back-End Transistor Fabrication ......................... 144
7.4.4 Cantilever Release ..................................... 144
7.5 Device Characteristics .................................... 146
7.6 Lithography with Integrated Transistor for Exposure Dose Control .148
7.7 Summary ............................................... 150
7.8 References .............................................. 151
Chapter 8: Scanning Probe Tips for SPL 153
8.1 Silicon and Metal-Coated Tips .............................. 153
8.2 Post-Processed Silicon Tips ................................ 155
8.3 Carbon Nanotubes as Scanning Probe Tips .................... 156
8.3.1 Direct Synthesis on Silicon Pyramidal Tips ................. 157
8.4 References .............................................. 160
Chapter 9: Scanning Probe Arrays for Lithography 163
9.1 Current-Controlled Lithography With Two Tips ................ 163
9 .1.1 High-Voltage Current Preamplifier. ....................... 164
9.1.2 Independent Parallel Lithography ......................... 166
9.1.3 Summary of Progress on Parallel Lithography ............... 167
9.2 Massively Parallel Arrays for Lithography .................... 167
9.2.1 Exposure Time for Different Size Arrays ................... 168
9.2.2 SPL Throughput Using Cantilever Arrays .................. 170
9.3 Integrated Current Control for Arrays ........................ 172
9.4 Two Dimensional Arrays: Process Development ................ 173
9.4.1 Enabling Technologies ................................. 173
9.4.2 Anisotropic Through Wafer Etching ....................... 174
9.4.3 Through-Wafer Via Process ............................. 175
9.5 Two Dimensional Arrays: Integration ........................ 178
vii
Scanning Probe Lithography
9.5.1 Introduction to the Piezoresistive Cantilever ................ 178
9.5.2 Design and Modeling .................................. 178
9.5.3 Processing ........................................... 181
9.6 Imaging With the 2D Array ................................ 187
9.7 References .............................................. 188
Epilog 191
List of Publications 193
Index 197
viii
List of Figures
List of Figures
Figure 1.1: Schematic diagram of the most common configurations of the
scanning probe microscope (SPM) .......................................................... 2
Figure 1.2: Schematic diagrams of surface modification using a scanning probe ..... 7
Figure 2.1: Schematic diagram of SPL by electric-field-enhanced oxidation
of silicon ................................................................................................ 23
Figure 2.2: Schematic of SPL by electric field enhanced oxidation using
amorphous silicon as a resist material. .................................................. 25
Figure 2.3: SEM image ofa:Si patterned by SPL with the electric-field-
enhanced oxidation ................................................................................ 25
Figure 2.4: Schematic of the process flow for the 100 nm nMOSFET .................... 27
Figure 2.5: Schematic ofnMOSFET gate patterning step by SPL. ......................... 29
Figure 2.6: SEM micrographs of the patterned amorphous silicon gate .................. 30
Figure 2.7: Optical micrograph of the completed nMOSFET .................................. 30
Figure 2.8: Electrical characteristics of the nMOSFET ........................................... 31
Figure 3.1: (a) Schematic diagram of a cantilever with integrated tip used
for electron emission and resist exposure. (b) Electric field
distribution near a biased probe tip ........................................................ 39
Figure 3.2: Potential energy diagram for electrons at a metal surface in the
presence of an applied field. . ............................................................... .40
Figure 3.3: Depiction of two different scanning strategies for direct write
lithography. (a) Raster scanning. (b) Vector scanning. ........................ .44
Figure 3.4: Schematic diagrams of SPL resist exposure, development, and
pattern transfer. ..................................................................................... 45
Figure 3.5: Transfer ofPMMA patterns through chrome evaporation and
lift-off. .................................................................................................... 46
Figure 3.6: Schematic diagrams of resist exposure using electrons field
emitted from a scanning probe in the (a) STM configuration and
(b) AFM configuration ........................................................................... 48
Figure 3.7: Schematic diagram of the hybrid AFMlSTM lithography system ...... .49
ix
Scanning Probe Lithography
Figure 3.8: Diagram of the integral feedback circuit used for emission
current control. ....................................................................................... 50
Figure 3.9: Emission current as a function of the tip-sample voltage bias for
SAL60 I resist thicknesses of 35 nm and 65 nm ................................... 51
Figure 3.11: AFM micrographs of latent images in resist immediately after
SPL exposure ........................................................................................ 54
Figure 3.12: SEM micrographs of 500-nm-pitch line gratings patterned by SPL. .... 55
Figure 3.13: SPL patterned line width dependence on exposure line dose
for hybrid AFM/STM patterning of 65-nm-thick SAL60 I resist
and 50-nm-thick PMMA resist on doped silicon substrates .................. 56
Figure 3.14: Optical micrographs oflithographed lines before and after
pattern transfer. ...................................................................................... 57
Figure 3.15: Cross-sectional SEM images of etched silicon features patterned
by SPL. ................................................................................................... 58
Figure 3.16: The words "MASKLESS LITHOGRAPHY" were written by
SPL in PMMA positive resist using the vector scanning strategy ........ 59
Figure 3.17: Schematic diagram of the system used for noncontact SPL. ................. 61
Figure 3.18: Relative tip height as a function of sample bias necessary to
maintain an emission current of 50 pA while the tip was scanned
over the resist surface at 10 11m/so ......................................................... 62
Figure 3.19: AFM image of developed SAL60 I resist lines patterned by
noncontact SPL. .................................................................................... 63
Figure 3.20: SEM micrographs oflines written using the noncontact SPL mode
and etched into the underlying silicon substrate .................................... 64
Figure 3.21: Linewidth control using the noncontact SPL mode to expose
SAL60 I resist. ....................................................................................... 65
Figure 3.22: Comparison of non contact mode and contact mode SPL data .............. 66
Figure 3.23: Potential contours and electric field vectors between the tip
and sample ............................................................................................. 69
Figure 3.24: Simulation results for a tip I nm above the surface of a
65-nm-thick resist film ........................................................................... 70
Figure 3.25: Normalized electric field distribution at the tip surface for
different resist thicknesses (R) and spacings (D) between the
tip apex and resist surface ...................................................................... 72
x