Scalable Hardware Verification with Symbolic Simulation

192 Pages·2006·3.843 MB·English

by  Valeria Bertacco (auth.)

SCALABLE HARDWARE VERIFICATION
WITH SYMBOLIC SIMULATION
SCALABLEHARDWAREVERIFICATION
WITH SYMBOLIC SIMULATION
VALERIABERTACCO
UniversityofMichigan
KluwerAcademicPublishers
Boston/Dordrecht/London
Valeria Bertacco
The University of Michigan
Advanced Computer Architecture Lab
Department of EE & CS
13 0 1 Beal Avenue, Room 2224
Ann Arbor, MI 48109
U.S.A.
Scalable Hardware Verification with Symbolic Simulation
Cover design by S. Alexander Garcia
Library of Congress Control Number: 20055934803
ISBN-I 0: 0-387-2441 1-5 ISBN-1 0: 0-387-29906-8 (e-book)
ISBN-1 3: 97803872441 12 ISBN-13: 9780387299068 (e-book)
Printed on acid-free paper.
O 2006 Springer Science+Business Media, Inc.
All rights reserved. This work may not be translated or copied in whole or in part without
the written permission of the publisher (Springer Science+Business Media, hc., 233 Spring
Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or
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even if they are not identified as such, is not to be taken as an expression of opinion as to
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Printed in the United States of America.
SPIN 11 325031
To Roberta, Bruno,
Livio and Todo.
Contents
Dedication v
List of Figures xi
...
List of Tables Xlll
Preface xv
Acknowledgments xix
1. INTRODUCTION
1.1 Functional validation
1.2 Formal verification
1.2.1 Symbolic simulation
1.3 Organization of the book
2. DESIGN AND VERIFICATION OF DIGITAL SYSTEMS
2.1 The design flow
2.2 RTL verification
2.3 Boolean functions and their representation
2.3.1 NP-equivalence
2.4 Binary decision diagrams
2.5 Models for design verification
2.5.1 Structural network model
2.5.2 State diagrams
2.5.3 Mathematical model of finite state machines
2.6 Functional validation
2.7 Formal verification
2.7.1 Symbolic finite state machine traversal
2.8 Summary
References
3. SYMBOLIC SIMULATION
3.1 The origins of symbolic simulation
3.2 Symbolic simulation of a logic gate
3.3 Symbolic simulation, time frame-by-time frame
3.3.1 Symbolic simulation to expose design flaws
3.4 Close relatives of symbolic simulation
.. .
vlll SCALABLE VERIFICATION WITH SYMBOLIC SIMULATION
3.4.1 Symbolic reachability analysis
3.4.2 Symbolic trajectory evaluation
3.5 Enhancements and optimizations
3.6 The challenge in symbolic simulation
3.7 Summary
References
4. COMPACTING INTERMEDIATE STATES
4.1 Parametric transformations
4.1.1 A formal definition
4.1.2 Applications to symbolic simulation
4.1.3 A brief history of parametric solutions
4.2 Disjoint-support decompositions
4.2.1 A canonical form of DSDs
4.2.2 Decomposition trees
4.3 A BDD-based algorithm to extract DSDs
4.3.1 Building decompositions bottom-up
4.3.2 Putting it all together: The DEC procedure
4.3.3 Complexity analysis and considerations
4.3.4 Decomposability experiments
4.4 On the decomposability of Boolean functions
4.5 Evolution of disjoint-support decompositions
4.6 Summary
References
5. APPROXIMATE SIMULATION
5.1 Cycle-based symbolic simulation flow
5.2 The CBSS algorithm
5.3 The reparametrization phase
5.3.1 Using functional dependencies
5.3.2 How to classify the components of the state vector
5.3.3 The remap function
5.4 Implementation and insights
5.4.1 Experimental results
5.5 Quasi-Symbolic Simulation
5.5.1 Simulation with X values
5.5.2 Approximating and reclassifying symbolic variables
5.5.3 Care and Don't care sets
5.6 Summary
References
Contents ix
6. EXACT PARAMETRIZATIONS
6.1 Re-encoding the state function using DSDs
6.1.1 Reduction at free points
6.1.2 Elimination of prime functions
6.1.3 Removal of non-dominant variables
6.2 The DSD-based simulator
6.2.1 Experimental results
6.3 Parametrization in the micro-processor domain
6.3.1 Structural decompositions
6.3.2 Parametrization for data-space partitions
6.4 Summary
References
7. CONCLUSION 127
7.1 Enabling techniques for symbolic simulation 128
7.2 Scalable symbolic simulation techniques 128
References 129
Appendices
A Disjoint-Support Decompositions
A.l Function decompositions
A.2 The unique maximal Disjoint-Support Decomposition
A.2.1 Partitions and representative elements
A.2.2 Uniqueness of the kernel function
A.2.3 Uniqueness of the actuals list
A.3 The canonical decomposition tree
A.3.1 Extracting all decompositions from the canonical tree
A.4 Building the decomposition tree from a BDD
A11
A.4.1 Case 1. Neither Alo nor A1 is constant and Alo #
A.4.1.1 Case 1. a - PRIME decomposition
A.4.1.2 Case 1. b - Associative decomposition
A.4.2 Case 2. Exactly one of Ale, All is constant
A.4.2.1 Case 2.a - PRIME decomposition
A.4.2.2 Case 2.b - Associative decomposition
=All
A.4.3 Case 3. A10 and Ale is not a constant
A.4.3.1 Case 3.a - PRIME decomposition
A.4.3.2 Case 3.b - Associative decomposition
A.4.4 New decompositions
A.4.4.1 Case NEW.a - AND or OR decomposition
A.4.4.2 Case NEW.b - XOR decomposition
A.4.4.3 Case NEW.c - PRIME decomposition
A.5 The DEC procedure
A.5.1 Inherited decompositions
A.5.1.1 OR decompositions
SCALABLE VERIFICATION WITH SYMBOLIC SIMULATION
A.5.1.2 XOR decompositions
A.5.1.3 PRIME decompositions
A.5.2 New decompositions
A.5.2.1 OR and XOR decompositions
A.5.2.2 PRIME decompositions
References
References
Index
List of Figures
Conceptual design flow of a digital system 8
Approaches to verification: Validation vs. Formal Verification 13
Examples of Binary Decision Diagrams 18
Graphic symbols for basic logic gates 20
Structural network model schematic 2 1
Network model of a 3-bits upldown counter with reset 21
State diagram for a 3-bits upldown counter 22
State diagram for a 1-hot encoded 3-bits counter 23
Compiled logic simulator 25
Pseudo-code for a cycle-based logic simulator 26
Comparison of logic and symbolic simulation 36
Simulation of a netlist by composition of symbolic expressions 37
Schematic of the iterative model of symbolic simulation 3 8
Symbolic simulation for Example 3.1 - Initialization phase 39
Symbolic simulation for Example 3.1 - Simulation Step 2 40
Pseudo-code for frame-by-frame symbolic simulation 41
Pseudo-code for symbolic reachability analysis 43
Parametrization of the state vector during symbolic simulation 53
Parametrization of the state vector during symbolic simulation 54
Three steps of symbolic simulation for the counter of
Example 2.2 and possible parametrizations of the reached
state sets
General form of a disjoint-support decomposition (DSD)
Three different disjoint-support decompositions for Ex-
ample 4.3
A decomposition tree for Example 4.4
Decomposition data structure for the function of Ex-
ample 4.5
Pseudo-code for the decomposenode procedure
Pseudo-code for the decompose procedure
Pseudo-code for decompose-INHERITED
Pseudo-code for decompos eNEW
Flow of cycle-based symbolic simulation algorithm
SCALABLE VERIFICATION WITH SYMBOLIC SIMULATION
Pseudo-code for cycle-based symbolic simulation
The parametrized frontier subset PS@k
Pseudo-code for the Parametrize function of CBSS
Pseudo-code for classifying simple and complex sup-
port variables
Pseudo-code for classyfing shared support variables
Comparison of CBSS vs. logic simulation
Definition of logic operations over the ternary set {0,1, X}
+
MTBDD for the function (a X)b
Quasi-symbolic simulation for Example 5.7
The decomposed state vector for a small design
The parameterized frontier set PS@k
A vector function and its free points
Free points elimination for Example 6.1
General case for prime function elimination: (a) before
and (b) after the transformation
Prime elimination in test s1196 for Example 6.2
Non-dominant variable removal for Example 6.4
Comparison of DSD simulation vs. cycle-based sym-
bolic simulation and vs. logic simulation
Design decomposition for Example 6.5
Decomposition tree for Example A.5.
PRIME decomposition.
Function for Example A. 11.
Pseudo-code for decompose~INHERITED~OR~3 1.b 2
Pseudo-code for decompose-INHERITED-PRIME-1a.
.
Pseudo-code for decompose-INHERITED-PRIME-2a
Two functions and the construction of their Max(G,H ) tree.