(SAR) ADC - CMOSedu.com

67 Pages·2008·1.22 MB·English

Understanding Design and Operation
of Successive Approximation Register
(SAR) ADC
ECE 614 - Spring ‘08
April 28,2008
By Prashanth Busa
Talk Outline
Various ADC Architectures
(cid:1)
SAR ADC Introduction and Operation
(cid:1)
Charge Redistribution SAR ADC
(cid:1)
Different SAR ADC topologies
(cid:1)
Comparison with other ADCs
(cid:1)
Summary
(cid:1)
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Various ADC Architectures
Figure from ref [2]
Plot of Resolution vs Conversion rate.
(cid:1)
SAR ADCs are available from 8-18 bits resolution with
(cid:1)
sampling rates up to 5Msps.
Higher accuracy, low power and used in medium
(cid:1)
speed/medium-high resolution applications.
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SAR ADC History
First commercial converter, 1954 "DATRAC" 11-Bit, 50-kSPS SAR ADC
(cid:1)
Designed by Bernard M. Gordon at EPSCO.
Today, the state of the art SAR ADC reported is 18 bit, 2Msps fully
(cid:1)
differential with a single power supply of 2.5v.
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Successive Approximation ADC
Implements Binary search
(cid:1)
algorithm
Initially, DAC input set to
(cid:1)
midscale (MSB =1)
V < V MSB remains 1
(cid:1)
IN DAC ,
V > V MSB set to 0
(cid:1)
IN DAC ,
Algorithm is repeated until
(cid:1)
LSB
End of algorithm, DAC
(cid:1)
[input] = ADC [output]
N cycles required for N-bit
(cid:1)
conversion
Figure from Maxim semiconductors ref [3]
Simplified SAR ADC Architecture
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SAR Operation
DAC [in]=ADC [out] =101000
V = V /2
DAC REF
Start -100000
A 6-bit SAR ADC Example, V = 5/8 V
Simplified SAR ADC Architecture IN REF
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SAR Timing diagram
Figure from Analog Devices, ref[4]
(cid:1) The positive going edge of CONVST indicates the start of conversion,
the input sample and hold is in the hold mode from this edge and
various bits are determined using SAR algorithm.
(cid:1) When CONVST goes low the busy signal goes high and the BUSY line
goes low at the end of conversion process.
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A simple Charge Redistribution DAC
Assuming C1=C2 Charging C1 to Vref, C2 grounded
Discharging C1,C2 – S3 and S4 closed
Charge sharing C1,C2 –> V = Vref/2
0
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Figures from ref[2]
Simple Charge redistribution DAC cont’d
If bit =1, S2 is closed Depending on input,
=0, S3 is closed V =(V /2 + V /4) for S2 closed (b=1)
0 ref ref
= V /4 for S3 closed (b=0)
ref
Figures from ref[2]
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Charge Redistribution SAR ADC
Figure from ref[2]
(cid:1) Provides inherent T/H operation.
(cid:1) Initially, S is grounded and all the capacitors connected to V .
reset IN
(cid:1) MSB top plate is opened and MSB cap bottom plate connected to V
REF
resulting in –V + V /2 on the input of comparator.
IN REF
(cid:1) If –V + V /2 > 0 ,MSB =0 else MSB =1.
IN REF
(cid:1) Next cycle MSB-1 bit is connected to V ,algorithm is repeated until
REF
LSB.
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