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Programmable voltage reference generator for a SAR-ADC PDF

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Institutionen för systemteknik Department of Electrical Engineering Examensarbete Programmable voltage reference generator for a SAR-ADC ExamensarbeteutförtiElectronicsSystems vidTekniskahögskolanvidLinköpingsuniversitet av GeorgiosMylonas LiTH-ISY-EX–13/4717–SE Linköping2013 DepartmentofElectricalEngineering Linköpingstekniskahögskola Linköpingsuniversitet Linköpingsuniversitet SE-58183Linköping,Sweden 58183Linköping Programmable voltage reference generator for a SAR-ADC Examensarbete utfört i Electronics Systems vid Tekniska högskolan vid Linköpings universitet av GeorgiosMylonas LiTH-ISY-EX–13/4717–SE Handledare: JJacobWikner Examinator: JJacobWikner Linköping,11september2013 Avdelning,Institution Datum Division,Department Date ElectronicsSystems DepartmentofElectricalEngineering 2013-09-11 SE-58183Linköping Språk Rapporttyp ISBN Language Reportcategory — (cid:3)Svenska/Swedish (cid:3)Licentiatavhandling ISRN (cid:3)(cid:2)Engelska/English (cid:3)(cid:2)Examensarbete LiTH-ISY-EX–13/4717–SE (cid:3)C-uppsats Serietitelochserienummer ISSN (cid:3)D-uppsats Titleofseries,numbering — (cid:3) (cid:3)Övrigrapport (cid:3) URLförelektroniskversion http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-XXXXX Titel ProgrammablevoltagereferencegeneratorforaSAR-ADC Title ProgrammablevoltagereferencegeneratorforaSAR-ADC Författare GeorgiosMylonas Author Sammanfattning Abstract SAR-ADCsareverypopularandsuitableforconversionsuptofewtensofMHzwith8to12 bitsofresolution.AverypopulartypeistheChargeRedistributionSAR-ADCwhichisbased onacapacitivearray. Higherspeedscanbeachievedbyusingtheinterleavingtechnique whereanumberofSAR-ADCsareworkinginparallel. Thesespeeds,however,canonlybe achievedifthereferencevoltagecancopewiththeswitchingofthecapacitivearray. InthisthesisthedesignofaprogrammablevoltagereferencegeneratorforaChargeRedis- tributionSAR-ADCwasstudied.Anumberofarchitectureswerestudiedandonebasedona CurrentSteeringDACwaschosenbecauseofthesettlingtimethatcouldoffertotheCharge RedistributionSAR-ADCswitchingoperation.Thisarchitecturewasfurtherinvestigatedin ordertospottheweakpointsofthedesignandtrytominimizethesettlingtime. Intheend,thefinaldesignwasevaluatedandpossibletrimmingtechniqueswereproposed thatcouldfurtherspeedupthedesign. Nyckelord Keywords voltagereference,ADC,DAC Abstract SAR-ADCsareverypopularandsuitableforconversionsuptofewtensofMHz with8to12bitsofresolution. AverypopulartypeistheChargeRedistribution SAR-ADC which is based on a capacitive array. Higher speeds can be achieved by using the interleaving technique where a number of SAR-ADCs are working inparallel. Thesespeeds,however,canonlybeachievedifthereferencevoltage cancopewiththeswitchingofthecapacitivearray. In this thesis the design of a programmable voltage reference generator for a Charge Redistribution SAR-ADC was studied. A number of architectures were studied and one based on a Current Steering DAC was chosen because of the settling time that could offer to the Charge Redistribution SAR-ADC switching operation. This architecture was further investigated in order to spot the weak pointsofthedesignandtrytominimizethesettlingtime. Intheend,thefinaldesignwasevaluatedandpossibletrimmingtechniqueswere proposedthatcouldfurtherspeedupthedesign. iii Acknowledgments First of all, I would like express my special thanks of gratitude to Dr. Jacob Wikner for his support and guidance throughout this project. His comments andhishelpwereeducatingandinspiring. IwouldalsoliketothankDr. RobertHägglundfromAnaCatumABwhotrusted mewiththisprojectandMr. PavelAngelovforhishelpandsuggestions. IwouldliketothankmyfiancéeCharaforhersupportandherpatienceduring mystudies. Finally,Iwouldliketothankmyparentsandmysisterfortheirsupportandtheir unconditionallove. Linköping,September2013 v

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In this thesis the design of a programmable voltage reference generator for a Charge Redis- tribution . 4.20 Splitted bias current reference generator topology . 38 . A well defined and independed to temperature bandgap . algorithm in order to estimate the digital representation of the input.
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