Principles and Practices (4th Edition) [John F. Wakerly].

918 Pages·2012·61.05 MB·English

ital Design
and Practices
th Edition

John F. Wakerly
DIGITAL DESIGN
Principles and Practices

Fourth Edition

John F. Wakerly

Cisco Systems, Inc.
Stanford University
Watery Jo F
Dipl evgn: rnin and pracice Jo F. Wakely th ed

ISBN 0-11863604

1 Digit interascute-Design an consti. Tile
‘Tre7465434 2008
lava

Vice rset nd Eritrea, ECS: Marie Harton
dora Asan Rchrd Pig

Executive Managing Eto Vince O'Brien

Minaing Etor Dovid George

Proton Eder: So Dison

Bistro Crete Secs Poul Bola

‘At Decor Kew Beck

(Cover Desig: Brace Kenselaar

Ar Ete: Nioohong 2

‘Manufcring Manager Ales Med-Lone
Manufctring Byer: Liaw NeDovell

SesorMareting Manager Hol) Sark

‘Aout he Cover Orginal ove werk © 2001 Ken Bakeman, wow kena com

{© 2006, 200.1994, 190 by Pearson Edson Ie
Feaon Prentice Hall

Pan Ect

Upper Se River NJ O7HS6

‘Person rie Hallie radar of Pearson Education ns.

“The author and pubis of his ook have sd te et fos in raring this ook. Tex efor inde he develop
‘net ewarch nesting of he eres and porns to deen the <evtneyess: The suo an publisher stall

[eto in any even force consequent damages ithe arsing Of he faishing performance, fe of
these propa

‘Verge a wadema of Cadence Desin Systems Ine Sis ia wade of Simucad In. Synopsys, nd Foundation
grenades of Smaps, Ine. Kili ested wader of Xin Corp, Als sauder fA.

ISBN 0-13-186389-4
1098765432

Pearson Edson Led. Londo
Pes Eduation Asai Py. Lt. Syeney

Pearson Edneaton Singapore Pe: Lid

Peart Edisaton North Ass i, Hong Kong

Peano Eston Cann, Torn

Pears Ediacin de Meio, S.A. de CY.

Pearson Edtcaion Jaan Tyo

Pear Edtstion Malye, Pe. Lid

Pear Edition, ne, Upper Sale River, New Jesey
To Joanne
CONTENTS

PREFACE wv

1 INTRODUCTION 1
‘About Digital Design 1

‘Analog versus Digtal 3

Digtl Devices 6
Electonic Aspects of Dig! Design 7
Software Aspecs of Digital Design 8
Integrated Creuts 11
Programmable Logic Devices, 14
‘Aapleaton-SpectcCs 16
Prted-Crout Boards 17

1.10 DigtahDesign Levels 18

111 TheName ofthe Game 22

1.12 Going Forward 23

rit Prebiems 23

2 NUMBER SYSTEMS AND CODES 25
21 Postional Number Systoms 28
22 OctalansHexadecimal Numbers 27
23 Genera PosiionaNumberSysten Conversions 29
2.4 aden and Subtraction of Nondecmal Numbers 2
25 Representation of Negative Numbers 34
251 Signed Magnitude Representation 28.2 Complement Number Systems
25.3 Ratit-Complement Representation
1254 To's Complement Representation
1255 Diminished Radi Complement Representation
1256 Ones Complement Representation 237 Excet Representations
28 Two's Comploment Acton and Subtraction 39
261 Adon Rules 262 AGrophicel View 26.3 Overfow
26:4 Subwracion Rules 268 Two's Complement and Unsigned Binary Numbers
27 Ones'-Complement Adon and Subtraction 38
28 Binary Mutipleaion 45
vil Contents

29. BharyDWelon 47

210 Binary Codes for Decimal Numbers 48

211 Gray Code 81

212 CharactrCodes 53

213 Codes for Actions, Contons and States 53

214 Cubes and Distance 57

2.18 Codes or Detecting and Corectng rors 58
2ISI ror Detecting Codes
2152 Error Corecing and Maile Error Detecting Codes
2US3 Harming Codes” 2.134 CRC Codes
2155 Two-Dineninal Codes 2186 Checks Codes
2IS7 mourofn Codes

£2.16 ‘Codes or Sel Data Transmission and Storage 69
21641 Parallel and Serial Data 2.162 Serial Line Codes

Feforonces 73

Dri Probes 78

Exercises 78

3 DIGITALCIRCUTS 79
31 Logie Signals and Gates 80
32 Loge Famios | 64
33 CMOSLoge 86
BAL CMOS Logic Levels 3.22 MOS Trasnors
4323 Basie CMOS verter Circle
43.4 CMOS NANO and NOR Gates 335 Fann
338 Noninerting Gates
“337 CMOS ANO-OR-AVERT and ORANDANVERT Gates
24 Elctcal ahavor of CMOS Grete 96
441 Overiew 242 Data Shes and Speifcatons
35 CMOS Stat Electrical Behavior 101
43.5) Lopic Levels and Nose Margins
13582 Greit Behavior wth Resistive Loads
1353 Cieit Behavior wih Noida! puss 254 Fonout
355 fects of Loading 356 Unsed Ips
1357 How to Destroy @ CMOS Device
38 CMOS Dynamic Electrical Behavior 114
361 Transition Tone 32 Propagation Delay
1363 Power Consumption
136.8 Current Spies ond Decoupling Copacors
36S Inducve Eee
‘366 Simalianeous Switching and Grownd Bounce
87 Other CMOS input and Ouput Structures 129
271 Transmision Gates 372 Schmit-Triger Inputs
373 TireesStave Outs 374 Open-Drain Oupus
1273 Driving LEDs 3.76 Multsource Buses 37.7 Wired Loge
378 Pull Resistors
38 CMOS Loge Famites 141
$81 HCandHCT 382 AHCand AHCT
$243 HC HCT, AHC, ond AHCT Electra! Characterisies
384 ACondACT "385 FCTand FCTT
386 FCT Elecrical Charactriaics
389° Low-Votage CMOS Loge andintetacing 181
391 23-VLVITL end LVCMOS Logic 3.92 5.V Tolerant Inputs
39.3 $.VToleront Oupats 3944 TTLALVTTL inefacing Story
1393 Lope Level Less Than 33 V
310 BipoarLoge 158
LID] Diode Loic 3.102 Bipolar untion Transistors
3.10.3 TransiorTranisor Logie
‘310 TIL Logic Levels ond Nowe Morgins 3105 TTL Fonout
2108 TTL Familer 3.107 ATTL Data Shee
318 CHOSTTL merece 3.109 BninerCovpled Logie
Reloronces 174
nl Probems 175
Erercises 179

‘COMBINATIONAL LOGIC DESIGN PRINCIPLES 183
41 Switching Algebra 194
411 Avloms 41.2 Single-Varihle Theorems
‘4153 Two: and Thre-Varabe Theorems
414 nNeriable Theorems 4.1.8 Duality
‘415 Standard Representation f Lope Functions
42 CombinatonalCreut anayss 109
43. Combhnaonal Circuit Syethesis 205

‘431 Chet Descriptions and Designs 43.2 Cire Manpations

£33 Combinational Circuit Minimisation 434 Karnaugh Maps

‘£35 Mrnimiing Sums of Products 436 Other Minimization Topics

‘£37 Programmed Minimisation Methods
444 Timing Hazards 224
441 Static Hesards 442 Fin Sac Hasards Using Maps
4543 Dynamic Hazards 444 Designing Hasard-Free Cleats
Reteroncas

HARDWARE DESCRIPTION LANGUAGES 237
51 HOL-Based Digi Design 208
S11 Why HDLs? $1.2 HDL Too Suter
‘S13 HDL-Rased Design Flow
52 The ABEL Haraware Description Language 243,
521 ABEL Program Simezare 522 ABEL Compiler Operation
‘$23 AMEN Stoement and Equation Blocks 524 Trath Tables
15255 Ranges Sts and Relaons 52.6 Test Vecors,
‘527 Addtional ABEL Features
Contents

53. The VHOL Hardware Description Language 258
531 Program Smactre 5.32 Types, Constants. and Arrays
‘53.3 Functions and Procedures S34 Libraries and Packages
‘S45 Siractural Design Elements 5.38 Datelow Design Elements
‘S37 Behavioral Design ements 18 The Tone Dimension
‘539 Simulation 5.3.10 Teat Benches
‘53.11 VHDL Features for Sequential Loge Design 5.3.12 Syhesis.

‘54 The Veriog Hardware Deserpton Language 290
S41 Program incre
$42 Logie Sistem, Nets Variables, and Constams
1543 Vecwors and Operators Sd Arrant
‘S45 Logical Operators and Expressions $46 Compiler Directives
‘547 Sincturl Design Elenents 548 Dataow Design Elements
‘$49 Behavioral Design Elements (Procedural Code)

S410 Functions and Tasks 5411 The Tone Dimension
S412 Simulation 54.13 Tes Benches
5414 Venlog Features or Sequential Lape Design S18 Syhesis.

COMBINATIONAL LOGIC DESIGN PRACTICES 341
61 Documentation Standards 342
6.11 Block Diagrams 6.12 Gate Symbols
46.13 Signal Names ond Active Levels 614 Active Levels for Pas
{515 Babble Bubble Logie Devon
{6116 Signal Naming in HDL Programs 61.7 Drawing Layout
618 Bases 619 Additional Schematic Iformation
62. Gieut Timing 362
621 Timing Diogroms 62.2 Propagation Delay
623 Timing Specicuions 624 Taming Anasis
{625 Timing Analysis Tools
63. Combinaional PLDs | 370,
6.3. Programmable Logic Arrays
6.32 Programmable Array Logie Devices
63.3 Generic Aray Lape Deices
62:4 Complex Programmable Logic Devices (CPLDs)
63.5 CMOS PLD Ciruis 64 Desice Programming and Tsing
84 Decoders 364,
641 Binary Decoders
‘642 Lopc Symbol for Larger Scale Elements
4643 The 4138 40-8 Decoder 4d Cascading Binary Decoders
(643 Decoders in ABEL ond PLDs 546 Decoder in VHDL.
{647 Decoders in Vrlog 64.8 Sevn-Segment Decoders
85. Encoders 408
{651 Priority Encoders 62 The 7x148 Priority Buoder
{65.3 Encoders mABEL and PLDs 654 Encadersin VHDL
655 Encoders in Verilog
Contents

65 TwooState Devices 416
66.1 TireeState Buffers 652 Standard MSI Thre Sate Burs
{56.3 Three State Outputs in ABEL and PLDs
{5654 Tiree State Outputs in VHDL
66.5 Tree State Ouputs i Verilog

67 Mailers 432
421 Sundord MSI Muliplerers 67.2 Exponding Mulplesers
‘473 Mutiplesers Demuliplesers and Buses
(674 Muliplsers mABEL and PLDs 67-5 Mliplevers in VADL.
678 Maliplesers in Verilog

(68 Excusive-OR Gates and Party Creuts 447
81 Bxeushe-OR and Exeushe NOR Gates 6552 Party Circ
683 The 74280 9B Parity Generstor
{58:4 Poriy-Checting Applicaions
{543 ExcusneOR Gater ond Party Cir bx ABEL ond PLDs
686 Excushe OR Gater and Party Cru bn VHDL
687 Bxeushe OR Gates and Party Circus Verilog

89 Comparatos 458
9.1 Conpuraor Simctre 69.2 erative Cres
69.8 Anferave Compara Circuit
{694 Stondord MSI Magritade Comparators
{693 Conmpareorsin HDL 69 Comparators i ABEL and PLDs
{69.7 Comparators in VHDL. 6938 Comparators in Verilog

{610 Aare, Subvactors, and ALUS 474,

(610 Half Adders nd Full Adders 6102 Ripple Adders

{5103 Subiroctrs 6.104 Carr-Lovkahead Adders

6103 MSIAdders 6106 MSI Arete and Logi Units
{610.7 Growp-Carry Lookahead 6.1058 Addersn ABEL and PLDs
109 Adder in VHDL 61010 Adders in Veriog

6.11 Combinatoral Mutipors 494
GILL Combinational Maier Sracures
112 Malipiation n ABEL and PLDs 6.11.3 Muiplicaion in VHDL.
{6.114 Matplication in Verog

etorences 508

Dri Proiems 500

Erercises tt

SEQUENTIAL LOGIC DESIGN PRINCIPLES 521
71. Bible Elements 523,
ZL) Dipl Anatyis 7.1.2 Analog Analysis:
71.3 Metastable Behavior
72 Latches and Flip-Flops 526
72) $Alaich 722 BA Lach 72.3 $A Latch with Enble
724 Dlatch 7.2.5 EigeTrigeredO Flip-Flop
726 Edge Trgpered 0 FlipFlop wih Enable 7.2.7 Sean Fli-Flop
728 MasterfSave S# FlipFlop 729 MasterSlee #X FlipFlop
10 Edge Trgnered 3X FlipFlop 7.2.11 T FlipFlop
73

4

70

at

732

73

‘Gockas Synchronous Stale Machine Analysis 542
71 State Machine Srucure 7.42 Output Logie

73.3 Characteristic Equations

734 Anal of State Machines wih 0 Flip-Flops

‘Gcckad Syncwonous State Machine Design 553

74.1 Stae-Tabe Design Example 74.2 State Minimization

74.3 State Assignment 7-44 Syiheis Using D Flip-Flops

745 Syhesis Using 2K Flip-Flops

74 More Desig Examples Using Flip-Flops

Designing State Machines Using State Diagrams _570

‘State Machine Synthesis Using Traction Lists 577

741 Transition Equations 7.82 Evcaion Equations

763 Variations on the Scheme 74 Reaiing the State Machine
‘ArcnerState-Machine Design Example 580

72) The Guessing Gane 772 Unased Sates

7273 Oupu-Coded Stat Assignment

774 “Don'-Care” Sate Codings

Decomposing Sate Machines 887

Feedback Sequenta-CrcutAnaiyss 550

791 Basi Antsis

792 Analcing Crs ith Malaple Feedback Loops

793 Races 7. Sate Tables ond Flow Table

293 CMOS D Flip-Flop Analysis

Feedback Sequontia-Creut Design 601

710 Latches 7.102 Desiging Fundameral‘Moe Flow Table
7.103 Flow-Toble Minimisation 7.104 Race-Free State Assignment
7105 Exetation Eqaions 7.106 Essential Hazards

7107 Simenary

[ABEL Sequonla-Crcut Design Featres 612

ZL Registered Outs 7.11.2 State Diograms

713 External State Memory 7114 Spectying Moore Opts
ZL Spectiving Meny and Pipelined Ovurs with KITE

216 Test Vectors,

Sequentia-Creut Design wth VHOL 625,

ZURI Cloched Cress 7.12.2 Sate Machine Design wth VHDL
7123 A VHDL Stateachne Exmple

124 State Assignment VHDL. 7.125 Pipelined Outputs in VHDL.
7.126 Direct VHDL Coding Without Se Table

2127 More VHDL State-Machine Examples

7128 Specfing FipFopsin VHDL

7129 VHDL State-Machne Test Benches

712.10 Feedback Sequential Cireuts

Sequenta-Creut Design wth Veriog 646

7431 Clocked Cieitr 7142 State Machine Design wih Verilog
7133 A Veron State-Machine Example

7134 Pipelined Oxptsin Verilog

7185 Direc Verilog Coding Withou a Sate Tobe

7135 More Verilog State Machine Examples