PRINCIPLES AND CIRCUITS Part 1

16 Pages·2016·5.44 MB·English

PRINCIPLES CIRCUITS
AND
E Part 1
Field-Effect Transistors
Ray Marston explains FET
by Ray Marston
(Field-Effect Transistor)
basics in this opening
episode of this new
four-part series.
F
ield-Effect Transistors by charge-storage problems, of using FETs.
transistor. Two distinct families of
(FETs) are unipolar and they thus outperform
FETs are in general use. The first of
devices, and have two most bipolars in terms of digi FET BASICS these is known as 'junction-gate'
big advantages over tal switching speeds. types of FETs; this term generally
bipolar transistors: one is that Several different basic An FET is a three-terminal ampli being abbreviated to either JUGFET
they have a near-infinite input types of FETs are available, fying device. Its terminals are known or (more usually) JFET.
resistance and thus offer near and this opening episode as the source, gate, and drain, and The second family is known as
infinite current and power looks at their basic operating correspond respectively to the emit either 'insulated-gate' FETs or Metal
gain; the other is that their principles. Parts 2 to 4 of the ter, base, and collector of a normal Oxide Semiconductor FETs, and
switching action is not marred series will show practical ways these terms are generally abbreviat
ed to IGFET or MOSFET, respectively.
V+
'N-channel' and 'p-channel' versions
V+ V- Drain of both types of FET are available,
Depletion just as normal transistors are avail
region
able in npn and pnp versions. Figure
1 shows the symbols and supply
polarities of both types of bipolar
Gate
transistor, and compares them with
ov ov
Figure 1.
both JFET versions.
(a) npn transistor (b) pnp transistor Comparison of /
Figure 2 illustrates the basic con
transistor and
V+ V- JFET symbols, ..L n struction and operating principles of
notations, and + Source a simple n-channel JFET. It consists of
supply polarities. a bar of n-type semiconductor mate
ov
rial with a drain terminal at one end
and a source terminal at the other. A
Figure 2. Basic structure of
p-type control electrode or gate sur
a simple n<hannel JFET,
ov ov rounds (and is joined to the surface
showing how channel width is
of) the middle section of the n-type
(c) n-channel JFET (d) p-channel JFET controlled via the gate bias.
bar, thus forming a p-n junction.
In normal use, the drain terminal
B0 B-11 is connected to a positive supply and
PRIMTED the gate is biased at a value that is
EASILY ADD TEXT negative (or equal) to the source
voltage, thus reverse-biasing the
TO VIDEO WITH
CIRCUIT BOARDS JFET's internal p-n junction,
and accounting for its very high
• Auto-switching genlock overlay module input impedance.
With zero gate bias applied, a
• Generates complete video signal on-board
Since 1969 current flow from drain to source via
• Up to 308 characters in 11 rows, 28 cols
Prototype to Production a conductive 'channel' in the n-type
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region is formed within the junction,
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and reduces the width of the n-type
•Single Sided •Surface Mount
• Compatible with Parallaxtm BASIC Stamptm conduction channel and thus
•Double Sided •Punch Press reduces the magnitude of the drain
• • •Multi-Layer Capability to-source current. As the gate bias is
Video~ 808-11 -+
increased, the 'depletion' region
•LP!
spreads deeper into the n-type chan
J
nel, until eventually, at some 'pinch
Serial Data QUICK TURN AROUND
Sensors • 0 0 0 c::;:) off' voltage value, the depletion layer
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1/0 . Microcomputer NTSC or PAL ceases.
~
CIRCUIT ETCHING TECHNICS Thus, the basic JFET of Figure 2
I Since 1969 passes maximum current when its
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II
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11 DECADE ENGINEERING Toll Free: 888-657-3827 a 'depletion-type' n-channel JFET. A
Tel: [phone]- Fax: [phone] E-MAIL - [email protected] p-channel version of the device can
www .decadenet.com WEB ADDRESS - (in principle) be made by simply
WWW.MET-NET.COM/USERS/CET transposing the p and n materials.
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•
Source Gate Drain :::l:lio:sts-.----.'.--:-:-...1..:-:-:-.':-- . In In
10 VGS•OV
Figure3. ! I I I I Figure 5.
Construction 8 --~I- An n-channel G
n-channel of n-channel JFET can be =
Substrate (p) JFET. ---'I ~--,"-"-T"-,"-----;,-----:--,:-- -rVas • ·1V used as a
voltage
1 I I I
~,..' __1, __..,...,.1........,"""1" '~VGS = ·2V controlled
resistor.
c:
V+ Figure 4. g ov
2 -l....-+---ii---r--r--t-VGS • ·3V
Idealized
Off transfer '/~.;.--~~---~-~-t-VGS = -4V
On = cohf aarna cteristics 5 10 15 20 25 In -1I
n-channel +ve drain-to-source voltage,
Vos (vohs)
JFET. JlJ1IL
-ve G = JlJlIL--
Figure 6. An n-channel a 'knee' occurs on each curve, and transconductance, gm, ov
JFET can be used as a that 10 then remains virtually con and denotes the magni
voltage-controlled switch.
stant as Vos is increased beyond tude of change of drain ov ov
the knee value. Thus, when Vos is current with gate volt
below the JFET's knee value, the age, i.e., a gm of Figure 7. An n-channel JFET can be used as
JFET DETAILS drain-to-source terminals act as a 5mA/V signifies that a an electronic chopper.
resistor Ros. with a value dictated by VGs variation of one
1
Figure 3 shows the basic form of VGs. ar1d can thus be used as a volt volt produces a 5mA change in 10. can be used as a common source
construction of a practical n-channel age-variable resistor, as in Figure 5. Note that the form l/V is the inverse amplifier (corresponding to the bipo
JFET; a p-channel JFET can be made Typically, Ros can be varied from of the ohms formula, so gm mea lar npn common emitter amplifier)
by transposing the p and n materials. a few hundred ohms (at VGs = 0) to surements are often expressed in by using the basic connections in
All JFETs operate in the depletion thousands of megohms (at VGs = Vp), 'mho' units. Usually, gm is specified in Figure 9.
mode, as already described. Figure 4 enabling the JFET to be used as a FET data sheets in terms of mmhos Alternatively, the common drain
shows the typical transfer character voltage-controlled switch (Figure 6) (milli-mhos) or µmhos (micro-mhos). or source follower (similar to the
istics of a low-power n-channel JFET, or as ,an efficient 'chopper' (Figure 7) Thus, a gm of 5mA/V = 5-mmho or bipolar emitter follower) configura
and illustrates some important fea that does not suffer from offset-volt 5000-µmho. tion can be obtained by using the
tures of this type of device. The most age or saturation-voltage problems. In most practical applications, connections in Figure 10, or the com
important characteristics of the JFET Also note in Figure 4 that when the JFET is biased into the linear mon gate (similar to common base)
are as follows: Vos is above the knee value, the 10 region and used as a voltage amplifi configuration can be obtained by
value is controlled by the VGs value er. Looking at the n-channel JFET, it using the basic Figure 11 circuit. In
(1). When a JFET is connected to and is almost independent of V s.
0
a supply with the polarity shown in i.e., the JFET acts as a voltage-con
V+ V+ V+
Figure 1 (drain +ve for an n-channel trolled current generator. The JFET
FET, -ve for a p-channel FET}, a drain can be used as a fixed-value current
current (10) flows and can be con generator by either tying the gate to Figure 8. An. =
trolled via a gate-to-source bias volt the source as in Figure B(a), or by n-channel JFET or
age VGs· applying a fixed negative bias to the can be used as a
(2). 10 is greatest when VGs = 0, gate as in Figure B(b). Alternatively, it constant-current
and is reduced by applying a reverse can (when suitably biased) be used as generator. ov ov ov
bias to the gate (negative bias in an a voltage-to-current signal amplifier. (a) (b) (b)
n-channel device, positive bias in a (5). FET 'gain' is specified as
p-type). The magnitude of VGs need
ed to reduce 1 to zero is called the
0
BIG
'pinch-off' voltage, Vp, and typically
has a value between 2 and 10 volts. POWER
The magnitude of 10 when VGs = 0 is
denoted loss. and typically has a
LOW COST
value in the range 2 to 20mA.
(3). The JFET's gate-to-source
junction has the characteristics of a Dominos are rugged, miniature
silicon diode. When reverse-biased, encapsulated controllers that
com-bine lots of analog and
gate leakage currents (IGss) are only
digital 1/0 with a fast control-
a couple of ·nA (1nA = .001µA) at llillllgiiiiiill oriented floating-point BASIC to
room temperature. Actual gate sig provide a one-stop computation
nal currents are only a fraction of an and control solution for cost
sensitive control tasks. Used
nA, and the input impedance of the
stand alone or connected via
gate is typically thousands of
RS-232/RS-485, Dominos are
megohms at low frequencies. The true plug-and-go control.
gate junction is shunted by a few pF,
so the input impedance falls as fre Domino 1 features: Domino 2 has:
quency rises. • Full floating-point ROMed BASIC • everything in Domino 1 plus
If the JFET's gate-to-source junc • 32-KB SAAM arid 32-KB EEPROM
• I 2 bits of parallel 1/0 • 16 more bits of high-current parallel 1/0
tion is forward-biased, it conducts • 2 PWM outputs • Hardware clock/calendar
like a normal silicon diode. If it is • 12C bus • Wide-range power operation
excessively reverse-biased, it • 2-channel 12-bitADC • Hardware f¥IM output
•Serial port: 19.2-kbps RS-232A,
avalanches like a zener diode. In RS-4 22, or RS-485 $99 to $139
either case, the JFET suffers no dam • +SV@ ISmA
age if gate currents are limited to a Visit our Web site for complete datasheets
few mA. www.micromint.com
(4). Note in Figure 4 that, for
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each VGs value, drain current 10 rises To Order Call:
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Figure 16.
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VFET DEVICES RF Data Modules
and Figure 15 shows the VGs/1
0
curves of the same device when In a normal small-signal JFET or
powered from a 1S V supply. Note MOSFET, the main signal current ..
• .
that no lo current flows until the gate flows 'laterally' (see Figures 3, 12, ' . ,. .
' .
voltage reaches a 'threshold' (Vrn) and 13) through the device's con ' ..
·..
value of a few volts, but that beyond ductive channel. This channel is very \ ~
this value, the drain current rises in a thin, and maximum operating cur 11 I I 11 ( 1111 I 1a11, .. -,.~ . ~t .••
non-linear fashion. rents are consequently very limited
Also note that the transfer graph (typically to maximum values in the
is divided into two characteristic range 2 to 40mA). ••SCmMaOll SsiIzTeI: L1 7in.7p8u tx I l.43mm ••OConm-bpoaacrtd sdizaeta: r3e8co.1vxer1y3. .C7mMmOS ••OUnpl yto 2 430 xk 3b3p sx d laltma rmat e
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the dotted line, these being the 'tri facturers have tried to produce viable •Low Current. 4mA typical. •2kHz data rate. CMOSITIL output •Up to 500ft. range
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The basic n-channel MOSFETs of .of these devices is the 'VFET,' an
;
Figures 12 and 13 can - in principle enhancement-mode power MOSFET
- be converted to p-channel devices which was first introduced by
•Up to 19,200 bps half duplex
by simply transposing their p and n Siliconix way back in 1976. •4,800 to 38,400 bps half duplex •3 wire RS232 interface
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Supports 8 or 9 bit protocols
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•418 MHz and 433MHz versions
A number of sub-variants of the the top, followed by a p-type 'body' •Range up to 500ft. (0.25mW ver.) • 1/4 wave wire antenna on board
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conduction channel and a conse two layers and into the third layer of
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ftABAcoM
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MOSFET variants are described in the dioxide film) to the gate terminal.
• ' TECHNOLOGIES
remainder of this opening episode. If the gate is shorted to the
Note that the very high gate source, and the drain is made posi-
Nuts & Volts Magaztne/MA'i 2000 17
Insulation (Si Oz)
Figure 18. The IR HEXFET comprises
a balanced matrix of parallel
connected low-power MOSFETs,
which are equivalent to a single
high-power MOSFET.
Drain
Figure 17. Basic structure of the VFET
power device. Figure 19. The basic
TOPF~
internal circuitry (a)
and the circuit symbol
Power
MOSFET Input~ (b) of the TOPFET
Figure 20. Normal circuit (Temperature and
symbol of the IGBT s Overload Protected
(Insulated Gate Bipolar MOSFET).
Transistor). Source
(a) (b)
tive, no drain-to-source current flows, version of the 'VMOS' technique, with current rating (up to 16A), low on operating current equally between
because the diode formed by the p a U-shaped groove (plus other modifi resistance (down to 50 milliohms), them; the device thus acts like a sin
and n materials is reverse-biased. But cations) that improved device reliabili and very fast operating speeds (up to gle high-power MOSFET. These high
if the gate is made positive to the ty and gave higher maximum operat 2GHz at 1A, 500MHz at 10A). power devices are known as lateral
source, the resulting electrostatic ing currents and voltages. In 1980, · Siemens of West Germany used a MOSFETs or L-MOSFETs, and give a
field converts the area of p-type Siliconix added these and other modi modified version of DMOS, known as performance that is particularly useful
material adjacent to the gate into n fications to their own VFET devices, SIPMOS, to produce a range of n in super-fi audio power amplifier
type material, thus creating a con resulting in further improvements in channel devices with voltage ratings applications.
duction channel in the position performance. as high as 1k V and with current rat Note that, in parallel-connected
shown in Figure 17 and enabling cur ings as high as 30A. MOSFETs (as used in the internal
rent to flow vertically from the drain OTHER POWER FETs One International Rectifier solu structure of the HEXFET and L-MOS
to the source. tion to the power MOSFET problem is FET devices described above), equal
As the gate becomes more posi Several manufacturers have pro a device which, in effect, houses a current sharing is ensured by the con
tive, the channel width increases, duced viable power FETs without vast array of parallel-connected low duction channel's positive tempera
enabling the drain-to-source current using 'V'- or 'U'-groove techniques, power vertical MOSFETs or 'cells' ture coefficient; if the current in one
to increase as the drain-to-source but still relying on the vertical flow of which share the total current equally MOSFET becomes excessive, the
resistance decreases. This basic VFET current between drain and source. In between them, and thus act like a sin resultant heating of its channel raises
can thus pass reasonably high cur the 1980s, Hitachi produced both p gle high-power MOSFET, as indicated its resistance, thus reducing its cur
rents (typically up to 2A) without cre channel and n-channel power MOS in Figure 18. These devices are named rent flow and tending to equalize it
ating excessive current density within FET devices with ratings up to 8A and HEXFET. after the hexagonal structure with that of other parallel-connected
the channel regions. 200V; these devices were intended of these cells, which have MOSFETs. This feature makes such·
The original Siliconix VFET design for use mainly in audio and low-RF a density of about 100,000 per power MOSFETs almost immune to
of Figure 17 was successful, but applications. square centimeter of semiconductor thermal runaway problems._
imperfect. The sharp bottom of its V Supertex of California and material. Today, a vast range of power
groove caused an excessive electric Farranti of England pioneered the Several manufacturers produce MOSFET types are manufactured.
field at this point and restricted the development of a range of power power MOSFETs that each comprise a 'Low voltage' n-channel types are
device's operating voltage. MOSFETS with the general title of large array of parallel-connected low .readily available with voltage/current
Subsequent to the original VFET intro 'vertical DMOS.' These featured high power lateral (rather than horizontal) ratings as high as 1O OV/ 75A, and
duction, lntersil introduced their own operating voltages (up to 650V), high MOSFET cells that share the total 'high voltage' ones with ratings as
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Write In 129 on Reader Service Card. Write In 135 on Reader Service Card. Nuts & Volts Magazine/MA'I 2000 19
PRINCIPLES CIRCUITS
AND
Part 2
Field-Effect Transistors
by Ray Marston
Ray Marston looks at
practical JFET circuits in
this second episode of
this four-part series.
Last month's opening JFET BIASING
l
episode explained (among
other things) the basic oper The JFET can be used as a lin Figure 1. o~@-~ Gme@O~
J
ating principles of JFETs. ear amplifier by reverse-biasing its Outline and
JFETs are low-power devices gate relative to its source terminal, connections of
the 2N3819 and
with a very high input resistance thus driving it into the linear region. Gate
and invariably operate in the deple Three basic JFET biasing techniques MPF102 JFETs. Source
2N3819 MPF102
tion mode, i.e., they pass maximum are in common use. The simplest of (bottom view) (bottom view)
current when the gate bias is zero, these is the 'self-biasing'
and the current is reduced ('deplet system shown in Figure 3, r--
ed') by reverse-biasing the gate in which the gate is I Parameter 2N3918 MPF102
terminal. grounded via Rg, and any
Most JFETs are n-channel current flowing in Rs drives Vos max(= max. drain-to-source voltage) 25V 25V
(rather than p-channel) devices. the source positive relative VoG max(= max. drain-to-gate voltage) 25V 25V
Two of the oldest and best known to the gate, thus generat VGs max(= max. gate-to-source voltage) -25V -25V
n-channel JFETs are the 2N3819 ing reverse bias. loss(= drain-to-source current with VGs = OV) 2-20mA 2-20mA
and the MPF102, which are usually Suppose that an lo of IGss max (= gate leakage current at 25° C) 2nA 2nA
housed in T092 plastic packages 1m A is wanted, and that a Pr max(= max. power dissipation, in free air) 200mW 310mW
with the connections shown in VGs bias of -2V2 is needed
Figure 1; Figure 2 lists the basic to set this condition; the Figure 2. Basic characteristics of the 2N3819 and MPF102 n-channel JFETs.
characteristics of these two devices. correct bias can obviously
This month's article looks at be obtained by giving Rs a value of In practice, the VGs value need
basic usage information and appli 2k2; if lo tends to fall for some rea ed to set a given lo varies widely
cations of JFETs. All practical cir s.on, VGs naturally falls as well, and between individual JFETS, and the
cuits shown here are spe-:ifically thus makes lo increase and counter only sure way of getting a precise lo
designed around the 2N3819, but the original change; the bias is thus value in this system is to make Rs a
will operate equally well when self-regulating via negative feed variable resistor; the system is, how
using the MPF102. back. ever, accurate enough for many
PCB LAYOUT I r-J rE1 n -u _..
:1- ov
RAM~B~~ Figure 3. Basic JFET
Software For Windows • FREE 'self-biasing' system.
applications, and is the most widely
0 Download our board layout software used of the three biasing methods.
~,~;=::=::=I'
A more accurate way of biasing
6 Design your 2 sided plated-through PCB
the JFET is via the 'offset' system of
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• Completely assembled. NOT A KIT! gate voltage is large relative to VGs,
• Program in C, assembly, IC, etc. lo is set mainly by Rs and is not
• 32K RAM chip with 10 year battery backup greatly influenced by VGs variations.
This system thus enables lo values to
• 5 volt low drop-out voltage regulator
be set with good accuracy and with
• Max233 RS232 converter
out need for individual component
• Most signals available at expansion ports
selection. Similar results can be
• External mode, reset and power connections
obtained by grounding the gate and
• Available options include 1/0 expansion and
taking the bottom of Rs to a large
LCD board ' negative voltage, as in Figure 4(b).
• Comes with complete instructions The third type of biasing system
·Very small package: 2.1" x 3.0" is shown in Figure 5, in which con
• 1 year limited warranty stant-current generator Q2 sets the
--------- ONLY $145------------ lo, irrespective of the JFET character
www.expresspcb.com Ray's Robotic Racers [phone] istics. This system gives excellent
biasing stability, but at the expense
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of increased circuit complexity
30 JUllE 2000/N uts & Volts Magazine Write In 148 on Reader Service Card.
and cost. an input impedance of 2M2, and
V+
In the three biasing systems can use any supply in the 9V to 18V
described, Rg can have any value up range.
to 1O M, the top limit being imposed Figure 11 shows a self-biasing
by the volt drop across Rg caused add-on pre-amplifier that gives a
by gate leakage currents, which may voltage gain in excess of 20dB, has
upset the gate bias. a bandwidth that extends beyond
1O OkHz, and has an input imped
SOURCE FOLLOWER ance of 2M2. It can be used with
CIRCUITS any amplifier that can provide a 9V
to 18V power source.
When used as linear amplifiers, JFET common source amplifiers
JFETs are usually used in either the can - when very high biasing accu
source follower (common drain) or racy is needed - be designed using
common-source modes. The source either the 'offset' or 'constant-cur
follower gives a very high input rent' biasing technique. Figures 12
impedance and near-unity voltage and 13 show circuits of these types.
gain (hence the alternative title of Note that the 'offset' circuit of
'voltage follower'). . Figure 12 can be used with supplies
Figure 6 shows a simple self in the range 16V to 20V only, while
biasing (via RV1) source follower; the hybrid circuit of Figure 13 can
RV1 is used to set a quiescent R2 be used with any supply in the 12V
volt-drop of 5V6. The circuit's actual to 20V range. Both circuits give a
input-to-output voltage gain is 0.95. voltage gain of 21 dB, a ±3dB band
A degree of bootstrapping is width of 15Hz to 250kHz, and an
applied to R3 and increases its effec input impedance of 2M2. Figure 5. Basic JFET
tive impedance; the circuit's actual 'constant-current' biasing
Figure 6. Self-biasing
input impedance is 1O M shunted by DC VOLTMETERS source-follower. Zin= 10M. system.
10pF, i.e., it is 10M at very low fre
quencies, falling to 1M O at about Figure 14
16kHz and 1O Ok at 160kHz, etc. shows a JFET +12 to +20V +12 to +20V
Figure 7 shows a source follow used to make a
R1 R1
er with offset gate biasing. Overall very simple and 220k RS I 220k
12k
voltage gain is about 0.95. C2 is a basic three In--!.......,, ___ _, I
bootstrapping capacitor and raises range DC volt , ..." -,.._ 03
the input impedance to 44M, shunt meter with a C1 - - - T .... 1--~, 12 N3904 10--1~~---' +~I
ed by 10pF. maximum FSD 220n C1 + 10"
~-... out 2200 t----flll--...
plus Fbiigpuorlea r8) ssohuorwces afo lhloywbreidr. (OJFfEfsTe t Ose.SnVs itaivnitdy aonf 12R02k 01N1 4148 ~I R6 12R02k 1Cµ20 Out
biasing is applied via R1-R2, and input imped 02 ~6k8
constant-current generator Q2 acts ance of 11M1. 1N4148 ov
as a very high-impedance source Here, R6-RV2
load, giving the circuit an overall and R7 form a Figure 7. Source follower with
Figure 8. Hybrid source follower. Zin = SOOM. offset biasing. Zin = 44M.
voltage gain of 0.99. C2 bootstraps potential divider
R3's effective impedance up to across the 12V
1O OOM, which is shunted by the supply and - if the R7-RV2 junction I point - sets the top of R6 at +8V used as a source follower, with its
JFET's gate impedance; the input is used as the circuit's zero-voltage and the bottom of R7 at -4V. Q1 is gate grounded via the R1 to R4 net-
impedance of the complete circuit is
500M, shunted by 1O pF.
Note then if the high effective
value of input impedance of this cir
cuit is to be maintained, the output Honey, I
must either be taken to external
loads via an additional emitter fol
lower stage (as shown dotted in the shrunk the
diagram) or must be taken only to
fairly high impedance loads.
COMPUTE Rf
COMMON SOURCE
AMPLIFIERS
Figure 9 shows a simple self
biasing common source amplifier; PicStics are like BASIC
RV1 is used to set a quiescent 5V6 Stamps® on steroids.
across R3. The RV1-R2 biasing net
They have more speed,
work is AC-decoupled via C2, and
more parallel 1/0, more
the circuit gives a voltage gain of
21dB (= x12), and has a ±3dB fre code and data space, and
quency response that spans 15Hz to more neat features like a
250kHz and an input impedance of real-time clock, 12-bit
2M2 shunted by SOpF. (This high ADC, and 12-bit DAG.
shunt value is due to Miller feed .
back, which multiplies the JFET's
www.m1cr
effective gate-~o-drain capacitance
by the circuit's x12 Av value.)
Figure 10 shows a simple self
biasing headphone amplifier that
Micr~om int.
can be used with headphone inc www.levylatham.com
~
impedances of 1k O or greater. It has
a built-in volume control (RV1 ), has PRIVATE MARKETERS OF US. GOVERNMENT MILITARY SURPLUS ASSETS
Write In 150 on Reader Service Card. Write In 147 on Reader Service Card. JaM 2000 31
+12to +20V ~
+16to+20V I On~
SW.!
C3- + 01
R1 2N3819
R3
120k
10M RV2
2k7 +
C1 R2 (Set ,-
+-2-210n1 --"I'----' In 1MO zero) 1 81
Out In 112V
R1
2M2 C2 R2 11R11k
22µ 22k
ov ov
R7
ov 1k5
ov
Figure 12. Common-source Figure 14. Simple three-range
Figure 9. Simple self-biasing amplifier with offset gate biasing. DC voltmeter.
common-source amplifier.
ly on the meter. low-drift version of the JFET volt
R1 to R3 form a meter. Q1 and Q2 are wired as a
range multiplier network differential amplifier, so any drift
R4
12k that - when RV1 is cor occurring on one side of the circuit
C1
rectly adjusted - gives is automatically countered by a simi
220n
Q1 In +--1........,---+.i FSD ranges of 0.5V, 5V, lar drift on the other side, and
2N3819 and 50V. R4 protects good stability is obtained. The cir
Q1 's gate against dam cuit uses the 'bridge' principle, with
age if excessive input Q1-R5 forming one side of the
+
R1 C2 R1 01 voltage is applied to the bridge and Q2-R6 forming the
2M2 471J 2M2 1N4148
circuit. other. Q1 and Q2 should ideally be
02
ov 1N4148 To use the Figure 14 a matched pair of JFETs, with loss
circuit, first trim RV2 to values matched within 10%. The cir
Figure 10. Simple headphone give zero meter reading cuit is set up in the same way as
amplifier. Figure 13. 'Hybrid' common-source in the absence of an that of Figure 14.
amplifier.
input voltage, and then
connect an accurate MISCELLANEOUS
work and is offset biased by tak 0.5V DC to the input and trim RV1 JFET CIRCUITS
ing its source to -4V via RS; it con to give a precise full-scale meter
sumes about 1m A of drain cur reading. Repeat these adjustments To conclude this month's arti
rent. until consistent zero and full-scale cle, Figures 16 to 19 show a miscel
In Figure 14, R6-RV2 and Q1- readings are obtained; the unit is laneous collection of useful JFET cir
R5 act as a Wheatstone bridge then ready for use. cuits. The Figure 16 design is that
network, and RV2 is adjusted so In practice, this very simple cir of a very-low-frequency (VLF)
that the bridge is balanced and cuit tends to drift with variations in astable or free-running multivibrator;
zero current flows in the meter in supply voltage and temperature, its on and off periods are controlled
the absence of an input voltage at and fairly frequent trimming of the by C1-R4 and C2-R3, and R3 and R4
ov
Q1 gate. Any voltage applied to zero control is needed. Drift can be can have values up to 10M.
Q 1 gate then drives the bridge greatly reduced by using a zener With the values shown, the cir
Figure 11. General-purpose
out of balance by a proportional stabilized 12V supply. cuit cycles at a rate of once per 20
add-on pre-amplifier. .
amount, which can be read direct- Figure 15 shows an improved seconds, i.e., at a frequency of
0.05Hz; start button S1 must be
held closed for at least one second
to initiate the astable action.
Figure 17 shows - . in basic form
- how a JFET and a 741 op-amp
can be used to make a voltage-con
trolled amplifier/attenuato(. The op
amp is used in the inverting mode,
with its voltage gain set by the
R2/R3 ratio, and R1 and the JFET
are used as a voltage-controlled
input attenuator.
When a large negative control
voltage is fed to Q1 gate, the JFET
acts like a near-infinite resistance
and causes zero signal attenuation,
so the circuit gives high overall gain
but, when the gate bias is zero, the
FET acts like a low resistance and
causes heavy signal attenuation, so
the circuit gives an overall signal
into a sophisticated storage scope AND spectrum humidity & light sensors, door position, etc. scope and DVM - stand loss.
Intermediate values of signal
analyzer AND multimeter. Display simultaneously Record for 365/24 without a PC even if power alone or plugs into your PC
attenuation and overall gain or loss
on large screen! 100MS/s 8-bit or 1.2MS/s 12-bit or fails. Monitor 30 sensors 400 yds away. With for display, store-to-disk,
can be obtained by varying the con
333kS/sversions.Greatforschools,testdepts,etc. cables and easy software. Remote audio printing in color. Inputs to
trol voltage value.
Input to Excel! LabView/NTdriversincluded. alarm. UseTC-08formostthermocouples. 100V, trigger, backlit LCD.
Figure 18 shows how this volt
age-controlled attenuator technique
can be used to make a 'constant
volume' amplifier that produces an
output signal level change of only
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varied over a 40dB range (from
32 J.- 2000/Nuts & Volts Magazine Write In 146 on Reader Service Card.
3mV to 300mV RMS).
+9 to +12V On
The circuit can
accept input signal I SW2.
s1
levels up to a maxi Start +
mum of SOOmV RMS
R3
01 and R4 are wired
10M
in series to form a Out Figure 15. +
voltage-controlled Low-drift R2 e1i
attenuator that con 2N38Q119 three-range In 1MO 12·18V 1
DC
trols the input signal
voltmeter. R1 RV2 (Set
level to common emit 111k *=See text
10k zero)
ter amplifier 02, ov ov av
which has its output RB
buffered via emitter Figure 16. VLF astable multivibrator. 33k
follower 03.
03's output is used to gener
ate (via C5-R9-D1-D2-C4-R5) a DC R3 +12to +20V
control voltage that is fed back to R1
01 's gate, thus forming a DC Signal 100k
negative-feedback loop that auto in --./Vv----./\/1~-+-1
matically adjusts the overall volt
-ve--4..i
age gain so that the output signal
level tends to remain constant as Control
voltage
the input signal level is varied, as
follows. ov
When a very small input sig
nal is applied to the circuit, 03's Figure 17. Voltage<ontrolled
output signal is also small, so neg amplifier/a ttenuator. + cs
ligible DC control voltage is fed to 1~
01 's gate; Q1 thus acts as a low wave output with a peak amplitude
resistance under this condition, so equal to that of the DC input volt 1N4148 2k2
almost the full input signal is age.
applied to 02 base, and the circuit In this case, 01 acts like an Figure 18. Constant-volume amplifier.
gives high overall gain. electronic switch that is wired in
When a large input signal is series with R1 and is gated on and
applied to the circuit, Q3's output off at a 1k Hz rate via the 02-Q3 -4V5to-9V
R1
signal tends to be large, so a large astable circuit, thus giving the DC-to
DC negative control voltage is fed to AC conversion. Note that O1 ' s gate + 100k R6 R7
39k 39k
01 's gate; 01 thus acts as a high d rive signal amplitude can be varied C1
10µ
resistance under this condition, so via RV1; if too large a drive is used,
only a small part of the input signal Q1 's gate-to-source junction starts d.c. ~ +
is fed to Q2's base, and the circuit to avalanche, causing a small spike siy~al a.le. '
gives low overall gain. voltage to break through the drain
signal
Thus, the output level stays and give an output even when no out
fairly constant over a wide range of DC input is present.
input signal levels; this characteris To prevent this, connect a DC
tic is useful in cassette recorders, input and then trim RV1 until the
intercoms, and telephone ampli output is just on the verge of Figure 19. DC-to-AC converter or 'chopper' circuit.
fiers, etc. decreasing; once set up in this way,
Finally, Figure 19 shows a JFET the circuit can be reliably used to
used to make a DC-to-AC converter chop voltages as small as a fraction
Next time, Ray looks at practical MOSFET and CMOS circuits.
or 'chopper' that produces a square- of a millivolt. NV
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Write In 149 on Reader Service Card. Nuts & Volts Magazine/J- 2000 33