Power Trade-offs and Low Power in Analog CMOS ICs

235 Pages·2002·9.63 MB·English

by  Mihai A.T. Sanduleanu

POWER TRADE-OFFS AND LOW-POWER IN ANALOG CMOS ICs
THE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND
COMPUTER SCIENCE
ANALOG CIRCUITS AND SIGNAL PROCESSING
Consulting Editor: Mohammed Ismail. Ohio State University
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POWER TRADE-OFFS
AND LOW-POWER
IN ANALOG CMOS ICs
by
Mihai A.T. Sanduleanu
Philips Research, Eindhoven, The Netherlands
and
Ed A.J.M. van Tuijl
Philips Research, Eindhoven, The Netherlands
KLUWER ACADEMIC PUBLISHERS
NEW YORK,BOSTON, DORDRECHT, LONDON, MOSCOW
eBookISBN: 0-306-48140-5
Print ISBN: 0-7923-7642-0
©2003 Kluwer Academic Publishers
NewYork, Boston, Dordrecht, London, Moscow
Print ©2002 Kluwer Academic Publishers
Dordrecht
All rights reserved
No part of this eBook maybe reproducedor transmitted inanyform or byanymeans,electronic
mechanical, recording, or otherwise, without written consent from the Publisher
Created in the United States of America
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v
Contents
List of figures ix
List of tables xiii
Selected Symbols and Abbreviations xv
Foreword xvii
Acknowledgements xix
1.Introduction 1
1.1Motivation 1
1.2Problem definition 2
1.3Scope and outline 3
References 8
2.Power considerations in sub-micron digital CMOS 9
2.1Introduction 9
2.2Fundamental limits 10
2.3From fundamental limits to practical limits of power. An
architecture level approach 12
2.4S/N ratio and power in fixed point applications 18
2.5Adders and computational power 19
2.6Ways to low-power in digital 23
2.7Example of a digital video filter 25
2.8Conclusions 28
References 29
3.Power considerations in sub-micron analog CMOS 31
3.1Introduction 31
3.2Process tuning towards digital needs. Consequences on analog 32
vi
3.3Fundamental limits 36
3.4From fundamental limits to practical limits of power. Noise
related power 38
3.5From fundamental limits to practical limits of power. Mismatch
related power 56
3.6Power estimations in continuous time filters 60
3.7 Conclusions 66
References 67
4.Gm-C integrators for low-power and low voltage applications. A
gaussian polyphase filter for mobile transceivers in 0.35 CMOS 69
4.1Introduction 69
4.2Large swing and high linearity transconductor 69
4.3Low voltage current Gm-C integrator with high power efficiency
78
4.4Low-power luminance video filter. Noise driven power 83
4.5Low-power, gaussian, polyphase filter for mobile transceivers.
Matching driven power 87
4.6 Conclusions 97
References 99
5.Chopping: a technique for noise and offset reduction 101
5.1Introduction 101
5.2Ways to reduce offset and 1/f noise 102
5.3Chopping seen as a modulation technique 105
5.4Noise modulation 106
5.5 Chopped amplifiers and offset reduction 108
5.6Low-power low-voltage chopped transconductance amplifier for
noise and offset reduction. Chopping at high frequency 109
5.7 A low-power bandgap voltage reference 119
vii
5.8 Conclusions 124
References 125
6.Low-noise, low residual offset, chopped amplifiers for high-end
applications 127
6.1Introduction 127
6.2Low-pass filtering in a digital audio system. Application specific
constraints 128
6.3The gain stage 130
6.4A low noise, low residual offset, chopped amplifier in 0.8mm
CMOS 132
6.5A low noise, low residual offset, chopped amplifier in 0.5mm
CMOS 142
6.6 Conclusions 150
References 152
7.A 16-bit D/A interface with Sinc approximated semidigital
reconstruction filter 153
7.1Introduction 153
7.2Bitstream D/A conversion system with time-discrete filtering 154
7.3S-D modulators and noise shaping 155
7.4. Semidigital FIR filter principles 158
7.5.Semidigital FIR filter design 160
7.6Noise properties of the D/A interface 168
7.7 Realisation 176
7.8Experimental results 180
7.9Interpolative D/A converter with Sinc approximation in the time
domain 181
7.10.Conclusions 184
References 186
viii
8. Conclusions 187
8.1Summary 187
8.2 Conclusions 189
8.3Original contributions 192
8.4Recommendations for further research 193
APPENDIX 1 195
APPENDIX 2 199
APPENDIX 3 203
INDEX 207
ix
List of Figures
2.1: The levels of abstraction for powerconsiderations 9
2.2: Thermodynamic limit 11
2.3: Fundamental limits of power in digital 12
2.4: Energy as a function of S/N for a generic DSP 15
2.5: FIR digital filter 15
2.6: IIR digital filter (direct form 1) 16
2.7: IIR digital filter (direct form 2) 17
2.8: Circuit diagram of a full adder FA 19
2.9: RCA m bits adder 20
2.10: Cascade RCA for adding m words of B bits 21
2.11: Chain (a) vs. tree (b) implementation of adders 22
2.12: The delay of a simple inverter 25
2.13: The LP prototype after scaling 26
2.14: Multiplication by hardwiring 26
2.15: Example of a FIR digital video filter 27
3.1: Output resistance and the drain current in processes 33
3.2: Matching in for processes 34
3.3: Analog processor 36
3.4: Fundamental power limits as a function of S/N 37
3.5: Power spectral densities of the thermal noise 38
3.6: Voltage amplifier with feedback 41
3.7: Voltage amplifier with differential stage and feedback 43
3.8: OTA with active load 44
3.9: Feedback amplifier with OTA 45
3.10: Current amplifier 46
3.11: Frequency transfer of the current amplifier 47
3.12: Charge summing amplifier with S/H 49
3.13: Switched capacitor amplifier 50
3.14: Circuit for settling time computation 52
3.15: SI memory cell 53
3.16: SI non-inverting amplifier (damped integrator) 54
3.17: State space representation of a filter 60
3.18: Transconductors with degeneration resistors 63
4.1: Gm core diagram 70
4.2: Gm fine tuning 72
4.3: Gm coarse tuning for different aspect ratios of MN12(13) 72
4.4: THD for Gm_TUNE=0 73
4.5: THD for Gm_TUNE=3V 74
4.6: Frequency response of the integrator 75
4.7: The noise excess factor of the transconductor 75
4.8: Circuit diagram of the transconductor 77
4.9: Continuous time, current, Gm-C integrator 78
4.10: Frequency transfer of the integrator 79
4.11: Linearized integrator 82