Power Scaling in High Speed Analog-to-Digital Converters using Photonic Time Stretch Technique

0.46 MB·English

by  Shalabh Gupta

Power Scaling in High Speed
Analog-to-Digital Converters using
Photonic Time Stretch Technique
ShalabhGupta1, ,GeorgeC.Valley2,RobertH.Walden2,
9 ∗
andBahramJalali1
0
0 1DepartmentofElectricalEngineering,UniversityofCalifornia,LosAngeles,CA90095
2
2TheAerospaceCorporation,ElSegundo,CA90245
n
a ∗[email protected]
J

9
1 Abstract: Factorsthatcontributetotherapidincreaseinpowerdissipation
asafunctionofinputbandwidthinhighspeedelectronicAnalog-to-Digital

] Converters(ADCs) are discussed. We find that the figure of merit (FOM),
t
e defined as the energyrequired per conversionstep, increases linearly with
d
bandwidthforhigh-speedADCswithmoderatetohighresolution,orequiv-
-
s alently,thepowerdissipationincreasesquadratically.Itisshownthatbyuse
n
ofphotonictime-stretchtechnique,itispossibletohaveADCsinwhichthis
i
. FOM remains constant for up to 10 GHz input RF frequency. Using this
s
c technique,itisalsopossibletoovercomethebarriertoachievinghighres-
si olution caused by clock jitter and speed limitations of electronics in such
y ADCs.
h
Use ofopticsis activelybeingpursuedforreducingpowerdissipationand
p
achieving higher data-rates for board-level and chip-level serial commu-
[
nication links. In the same manner,we expect that optics will also help in

1 reducing power dissipation in high-speed ADCs in addition to providing
v
broaderbandwidths.
7
6 © 2009 OpticalSocietyofAmerica
7
2 OCIScodes:(060.0060)Fiberopticsandopticalcommunications;(070.1170)Analogoptical
. signalprocessing;(260.2030)Dispersion.
1
0
9
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1. Introduction
Increasedbandwidthdemandsfrominternetbackboneshaveledresearcherstotarget100Gbit/s
and higher data rates per wavelength division multiplexing (WDM) channel using spectrally
efficient,multilevelmodulationformats[1].Demodulationofsuchsignalsrequiresanalog-to-
digital converters (ADCs) with very high performance and resolution. Such ADCs are also
crucialfordefenseapplicationssuchasradarsandforwide-bandwidthlaboratoryinstruments
suchasoscilloscopesandvectorspectrumanalyzers.
Fig. 1. Energy per conversion step versus performance for state-of-the-art high-speed
analog-to-digitalconverterswithmoderatetohighresolution(from2002topresent).FOM
roughly increases linearly, i.e., power dissipation increases quadratically with frequency
(i.e.P(cid:181) f2,asshownintheinset).
WhilecontinuedscalingofCMOStechnology[2]hasimproveddigitalcircuitstremendously
intermsofperformance,powerefficiencyandcost,analogcircuits(andADCs)havenotreally
keptpace.Eventhoughthebandwidthofananalogcircuitimproveswithtechnologyscaling,
sincesmallerdevicesrunfaster,thankstoreducedcapacitances,powerdissipationforthesame
functionalitydoesnotalwaysscalebecauseoflowerintrinsicgainsinshorterchannelCMOS
transistors [3]. In fact, most improvements in power efficiency of analog circuits can be at-
tributedtoarchitecturalimprovementsandscaledvoltages,ratherthanreducedcapacitancesin
CMOSdevices.
In ADCs, analog full-scale voltage cannot be reduced arbitrarily because of the thermal
(kT/C) noise limitations. As a result, while technology scaling has not directly resulted in
decreasedanalogpowerdissipation,powerreductionandincreasedspeedofdigitalcircuitshas
allowed extensive use of digital correction and calibration techniques,which have led to im-
provementinperformance.Themostcommonlyusedfigureofmerit(FOM)forADCefficiency
istheenergyrequiredperconversionstep,
P
diss
FOM= , (1)
2ENOB 2 ERBW
× ×
where, P is the power dissipation of the ADC, ENOB is the effective number of bits
diss
and ERBW is the effective resolution bandwidth of the ADC [4]. ERBW is defined as the
frequency at which the signal-to-noise-and-distortionratio (SNDR) of the ADC degrades by
3-dBascomparedtoitslowfrequencyvalue.Fig.1showstheenergyperconversionstepasa
functionofERBWforADCsfrom2002tothepresent.WhileFig.1lumpstogetherADCsfor
5or6differentelectronictechnologies,itisevidentfromtheplotthatabove100-MHz,energy
perconversionstepforthebestADCsincreasesrapidlywithbandwidth.Similartrendisfound
fromthedataobtainedin[5]forCMOStechnologiesforhighspeed(>100MHzERBW)and
moderate to high (>6 ENOB) resolution ADCs. In reference [6], Murmannfinds that power
theefficiencyoftheADCshasimprovedbyafactorof2everytwoyears,thankstotechnology
andpowersupplyscaling.However,thedatain[5]confirmsthatthistrendisnotobservedfor
highspeedADCswithmoderatetohighresolution.
In this paper we estimate that the power dissipation in such high speed ADCs increases
approximatelyas f2foraconstantresolution,where f isthesamplingfrequencywithNyquist
s s
Fig.2.ConceptualdiagramofaphotonicTime-StretchAnalog-to-DigitalConverterwith
astretchfactorof4.Thehigh-speedRFsignaltobedigitizedissegmentedintomultiple
wavelengthchannelsandtime.Allsegmentsarethentimestretchedanddigitizedbymuch
slowerbackenddigitizers.Digitizedsignalsarerearrangedandcombineddigitallytoobtain
thedigitalrepresentationoftheoriginalRFsignal.
ratesampling.Ontheotherhand,ifthephotonictime-stretchtechnologyisused[7,8,9],we
show that one can obtain linear power scaling of future ADCs to much higher frequencies.
The conceptual diagram of a Time-Stretch Analog-to-DigitalConverter (TS-ADC) is shown
in Fig. 2. The time-stretch technique also allows breaking through the so-called walls in the
ENOB-bandwidthplanecausedbycomparatorambiguityandtimingjitter[4,10].
Inthispaper,firstwediscussthefundamentallimitsonnoiseandpowerdissipationinADCs.
Second, we discuss frequencyscaling in digital circuits and show why similar trendsare ob-
servedin ADCs. Third,we show thatthe photonictime-stretchtechniquecanpush thelinear
scalingofpowerdissipationversussamplingfrequencyintheADCswellintotheGHzband.
Finally,wecomparethepowerdissipationinhighspeedADCswithandwithouttheuseofthe
photonictime-stretchtechnique.
1.1. FundamentallimitstopowerdissipationinADCs
An analog-to-digitalconverter consists of two main operationalstages. First, the sample and
holdstage(S&H)samplestheanalogsignalonacapacitorthroughaswitchatperiodicinter-
vals of time. Second, the quantization stage which converts the sampled analog signal using
comparatorstodigital(binary)outputs.Dependingonthearchitecture,therecanbeaseriesof
these two stages in a specific ADC design.In addition,clock generationcircuitryis required
toprovideclockswithdifferentphasesanddutycyclestodifferentsetsofswitchessothatall
operationsin the ADC are synchronized.Finally,thereare referencebuffersthatactas accu-
ratevoltagesourceswithverylowoutputimpedances.Additionally,modernADCsusedigital
circuitryextensivelyforcorrectionandcalibrationinpost-processing,whichcanalsoconsume
asignificantfractionofthetotalpower.
Inthesampleandholdstage,theanalogsignalandthethermalnoisegeneratedintheswitch
aresampledontoacapacitorwithcapacitanceC.Thesamplednoisevoltagehasameansquared
valueofkT/C,where,kistheBoltzmannconstantandT istheambienttemperature.Notethat
the total magnitude of thermal noise is sampling frequencyindependent.This is because the
thermalnoiseatallfrequenciesisfoldedbackintotheNyquistbandwidthinasampledsystem.
IfthethermalnoiseisthedominantnoisesourceandV isthefullscalevoltage,weobtainthe
FS
signal-to-noiseratioanddissipatedpoweras:
V2
SNR(cid:181) FS , P (cid:181) CV2 f (2)
kT/C diss FS s
P (cid:181) kT.f .SNR (3)
diss s
⇒
Therefore,foragivensignalpower(orV ),thermal(kT/C)noiseplacesalowerlimitonthe
FS
capacitancethatcanbeusedinthesampleandholdstage.Onanaverage,biascurrentsrequired
inthebufferamplifierstochargethesamplingcapacitorswiththesignalorthereferencevoltage
are directly proportionalto the value ofC and the charging time, fundamentallylimiting the
power dissipation of an ADC, as observed in (3). This limitation can be written in terms of
the effective number of bits of the ADC by substituting the standard relation for ENOB as a
functionofSNR[4,11]:
Pdiss(cid:181) kT.fs.10(6.02×ENOB+1.76)/10. (4)
Inpracticalcircuits,thepowerdissipationisatleast3to4ordersofmagnitudeshigherthan
thisvalue[12]sincetheindividualcomponentssuchasvoltagebuffers,opamps,comparators,
andclocksourceshavetosatisfyrequirementsoflownoise,highlinearity,highspeedandhigh
precisionsettling.CurrentsinallthesecircuitsscaleproportionallywiththecapacitanceCfor
afixedsamplingfrequency.
Equation (4) suggests that ADC power dissipation should scale linearly with f . However,
s
fromthetrendseeninFig.1andin[13],andfromthediscussioninthefollowingsubsection,
itbecomesclearthatinreality,theenergyperconversionstepscalesroughlyas f ,i.e.,power
s
dissipationisproportionalto f2 inhigh-speedADCs.
s
1.2. PowerScalinginDigitalCircuits
Powerdissipationindigitalcircuits,whichuntilrecentlyhasbeendominatedbythedynamic
powerrequiredforswitchingtransistors,isproportionaltoCV2f,whereCistheaveragenode
capacitance,V is the supply voltage and f is the clock frequency[14]. To run the circuits at
fastspeeds,highswitchingcurrentsarerequiredtochargeordischargethenodecapacitances
quickly,whichdemandsahighersupplyvoltage.TheminimumoperatingvoltageV atwhicha
digitalcircuitcanoperatecorrectlyisroughlyproportionalto√f forawiderangeoffrequen-
ciesorvoltages[14].Thisimpliesthatifthefrequencyofoperationisreducedbyafactora ,
therequiredpowerdecreasesbyfactora 2.Asaresult,theenergy-delayproductforperforming
anoperationisroughlyconstantoverawiderangeofoperatingfrequenciesindigitalcircuits
[14].Thissimpleobservationimpliesthatwhenmoredelayisallowedforasetofoperations,
lessenergyisrequiredtoperformthem.Thisimplicationisthereasonthatthedigitalworldis
movingtowardsarchitecturesexploitingparallelism[15],andthesametrendisfoundinhigh
samplerateADCsandreal-timedigitaloscilloscopes[16,17,18,19,20].Inthispaper,wefind
that the time-stretch technique, which uses the same approachof parallelism to digitize very
highbandwidthsignals,canalsohelpinreducingpowerdissipationinhighspeedADCs.
1.3. PowerScalinginAnalog-to-DigitalConverters
Speed considerations: In deriving the expression P (cid:181) kT.f .SNR, it was assumed that to
diss s
increase the sampling frequency,the bias currents need to be increased linearly to charge up
the capacitors fast with no limitation being posed by the transistor response time. In reality,
theunitygainfrequency f ofthetransistorsshouldalsobeincreasedlinearlywith f because
T s
theoperationalamplifier(opamp)outputsdrivingthecapacitorshaveshortertimetostabilize
beforequantizationbegins.
Fig.3.SchematicofatimeinterleavedADC.
IncreasingthebiascurrentinaCMOStransistorcanbedoneintwoways.Inthefirstmethod,
the device size is keptconstantand the bias current(I ) is increasedby increasingoverdrive
D
voltage(V ).Thisincreasesthe unitygainfrequency f (cid:181) √I ,asforadevicewitha fixed
OD T D
size, transconductance g (cid:181) √I and f (cid:181) g . However it also results in a lower output re-
m D T m
sistance r which is proportionalto 1/I and hence a lower intrinsic gain of g r (cid:181) 1/I .
o D m o D
p
LowergainresultsinhighergainerrorsintheopampsreducingaccuracyoftheADC.
In the second method, overdrive voltages are kept constant and only the transistor widths
are increased linearly for a proportionalincrease in current. In this case, the intrinsic gain is
maintained,but f doesnotincrease,resultinginanincompletesettlingoftheopampoutputs
T
forhighersamplingfrequencies.
In bothcases, we find thatjustbyscaling currentsproportionally,onecannotfulfillthere-
quirementsoffaster responsetime while maintainingthe same linearity(andresolution).For
quantization process, the voltage comparatorsalso need to switch faster to avoid comparator
ambiguity [4]. The same arguments, as discussed above, indicate that increasing drive cur-
rentslinearlywithfrequencyincomparatorsisagainnotasolutionforachievingtherequired
comparatorspeeds.ThesefactssuggestthatpowerdissipationinADCsshouldincreasemore
rapidlywithfrequency,followingasomewhatsimilartrendasindigitalcircuits.Thisfrequency
scalingtrend,asshowninFig.1,isfoundnotonlyinCMOStechnologies,butisalsocentral
toothertechnologieslikeSiGe,GaAsandInPwhichhavetraditionallybeenusedforveryhigh
speedADCs.
To overcome these issues in frequency scaling, new ADC architectures employing paral-
lelism must be used as in case of digital circuits [14]. In the time-interleaved architecture,
which is a parallelADC architecturesuch as the oneshown in Fig. 3, multiplesub-sampling
ADCsareusedinparallel,tosamplethesignalatdifferentinstantsoftimewithinafullsam-
pling clock cycle [16, 17, 18]. The outputs of these “sub-ADCs” are combined in the digital
domainandpostprocessingisperformedtosuppressdistortionscausedbytimingerrors,gain
mismatchesandDCoffsets.Thefront-endofthetimeinterleavedarchitecturecanhaveasingle
S&H block [16] feeding all sub-ADCs, or a separate S&H block correspondingto each sub-
ADC [17], or a combinationof the these two approaches[18]. In the first and the third case,
scalabilitytohighsamplingfrequenciesandtolargesub-ADCnumbersisstillachallenge,and
samepowerconsiderations,asdiscussedabovefortheADCs,applytothefront-endcircuitry.
Thesecondarchitecture(discussedin[17])canpotentiallybescaledtohavehighersampling
rates,buttimingjitterandresidualtimingoffsets,whicharediscussedinthenextsection,limit
theADCresolution.Also,thisarchitecturerequiresapredrivertodrivealargecapacitiveload
ofS&Hblockswhichcanlimitthebandwidthandaddsignificantpowerdissipation.
Fig. 4. Sampling a signal withand without time-stretch. When time-stretch technique is
used,thenoiseduetoclockjitterbecomesinsignificant,andnoiseaddedbythelaserjitter
dominates,whichistypicallymuchlessthantheelectronicclockjitter(Vn representsthe
noisevoltage).
1.4. NoiseduetoApertureJitter
In high speed ADCs, aperture jitter (or uncertainty) is a significant source of noise [4] (as
showninFig.4),whichiscausedbyjitterinthesamplingclock.Aperturejitternoiseissignal
frequencydependentwhichseverelydegradestheSNRofmoderatetohighfrequencysignals.
ThejitterlimitedSNRforanrmstimingjittert isgivenby[4,21]:
j
SNR = 20log(2pt f ). (5)
jitter j signal
−
Most of the aperturejitter noise is added by the jitter in the sampling clocks generated by
the clock sources. In the time interleaved architectureused in [17], timing errorsin clocking
differentsub-ADCsalsoaddthesameeffectasjitterandlimittheachievableSNR.Forexample,
the 20GS/sADCreportedin[17] showsa resolutionof6.5effectivebitsatlowfrequencies,
buttheresolutiondropsto4.6effectivebitsfor6-GHzRFsignalbecauseof aneffectiverms
sampling jitter of 0.7-ps. In anotherexample [21], an rms jitter of 250-fsis shown to reduce
theeffectiveresolutionofa14-bitADCtoabout11.2effectivebitsfora230-MHzRFsignal.
As discussed in the next section, the time-stretch ADC technique uses optical processing to
overcometheselimitations,inadditiontoachievingsignificantpowersavings.
2. TimeStretchAnalog-to-DigitalConverter
Inatime-stretchADC(TS-ADC),theeffectivebandwidthandfrequencyoftheRFsignaltobe
digitizediscompressedbystretchingthesignalintime[7,8,9],therebyreducingthebandwidth
of the backend electronic digitizer required to capture the original signal. Fig. 5 shows the
fundamentalprocess of time-stretch. To do so, the RF signal is modulated over a long pulse
of a linearly chirped optical carrier obtained from a super-continuum source (which can be
a femto-secondmode locked fiber laser). Propagationthrougha dispersive medium stretches
the modulated pulse in time, resulting in a “time-stretched” replica of the originalRF signal
Fig. 5. Schematicdiagram showing physics of photonic time-stretchpreprocessing tech-
nique. TheRFsignal ismodulated over alinearlychirpedoptical pulseobtained bydis-
persingasuper-continuum(SC)pulse.Signalobtainedatthephoto-detectoroutput,after
propagationthroughtheseconddispersionfiber,isatime-stretchedreplicaoftheoriginal
RFsignal.
afterphotodetection.ThemagnificationorthestretchratioM isgivenby(D /D +1),where
2 1
D and D are the dispersion values of dispersion fibers DCF-1 and DCF-2, respectively.To
1 2
achievecontinuousoperation,theopticalspectrumissegmentedintomultiplechannelsusinga
wavelengthdivisionmultiplexing(WDM)filter.Time-stretchedsignalsfromdifferentchannels
aredigitizedbyseparateelectronicdigitizersandcombinedtogetherindigitaldomain.Fig.2
illustratesonerealizationoftheTS-ADCsystemthatcanbeusedtostretchthesignalbyupto
afactoroffour,andrequiresfourchannelstocapturethewholesignalcontinually.
As illustrated in Fig. 4, stretching the signal in time using optical preprocessing reduces
theeffectivesignalfrequencyseenbytheS&HblockbythestretchfactorM.Asaresult,the
noise added to the system due to clock jitter is scaled downby M2. For example,if a stretch
factor of 10 is used in a TS-ADC, the clock jitter limited noise can be lowered by up to 20-
dB comparedto a conventionalADC. We note thatthe timingjitter of the mode-lockedfiber
laser, which is used for generatingchirped pulses in the TS-ADC, still adds noise, but it can
bereducedtoverysmallvalueswithcarefuldesign.Forexample,alaserwith18-fsrmsjitter
has been reported in [22]. On the other hand, the best jitter performanceachieved by clocks
inelectronicdigitizersisoftheorderof200-fs[21].Inreference[23],thebestclockjitterof
180-fsisobservedforclockswithveryhighvoltageswings.However,suchvoltageswingsat
high speeds add very substantially to power dissipation, and make clock distribution almost
impossibleintime-interleavedADCs.
Intime-interleavedADCs,theclockjitterisgenerallymuchhigherasextensiveclockgen-
erationcircuitryisrequiredtogeneratemultipleclockswithveryprecisephasedelays.Addi-
tionally,evenafteradaptivealignmentandcalibration,thereisaresidualtimingmisalignment
between clocks going to different sub-ADCs. Stringent requirements on clock accuracy can
thusresultinasignificantpowerpenaltyinthetimeinterleavedADCs.
AsevidentfromFig.4,whenthetime-stretchtechniqueisused,theeffectivesamplingjitter
inthesystemcanbereduced,andcanbewrittenas
t = t 2 +(t 2 /M)2. (6)
j,effective q j,laser j,clock
This makes the time stretch architecture very well suited for high signal frequency appli-
cations where aperture jitter is the dominantsource of noise. Another key advantage of time
stretchingis thatnoneofthe electronicdigitizerssee the original,veryhighfrequencysignal
since thesignalfrequencyscalesdownuponstretching.Asa result,thepowerscaleslinearly
Fig.6.SchematicdiagramoftheTime-StretchADCforcontinuousoperation(MLL:Mode
LockedLaser;SC:Super-Continuum;PC:PolarizationController;DCF:DispersionCom-
pensatingFiber;MZM:Mach-ZehnderModulator;PD:Photodetector).
withsamplingfrequencyfortheADC.Inthenextsub-section,weconsideranexampletoshow
howtimestretchingcanbeveryusefulinthecontextofpowersavings.
2.1. PowercalculationsforaTime-StretchADC
The blockdiagramof a TS-ADC system forcontinuousoperationis shownin Fig. 6. We as-
sumethattherepetitionrateofopticalpulsesfromthemode-lockedlaser(MLL)is100-MHz.
Therefore,the timesegmentsthatneedto becapturedbyelectronicdigitizersare 10-nslong.
Usable optical bandwidth of 40-nm (i.e. 5-THz bandwidth in frequency at 1550-nm center
wavelength) can easily be obtained from a femto-second MLL, for example, the FFL1560-
MP laser from Precision Photonics, followed by a highly non-linear fiber [24]. For continu-
ous modulation of RF signal, these 40-nm pulses have to be stretched to 10-ns before they
aremodulatedusingMach-Zehndermodulator(MZM),whichrequires-250ps/nmdispersion
in DCF-1, corresponding to dispersion of about 15-km SSMF (standard single-mode fiber).
For the TS-ADC, dispersion compensation fibers (DCFs) are used because they have higher
dispersion-to-loss ratios compared to SSMF. Using a DCF, dispersion value of -250ps/nm is
achieved with a distributed loss of about 0.65-dB (as found in [25] and from measurements
in ourlab),to whichconnectorlossesareaddedseparately.Ifthestretch factoris M, thedis-
persionrequiredinDCF-2becomes(M 1) ( 250ps/nm),sinceM=(D /D +1),where
2 1
− × −
D and D are the dispersion values of DCF-1 and DCF-2, respectively. Also, we estimate
1 2
the losses in the Mach-Zehndermodulatorto be 4-dBand losses in WDM filter, polarization
controllerand connectorsto be an additional3-dB. Therefore,total loss in the optical link is
aboutM 0.65+4+3=(M 0.65+7)dB.Also we estimate thatthe powerat the inputof
× ×
each photodetector as 1 mW – which gives 58-dB shot noise limited SNR for 500-MHz RF
bandwidth,0.5modulationdepthand0.8A/Wphotodetectorresponsivity.ThenoiseandSNR
calculationsforanopticalsystemisshowninAppendixA.Sameorbetterthermalnoisefrom
electronicsandphotodetectorcaneasilybeachieved,resultinginbetterthan58-dBSNRwith
differentialoperation[26].BackendADCswith8-ENOB(i.e.50-dBSNDR)cannowbeused
toobtainsame8-bitresolution,astheadditionalnoiseiscompensatedbydifferentialoperation
[26].NoisecontributionduetolaserRIN(relativeintensitynoise)isunimportantasamodest
RINof-150-dByieldsanSNRof63-dBinsuchconditions.
The backenddigitizersare assumedto capturewaveformsata sample rate of1-GS/s, with
0.5-pJ/stepFOMand500-MHzNyquistbandwidthwith8-ENOB–resultingin125-mWpower
dissipation. These values are projected using the blue line in Fig. 7 obtained from observing
the linear dependence of ADC FOM on f for published ADCs, and using FOM of the best
s
Fig. 7. Projected FOM for a Time-Stretch ADC (red trace) and a time-interleaved ADC
(blueline)fordifferentsignalfrequencies.GreentraceshowsFOMifCFBGsareusedfor
dispersion,whichalsorepresentsatrendifopticalamplificationwereused.
reportedGS/s ADC [18]. For each opticalWDM channel,differentialandarcsine operations
areperformed[26,27],whichnotonlyimprovetheSNRby3-dBbutalsosuppressnon-linear
distortion due to electro-optic modulation and chromatic dispersion. However, this requires
that the number of backend digitizers and photo-detectorsare twice the stretch factor M (or
the number of optical channels). The electrical-to-opticalpower conversion efficiency of the
laserisassumedtobe20%andthepowerconsumedbyeachphotodetectorisestimatedtobe
50-mW.Thisincludesthepowerrequiredtobiasthephotodetectorandthepowerinthesubse-
quentamplifyingstagetobringthesignaltofullscalevoltageoftheelectronicdigitizer.Asa
proofofprinciple,atwochannel7-ENOBTS-ADCwith10-GHzRFbandwidthwasrecently
demonstrated[24],inwhichtheresolutionwasprimarilylimitedbythebackenddigitizer.This
is, to the bestknowledgeof the authors,a world record resolutionachievedin digitizationof
10-GHzbandwidthsignals.
Finally,thecombinationofchanneloutputsindigitaldomainrequiressignalprocessingand
memory. Even though CMOS scaling has made digital circuits highly power efficient, large
amount of digital data is generated, which requires significant power consumption in digital
post-processing. Digital power is estimated to be the same as the total power consumed in
backend electronic ADCs (as a similar trend is observed in [13]). Using these numbers with
1-mW input optical power at each photo-detector,the total optical and electrical powers can
becalculated.PowerscalingobtainedintheTS-ADCisplottedastheredcurveinFig.7.Itis
observedthattheFOMroughlystaysconstantupto5-GHzaspowerconsumptionofelectronics
dominatesatlowerfrequencies.
Forhigherfrequencysignals,longerdispersivefibersarerequiredtohavelargerstretchra-
tios,whichaddsignificantpowerpenaltyduetoopticallosses.OpticalamplificationusingEr-
bium doped fiber amplifiers, or distributed Raman amplification can be used to curtail these
losses and improve the overall power efficiency significantly while maintaining high SNR.
However,their discussion has beenavoided herefor simplicity.Furthermore,with lowerloss
dispersivemedia,suchaschirpedfiberBragggratings(CFBGs),linearpowerscalingtrendcan
continueto muchlargerbandwidths,as shown bythe greencurvein Fig. 7. Inthese calcula-
tions, the losses in CFBGs are assumed to be half of the DCFs, though in actual, the CFBG
losses are even lower [28]. However, the CFBGs can have a significant group delay ripple,
which mustbe reducedor correctedin highresolutionapplications.Since thereis practically