Power and area efficient reconfigurable delta sigma ADCs

172 Pages·2013·4.1 MB·English

Power and area efficient reconfigurable delta sigma ADCs
Citation for published version (APA):
Porrazzo, S. (2013). Power and area efficient reconfigurable delta sigma ADCs. [Phd Thesis 1 (Research TU/e /
Graduation TU/e), Electrical Engineering]. Technische Universiteit Eindhoven. https://doi.org/10.6100/IR761378
DOI:
10.6100/IR761378
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Published: 01/01/2013
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POWER AND AREA EFFICIENT

RECONFIGURABLE ∆Σ ADCS

Serena Porrazzo
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POWER AND AREA EFFICIENT
RECONFIGURABLE ∆Σ ADCS

PROEFSCHRIFT

ter verkrijging van de graad van doctor aan de
Technische Universiteit Eindhoven, op gezag van de
rector magnificus prof.dr.ir. C.J. van Duijn,
voor een commissie aangewezen door het College
voor Promoties, in het openbaar te verdedigen op
dinsdag 26 november 2013 om 16:00 uur

door

Serena Porrazzo

geboren te Como, Italië
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Dit proefschrift is goedgekeurd door de promotoren en de samenstelling van de
promotiecommissie is als volgt:

voorzitter: prof.dr.ir. J.H. Blom
1e promotor: prof.dr.ir. A.H.M. van Roermund
copromotor: dr.ir. E. Cantatore
leden: dr.ir. M. Mischi
prof.dr.ir. G. Gielen (Katholieke Universiteit Leuven)
prof.dr. K.A.A. Makinwa (TU Delft)
prof.dr.ir. C. Van Hoof (Katholieke Universiteit Leuven)
adviseur: dr. R.F. Yazicioglu (imec)

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TABLE OF CONTENTS
List of figures ............................................................................................. ix
List of tables ............................................................................................. xiii
List of abbreviations.................................................................................. xv
List of symbols ........................................................................................ xvii
1 Introduction............................................................................................... 1
1.1 Background ........................................................................................................... 2
1.1.1 Reconfigurability ......................................................................................... 4
1.1.2 Power-efficiency and area-efficiency ........................................................ 9
1.1.3 State-of-the-art reconfigurable ADCs .................................................... 12
1.2 Problem statement ............................................................................................. 16
1.3 Aim of the thesis ................................................................................................. 17
1.4 Scope of the thesis .............................................................................................. 17
1.5 Approach ............................................................................................................. 19
1.6 Original contributions ........................................................................................ 20
1.7 Outline of the thesis ........................................................................................... 21
2 Power-efficient reconfigurable ∆Σ modulators for autonomous
biomedical applications ..........................................................................23
2.1 ∆Σ modulation for reconfigurable and power-efficient high-resolution
ADCs ................................................................................................................... 24
2.2 ∆Σ ADCs: basics and topologies ...................................................................... 26
2.3 State-of-the-art reconfigurable ∆Σ modulators............................................... 30
2.4 Reconfigurable ∆ΣMs for biomedical applications ........................................ 32
2.5 Conclusion........................................................................................................... 33
3 Power optimal design of SC ∆Σ modulators for given resolution and
bandwidth ...............................................................................................35
3.1 Introduction ........................................................................................................ 36
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3.2 Power optimization method .............................................................................. 37
3.2.1 Global design methodology .................................................................... 38
3.2.2 Step 1 - Choosing OL, STF/NTF for each (N, B, OSR) .................... 42
3.2.3 Step 2 - Sizing of the sampling capacitors ............................................. 44
3.2.4 Step 3 - Power consumption estimation ................................................ 46
3.2.5 Static power ............................................................................................... 47
3.2.6 Dynamic power ........................................................................................ 58
3.2.7 Quantizer power ....................................................................................... 59
3.2.8 DWA Power ............................................................................................. 63
3.2.9 Total Power consumption ....................................................................... 65
3.2.10 Power optimization of a ∆ΣM for hearing aids application and
impact of design parameters on power consumption ......................... 66
3.2.11 Results of the power optimization procedure .................................... 76
3.3 Design techniques for power-efficient SC feed-forward ∆ΣMs ................... 77
3.3.1 Active addition .......................................................................................... 78
3.3.2 Passive addition ........................................................................................ 79
3.3.3 The summing SAR quantizer .................................................................. 80
3.4 Design examples ................................................................................................. 82
3.4.1 A 95dB DR 10-kHz SC ∆ΣM for digital hearing-aids application ..... 83
3.4.2 A 1.8-V 88dB DR ∆ΣM for digital hearing aids using a novel
summing SAR quantizer ......................................................................... 87
3.5 Conclusion........................................................................................................... 95
4 Power-efficient design of reconfigurable SC ∆ΣMs ................................97
4.1 Introduction ........................................................................................................ 98
4.2 Power efficient approach to reconfigurability ................................................. 99
4.2.1 Overview of the methodology .............................................................. 100
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4.2.2 Case study: design of a reconfigurable ∆ΣM for a biomedical
application set......................................................................................... 102
4.3 Circuit design techniques for power-efficient reconfigurable ∆ΣMs ......... 111
4.3.1 Modular C implementation ................................................................. 111
s,1
4.3.2 Programmable OTAs for power- and speed-scalability..................... 114
4.4 Design example: a 1-V 99-to-75 dB SNDR 256-to-16kHz reconfigurable
∆ΣM................................................................................................................... 116
4.5 Conclusion......................................................................................................... 128
5 Conclusions ........................................................................................... 131
References ................................................................................................ 135
Publications list ........................................................................................ 145
Summary .................................................................................................. 147
Curriculum Vitae...................................................................................... 151

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List of figures
Fig. 1. Conversion bandwidth versus SNDR performance of state-of-the-art
ADCs. ............................................................................................................... 6
Fig. 2. Power-efficiency versus SNDR performance of state-of-the-art ADCs. . 10
Fig. 3. Power-efficiency versus SNDR performance of state-of-the-art tailored
(ISSCC- VLSI 1997-2012) and reconfigurable ADCs............................... 13
Fig. 4. Area-efficiency versus SNDR performance of state-of-the-art tailored
(ISSCC- VLSI 1997-2012) and reconfigurable ADCs............................... 15
Fig. 5. Power-efficiency versus SNDR performance of state-of-the-art ADCs. . 24
Fig. 6. Generic scheme of a ∆Σ ADC ...................................................................... 27
Fig. 7. ∆ΣM architecture (a) Basic scheme, (b) Linear model. ............................... 27
Fig. 8. State-of-the-art reconfigurable ADCs for multi-standard applications.
Continuous-time ∆Σ architectures are depicted in red, discrete-time
∆ΣMs in black; single-loop topologies are represented as empty shapes,
cascade as filled shapes. ................................................................................ 31
Fig. 9. Conventional FB (a) and FF (b) single loop ∆Σ modulators. The
implementation of the SC integrators H(z) is shown the inset. ............... 37
Fig. 10. Flow diagram of the proposed method for power-optimal point-solution
∆Σ designs. The index i (i=1,…,N) indicates the position of each
integrator in the ∆ΣM starting from the input. .......................................... 39
Fig. 11. Different feedback configurations of an SC integrator. A single-ended
implementation is shown for simplicity. L and L are feedback signals
p,j n,j
driving the DAC (j=1, …, 2B-1). .................................................................. 45
Fig. 12. Flow diagram of the procedure to calculate the power contributions of
the ∆ΣM. ........................................................................................................ 47
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