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Polycrystallization effects on the nanoscale electrical properties of high-k dielectrics. PDF

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Lanzaetal.NanoscaleResearchLetters2011,6:108 http://www.nanoscalereslett.com/content/6/1/108 NANO EXPRESS Open Access Polycrystallization effects on the nanoscale electrical properties of high-k dielectrics Mario Lanza*, Vanessa Iglesias, Marc Porti, Montse Nafria, Xavier Aymerich Abstract In this study, atomic force microscopy-related techniques have been used to investigate, at the nanoscale, how the polycrystallization of an Al O -based gate stack, after a thermal annealing process, affects the variability of its 2 3 electrical properties. The impact of an electrical stress on the electrical conduction and the charge trapping of amorphous and polycrystalline Al O layers have been also analyzed. 2 3 Introduction high-k dielectrics. While in some polycrystalline materi- To reduce the excess of gate leakage currents in metal- als the electrical conduction seems to be mainly related oxide-semiconductor (MOS) devices, the ultra thin SiO to the bulk of grains [16], in others, current can flow 2 gate oxide is replaced by other high-k dielectric materi- preferentially through grain boundaries (GBs) [17-20]. als [1]. However, high-k-based devices still show some Since this topic can be crucial for the successful inclu- drawbacks, and therefore to have a better knowledge of sion of high-k dielectrics in electron devices, in this their properties and to improve their performance, a study, AFM-related techniques have been used to inves- detailed electrical characterization is required. Many tigate, at the nanoscale, the effect of the high-k material researches have been devoted to the study of the electri- polycrystallization (derived from an annealing process) cal characteristics of high-k gate dielectrics, mainly on the conductivity and charge trapping of Al O -based 2 3 using standard wafer level characterization techniques stacks for Flash memories. on fully processed MOS capacitors or transistors [1-4]. However, since the lateral dimensions of complementary Experimental MOS devices are shrinking to a few tens of nanometers Gate stacks, which consist of a nominal 10-nm-thick or below, for a detailed and profound characterization, Al O layer and a 1-nm-thick SiO interface layer on 2 3 2 advanced methods with a large lateral resolution are top of a p-type Silicon substrate, have been analyzed. required. In this direction, conductive atomic force After the Al O deposition, some of the samples were 2 3 microscope (CAFM), as demonstrated for SiO and annealed by rapid thermal process (RTP) in nitrogen at 2 other insulators [5-14], is a very promising tool which 750 or at 950°C. The electrical properties of the stack allows for a nanometer-resolved characterization of the were measured using a Dimension 3100 AFM provided electrical and topographical properties of the gate oxide. with CAFM and Kelvin probe force microscope (KPFM) Characterization at the nanoscale allows us to study modules. The CAFM allows us to obtain, simultaneously which factors determine the electrical properties of the to the topography, current images of the structures, by dielectric stack, and details on how they affect them. For means of applying a constant voltage between the tip example, some manufacturing processes (such as high- and the sample during a surface scan, and I-V character- temperature annealing) can alter their electrical proper- istics on fixed locations, by means of applying ramped ties because of the polycrystallization of the high-k voltage tests. The KPFM allows us to obtain, simulta- dielectric, which can affect its electrical homogeneity neously to the topography, images of the contact poten- [15]. Recently, the CAFM has been started to be used to tial difference (CPD) between the tip and the substrate. evaluate the electrical conduction of polycrystalline For all the current and CPD measurements, Si tips with a Pt-Ir or diamond coating were used. Topographic images have been obtained in tapping mode using *Correspondence:[email protected] Silicon ultra sharp tips without coating, which offer a Dept.Eng.Electrònica,EdificiQ,CampusUAB,08193Bellaterra,Spain ©2011Lanzaetal;licenseeSpringer.ThisisanOpenAccessarticledistributedunderthetermsoftheCreativeCommonsAttribution License(http://creativecommons.org/licenses/by/2.0),whichpermitsunrestricteduse,distribution,andreproductioninanymedium, providedtheoriginalworkisproperlycited. Lanzaetal.NanoscaleResearchLetters2011,6:108 Page2of9 http://www.nanoscalereslett.com/content/6/1/108 better spatial resolution. Other techniques such as trans- amorphous (g) and polycrystalline sample (h). Their rms mission electron microscopy (TEM) and X-ray reflecto- value is also included. Again, after crystallization, the metry have been also used to perform a physical deviation increases, suggesting larger inhomogeneities in analysis of the structures. its trapping properties. The results presented until now demonstrate that the As-grown dielectrics polycrystallization of the Al O layers leads to a larger 2 3 To begin with, a physical analysis of the two samples inhomogeneity of the sample conduction and charge has been performed with TEM and X-ray Reflectometry. trapped in the stack, which could be attributed to the Figure 1 shows cross-sectional TEM images of the sam- different electrical properties of nanocrystals and grain ple annealed at (a) 750 and (b) 950°C. Note that the dif- boundaries. Taking advantage of the large lateral resolu- ferent layers of the stack structure are clearly tion of the CAFM, a more detailed analysis has been distinguished (SiO interfacial layer and high-k dielec- performed to explore this point. Toward this aim, the 2 tric). Moreover, it can also be observed that the sample areas with smaller conductivity have been evaluated annealed at 950°C shows a polycrystalline structure (the from the current images of the sample that has poly- different gray intensities in the high-k layer correspond- crystallized (Figure 2). In Figure 2, the white areas cor- ing to the different orientations of the nanocrystals), respond to the regions with a current above 0.2 pA, while the sample annealed at 750°C remains amorphous. while the black areas show a current lower than the These results were confirmed from GIXRD measure- noise level. The table in Figure 2 includes the results of ments [21]. From TEM images, the crystalline grains the statistical analysis of the image, indicating the num- seem to have a diameter of 15-30 nm. The surface of ber, density, and size of the regions with a smaller con- the two samples has also been studied from AFM topo- ductivity (black regions). Note that the average size of graphy maps. Figure 1 shows topographic images these areas is approximately 20 nm, which is compatible obtained on the (c) amorphous and (d) polycrystalline with the results obtained from TEM images (Figure 1) structures. The root mean square (rms) value of the for the sizes of the Al O nanocrystals. Therefore, these 2 3 images is also included. Although in this experiment the results suggest that the regions with a smaller conduc- resolution of the set-up does not allow to distinguish tivity could be related to the grains in the polycrystalline single crystals, the figure indicates an increase of the structure: the nanocrystals are more insulating whereas surface roughness after polycrystallization, in agreement the grain boundaries show a larger conductivity. Note with [11,22]. Finally, since a thermal annealing process that, in Figure 2, the width of the regions attributed to can also affect the thickness of the layers of the stack, the grain boundaries is much larger than that estimated the actual physical thicknesses of the SiO and Al O in other studies [22], when AFM measurements were 2 2 3 filmsweredeterminedfromX-rayReflectometry(Table1). performed in ultra high vacuum (UHV). This apparent Note that, after polycrystallization, a reduction in the discrepancy can be explained by considering the impov- thicknessofthehigh-klayerisobserved[23],leadingtoa erishment of the lateral resolution of CAFM experi- smallerequivalentoxidethickness(EOT)[17]. ments when working in air, compared to UHV The impact of the polycrystallization of the Al O measurements [22,24]. The differences in electrical 2 3 layer on the electrical conduction of the gate stack has behaviors between nanocrystals and grain boundaries been analyzed at the nanoscale from current and CPD could explain the larger inhomogeneity detected in the images obtained on fresh structures (before an electrical current and CPD images after polycrystallization. Grain stress). Figure 1e,f shows two current images obtained boundaries, probably with an excess of some kind of on the amorphous and polycrystalline sample, respec- defects or trapping sites generated during the polycrys- tively, at 10.25 V (their average and rms values are tallization (which could be related to O-vacancies [25]), included in the figure). Note that smaller currents (in could enhance the gate current through them, probably average) are measured in the polycrystalline stack. How- because of trap-assisted-tunneling (TAT) through the ever, since the EOT of the polycrystalline sample is defects detected with KPFM [23]. smaller (see Table 1), its lower conductivity can only be It is important to emphasize that the correlation of attributed to the crystallinity of the stack and not to the the leaky positions with the grain boundaries is a quali- reduction of the oxide thickness. Figure 1f also shows tative result, since the resolution in these experiments is that the rms value of the current and, therefore, the not high enough to resolve grain boundaries. This is electrical inhomogeneity of the polycrystalline stack is because the CAFM measurements presented in this sec- larger. Both samples have also been analyzed with tion have been performed with Si tips coated with a KPFM [21], which can provide information about the metallic layer in ambient conditions, drastically reducing presence of charge and trapping centers in the stack. its lateral resolution to approximately 20 nm [26]. Note, Figure 1 shows two CPD images obtained on the however, that other experiments, with sufficient Lanzaetal.NanoscaleResearchLetters2011,6:108 Page3of9 http://www.nanoscalereslett.com/content/6/1/108 Figure 1 TEM images (a, b), topographic maps (c, d), current maps (e, f), and CPDmaps (g, h) for amorphous (left column) and polycrystalline(rightcolumn)samples.Thevaluesofthemostrelevantparametersareshown. Lanzaetal.NanoscaleResearchLetters2011,6:108 Page4of9 http://www.nanoscalereslett.com/content/6/1/108 Table 1Thicknesses ofthe Al O andSiO layers were scanned (1000 × 1000 nm2 and 1500 × 1500 nm2), 2 3 2 obtained from X-ray reflectrometry onthe amorphous which included the previously scanned smaller areas. andpolycrystalline samples Figure 3 shows a sequence of three images measured on Phase Al O thickness SiO thickness EOT(nm) the amorphous (a, b, and c) and polycrystalline (d, e, 2 3 2 (nm) (nm) and f) samples. The first scan corresponds to images (a) Amorphous 14.6 1.0 7.3 and (d) and, the last scan, to images (c) and (f). The Polycrystalline 12.4 1.2 6.6 sizes of the images are (a and d) 500 nm × 500 nm, (b TheEOTwasestimatedbyconsideringapermittivityof9.1fortheAl2O3 and e) 1 μm × 1 μm, and (c and f) 1.5 μm × 1.5 μm. layer. The applied voltage was 11.5 V in all the cases. This procedure allows us to compare areas that have been resolution, have shown the relation between leaky sites subjected to different stresses–or, in other words–areas and grain boundaries [27,28]. The section “Influence of that have experienced different degradation levels. the environment on the resolution of grain boundaries” Comparing Figure 3a,d, which corresponds to the first will be devoted to investigate how the CAFM resolution image (fresh area) measured on amorphous and poly- can be improved. crystalline structures, respectively, results similar to those shown in the previous section are obtained. On Stressed dielectrics polycrystalline samples, background conduction is smal- In this section, the impact of an electrical stress on the ler (table of Figure 3, first scan). However, the leaky electrical conduction and charge trapping of the Al O sites of polycrystalline structures (spot S3, S4, and S5) 2 3 layers will be analyzed at the nanoscale. Differences have a larger conductivity compared to those of amor- between amorphous and polycrystalline structures will phous samples (S1 and S2). As discussed in the previous be evaluated. First, the effect of the degradation (before section, the larger current differences in the polycrystal- breakdown) induced during a constant voltage scan on a line structure could be attributed to the differences in certain area of the oxide will be investigated. Toward the conductivities between the crystals (background) this aim, sequences of current images have been col- and grain boundaries (leaky sites). lected, on amorphous and polycrystalline Al O samples. The effect of the stress has been analyzed from the 2 3 First, a 500 nm × 500 nm area was scanned by applying images measured during the zoom-outs. On the amor- a large enough constant voltage to induce degradation. phous sample (Figure 3b), the central area (which was Afterward, two zoom-outs were done, and larger areas previously pre-stressed, Figure 3a) shows smaller cur- rents than the rest of the scanned region. A similar behavior can be observed in Figure 3c, where three con- centric areas can be distinguished: a first central area with the smallest current value (three scans), another second area with a larger current (two scans), and the peripheral and the most conductive area (only one scan, that is, a fresh area). The quantitative values of the background current on the three concentric areas are shown in the table of Figure 3. In the amorphous sam- ple, the background current decreases significantly as the stress proceeds, making the structure less conduc- tive. This behavior, as already pointed out for SiO 2 layers [29] or high-k dielectrics, can be related to nega- tive charge trapping in the native defects or in traps generated during the stress. In the case of polycrystalline structures (Figure 3d,e,f and table), the decrease in the background conductivity is less important when com- pared to amorphous samples. This result suggests a smaller impact of the stress at the positions where crys- # Grains Density Diameter (nm) tals are present. (cid:11)(cid:6)(cid:18)(cid:541)(cid:80)(cid:240)(cid:12) Mean Deviation Although, in polycrystalline samples, regions with 78 312 19.5 19.0 background currents (which can be probably related to Figure 2 Grain analysis of a current image measured on the positions with a crystal under the CAFM tip) seem to sampleannealedat950°C.Whiteareascorrespondtocurrents be more resistive and robust to an electrical stress than abovethenoiselevel(0.2pA.) amorphous oxides, this behavior cannot be extended to Lanzaetal.NanoscaleResearchLetters2011,6:108 Page5of9 http://www.nanoscalereslett.com/content/6/1/108 Current on the amorphous sample (pA) Current on the polycrystalline sample (pA) Background S1 S2 Background S3 S4 S5 First Scan 0.42 1.4 0.99 0.10 5.8 2.5 4.0 Second scan 0.13 1.2 0.51 0.07 1.2 0.87 1.1 Third scan 0.05 0.65 0.48 0.05 0.67 0.32 0.62 Figure3Firstscans(a,b)andtwoconsecutivezoomsout(b/e,c/f)onamorphous(a,b,c)andpolycrystalline(d,e,f)samples.Their sizesare(a,d)500nm×500nm(b,e)1μm×1μmand(c,f)1.5μm×1.5μm.Theappliedvoltagewas11.5Vinallcases.Thetableshows theevolutionofthemaximumcurrentdrivenbythespotsS1-S5andonbackgroundareasforbothsamples. the weak spots (leaky sites). As an example, the table in proceeds, a larger amount of charge is trapped in the Figure 3 shows the maximum current in different spots as-grown or generated defects on the leaky positions, and its evolution with the stress on amorphous (spots leading to a higher reduction of the current compared S1 and S2) and polycrystalline samples (S3, S4, and S5). to amorphous oxides. Since these leaky regions could be Note that the weak spots in the polycrystalline structure related to the grain boundaries between nanocrystals, show, before the stress ("first scan”), larger leakage cur- charge trapping (in as-grown or generated defects) rents compared with the amorphous gate oxide. How- mainly occurs at those locations, leading to a higher ever, after the stress ("second scan” and “third scan”), reduction of the conductivity compared to the back- the reduction of current through these spots is larger ground areas. In amorphous samples, no distinction than those in amorphous structures. Therefore, initially, between crystals and grain boundaries can be observed, the leaky sites of polycrystalline samples are, from an and so trapping is randomly distributed in the gate area. electrical point of view, weaker (their conductivity is Finally, the impact of breakdown (BD) was also inves- higher) than those in amorphous oxides (because the tigated on polycrystalline and amorphous oxides. dielectric is thinner or because of the presence of Toward this aim, first, ramped voltage stresses (RVS) defects that enhance tunneling). However, as the stress with a current limit of 100 pA and with the same Lanzaetal.NanoscaleResearchLetters2011,6:108 Page6of9 http://www.nanoscalereslett.com/content/6/1/108 ending voltage have been applied on different oxide current is measured in the polycrystalline structure is locations until BD. Figure 4a,b shows an example of two lower, pointing out a harder BD. After the measurement consecutive I-V curves measured on an amorphous and of the I-V curves, current images of the areas that con- a polycrystalline structure, respectively. Note that, in the tain the stressed locations have been collected. Figure second RVS, current can be measured at much lower 4c,d shows the current images obtained on a 1 μm × 1 voltages in both cases, which is an indication that BD μm area of the amorphous (c) and the polycrystalline has been triggered. Moreover, the voltage at which (d) sample where four RVS had been previously applied S1 S2 S3 S4 Current (pA) 0.38 0.74 0.66 0.54 (c) Area (nm2) 8.8·102 1.1·102 1.1·104 7.2·103 Current (pA) 9.8 7.3 9.8 9.6 (d) Area (nm2) 2.3·104 8.4·103 2.3·104 1.9·104 Figure4Currentimagesobtainedonanamorphous(c)andpolycrystalline(d)samplewherepreviously,fourRVSwhereappliedto induceBD.Thevoltageappliedduringthescanwas,inbothcases,-8.6V.(a,b)correspondtotypicalI-Vcurvesmeasuredonthosepositions. ThemaximumcurrentandareaoftheBDspotscanbefoundinthetable. Lanzaetal.NanoscaleResearchLetters2011,6:108 Page7of9 http://www.nanoscalereslett.com/content/6/1/108 until BD at different locations. Regions with larger cur- behavior. While in UHV, a clear granular pattern can be rents are observed, which correspond to the BD spots. observed [35] (which overlaps with that observed in the The table in the figure shows the maximum current and topographical image, indicating that current flows area of the BD spots generated on each sample. Note mainly through grain boundaries, as suggested in that, for the amorphous sample, the BD areas are smal- the sections “As-grown dielectrics” and “Stressed ler and the post-BD electrical conduction is lower, sug- dielectrics”), in HV and, specially, in air, the granular gesting softer BD events, in agreement with the post-BD structure is not so clearly distinguishable and a point- I-V curves. From these results and those obtained dur- to-point correlation of the leakage spots with the posi- ing the degradation stage, it seems reasonable to specu- tion of the grain boundaries is not possible. If it is late that, in polycrystalline structures (with harder BD), assumed that, in (d) and (e), the current is measured BD takes place at the weaker regions, that is, the grain basically through GBs (conclusion that can be drawn boundaries. Therefore, the presence of grain boundaries from the analysis of images c and f), then the measured on Al O layers could reduce significantly the reliability GB’s width is much larger than that in (f). All these 2 3 of MOS devices due to their lower robustness. effects could be related, as demonstrated in [19], to the contact area increase because of the presence of the Influence of the environment on the resolution of grain water meniscus. Therefore, the results clearly demon- boundaries strate that the AFM lateral resolution is very sensitive to Some authors have suggested that, when working with a the environment, a point that is extremely important CAFM in air, the tip-sample contact area increases, when studying polycrystalline high-k dielectrics. Since probably due to the presence of a water layer on the the grain boundaries width is close to the limit of the sample (and, therefore, a water meniscus between the AFM resolution, environmental conditions can be the tip and the surface), which can reduce the lateral resolu- determinant factors to precisely correlate the leakage tion of the measurements [19,30,31]. Since the grain spots position with the morphological structure of the boundaries width is in the range of few nanometers high-k dielectric. [32,33] and the CAFM lateral resolution in air when using metal coated tips is about 10 nm, grain bound- Conclusion aries could not always be resolved. This would explain The conductivity and charge trapping of amorphous why in the sections “As-grown dielectrics” and “Stressed and polycrystalline Al O layers stacks for memory 2 3 dielectrics” when working with a CAFM in ambient con- applications have been studied before and after an ditions, a point-to-point correlation between the topo- electrical stress at nanometer scale using AFM-related graphical and electrical properties (in particular, techniques in ambient conditions. The current mea- between the leaky sites and the grain boundaries posi- surements obtained with CAFM before an electrical tion) was not possible. For this reason, when a higher stress show that the polycrystallization of the Al O 2 3 resolution is needed, CAFM in vacuum or UHV has leads to a smaller average and a larger spatial inhomo- been used [12,24,34,35]. In this section, the impact of geneity of the sample conductivity. A statistical analy- environmental conditions on the CAFM electrical reso- sis of the current images registered on polycrystalline lution for the study of polycrystalline structures will be samples has been compared to the measurements analyzed. obtained with TEM, showing that the mean size of the Toward the above aim, topographical and current less conductive areas is similar to the dimensions of images obtained on polycrystalline high-k dielectrics at the crystals. Therefore, the regions with a smaller con- different ambient conditions have been compared. ductivity could be related to the grains of the polycrys- Figure 5 shows topographical (first row) and current talline structure: the polycrystals are more insulating (second row) maps measured on a 5-nm-thick HfO whereas the grain boundaries show a larger conductiv- 2 layer grown on a Si substrate, obtained in air (a and d), ity. The charge-trapping properties of amorphous and high-vacuum (b and e, 1.2 × 10-6 mbar), and UHV polycrystalline samples were also investigated after an (c and f, 10-9 mbar) [35]. In current images, the white electrical stress. The results suggest that, although the areas correspond to the regions with a current above crystals are more resistive and robust (from an electri- 0.2 pA, while the black areas show a current lower than cal point of view) than the amorphous oxide, the grain the noise level. Note that as pressure decreases (and, boundaries of the polycrystalline samples seem to be therefore, the size of the water meniscus is reduced), more sensitive to an electrical stress than those of the topography images show a better-defined granular struc- non-crystallized structures: grain boundaries would ture, which can be attributed to single (or a cluster of) initially act as conductive paths, but would favor a fas- nanocrystals (grain boundaries would correspond to the ter charge trapping. Therefore, polycrystallization depressed regions [32]). Current maps show a similar strongly contributes to the inhomogeneity increase of Lanzaetal.NanoscaleResearchLetters2011,6:108 Page8of9 http://www.nanoscalereslett.com/content/6/1/108 Fi 5 T h ( ) d (d f) b i d l lli 5 hi k l i Figure 5 Topography (a, b, c) and current (d, e, f) maps obtained on a polycrystalline 5-nm-thick HfO sample in different 2 environments:air(a,d),high-vacuum(b,e),andultra-high-vacuum(UHV)–(c,f).Incurrentimages,whiteareascorrespondtoregionswith acurrentabove0.2pA,whiletheblackareasshowacurrentlowerthanthenoiselevel. the conduction and trapping properties of the stacks, LanzatocarryoutsomeofthepresentedAFMexperimentsandtoG. which could reduce the reliability of the MOS devices JaschkeandS.Teichert(Qimonda,Germany)andG.Bersuker(Sematech, USA)forsampleprovision.TheauthorsalsowanttoacknowledgeT. due to the weaker dielectric strength of the grain Schroeder(IHP)forhostingV.IglesiasintheirfacilitiesinFrankfurtOder boundaries. Finally, the influence of the environment (Germany).Theauthorsarealsoindebtedtothemforvaluablediscussions. conditions on the study of polycrystalline high-k Authors’contributions dielectrics was also analyzed. The results demonstrate MLcollectedalltopographicandcurrentscansperformedinair.VIcarried that the reduction of the water meniscus can be a outthetopographicandcurrentscansperformedinultrahighvacuum determinant factor for a precise study in detail on the conditions.MPcontributedtotheredactionofthemanuscriptandinthe designofthestudy.MNandXAparticipatedinthedesignandcoordination electrical properties of the grain boundaries. ofthestudyandreviewedthemanuscript.Allauthorsreadandapproved thefinalmanuscript. Abbreviations Competinginterests AFM:atomicforcemicroscopy;BD:breakdown;CFAM:conductiveatomic Theauthorsdeclarethattheyhavenocompetinginterests. forcemicroscope;CPD:contactpotentialdifference;GBs:grainboundaries; KPFM:Kelvinprobeforcemicroscope;rms:rootmeansquare;RTP:rapid Received:11September2010 Accepted:31January2011 thermalprocess;RVS:rampedvoltagestresses;TAT:trap-assisted-tunneling; Published:31January2011 TEM:transmissionelectronmicroscopy;UHV:ultrahighvacuum. References Acknowledgements 1. RobertsonJ:HighdielectricconstantgateoxidesformetaloxideSi ThisstudyhasbeenpartiallysupportedbytheSpanishMICINN(TEC2007- transistors.RepProgrPhys2006,69:327-396. 61294/MICresearchprojectandHA2007-0029IntegratedAction),andthe 2. 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