Pipeline Analog-to-Digital Converters for Wide-Band Wireless Communications PDF
Preview Pipeline Analog-to-Digital Converters for Wide-Band Wireless Communications
HelsinkiUniversityofTechnologyElectronicCircuitDesignLaboratory Report35,Espoo2002 Pipeline Analog-to-Digital Converters for Wide- Band Wireless Communications LauriSumanen DissertationforthedegreeofDoctorofScienceinTechnologytobepresentedwithduepermis- sion of the Department of Electrical and Communications Engineering for public examination anddebateinAuditoriumS1atHelsinkiUniversityofTechnology(Espoo,Finland)onthe13th ofDecember,2002,at12o’clocknoon. HelsinkiUniversityofTechnology DepartmentofElectricalandCommunicationsEngineering ElectronicCircuitDesignLaboratory Teknillinenkorkeakoulu Sähkö-jatietoliikennetekniikanosasto Piiritekniikanlaboratorio Distribution: HelsinkiUniversityofTechnology DepartmentofElectricalandCommunicationsEngineering ElectronicCircuitDesignLaboratory P.O.Box3000 FIN-02015HUT Finland Tel. +35894512271 Fax: +35894512269 Copyright(cid:13)c 2002LauriSumanen ISBN951-22-6222-3(printedversion) ISSN1455-8440 OtamediaOy Espoo2002 Abstract Duringthelastdecade,thedevelopmentoftheanalogelectronicshasbeendictatedby theenormousgrowthofthewirelesscommunications. Typicalforthenewcommuni- cation standards has been an evolution towards higher data rates, which allows more servicestobeprovided. Simultaneously,theboundarybetweenanaloganddigitalsig- nalprocessingismovingclosertotheantenna,thusaimingforasoftwaredefinedradio. Foranalog-to-digitalconverters(ADCs)ofradioreceiversthisindicateshighersample rate,widerbandwidth,higherresolution,andlowerpowerdissipation. The radio receiver architectures, showing the greatest potential to meet the com- mercialtrends,includethedirectconversionreceiverandthesuperheterodynereceiver with an ADC sampling at the intermediate frequency (IF). The pipelined ADC archi- tecture,basedontheswitchedcapacitor(SC)technique,hasmostsuccessfullycovered thewidelyseparatedresolutionandsampleraterequirementsofthesereceiverarchitec- tures.Inthisthesis,therequirementsofADCsinbothofthesereceiverarchitecturesare studiedusingthesystemspecificationsofthe3GWCDMAstandard.Fromthestandard andfromthelimitedperformanceofthecircuitbuildingblocks,designconstraintsfor pipelineADCs,atthearchitecturalandcircuitlevel,aredrawn. Atthecircuitlevel,noveltopologiesforalltheessentialblocksofthepipelineADC have been developed. These include a dual-mode operational amplifier, low-power voltage reference circuits with buffering, and a floating-bulk bootstrapped switch for highly-linear IF-sampling. The emphasis has been on dynamic comparators: a new mismatchinsensitivetopologyisproposedandmeasurementresultsforthreedifferent topologiesarepresented. At the architectural level, the optimization of the ADCs in the single-chip direct conversion receivers is discussed: the need for small area, low power, suppression of substratenoise,inputandoutputinterfaces,etc.Adaptationoftheresolutionandsample rate of a pipeline ADC, to be used in more flexible multi-mode receivers, is also an importanttopicincluded. A6-bit15.36-MS/sembeddedCMOSpipelineADCandan 8-bit1/15.36-MS/sdual-modeCMOSpipelineADC,optimizedforlow-powersingle- ii Abstract chipdirectconversionreceiverswithsingle-channelreception,havebeendesigned. The bandwidth of a pipeline ADC can be extended by employing parallelism to allow multi-channel reception. The errors resulted from mismatch of parallel signal pathsareanalyzedandtheireliminationispresented. Particularly,anoptimalpartition- ingoftheresolutionbetweenthestages,andthenumberofparallelchannels,intime- interleavedADCsarederived. Alow-power10-bit200-MS/sCMOSparallelpipeline ADCemployingdoublesamplingandafront-endsample-and-hold(S/H)circuitisim- plemented. Emphasisofthethesisisonhigh-resolutionpipelineADCswithIF-samplingcapa- bility.Theresolutionisextendedbeyondthelimitssetbydevicematchingbyusingcal- ibration,whiletimeinterleavingisappliedtowidenthesignalbandwidth. Areviewof calibrationanderroraveragingtechniquesispresented.Asimpledigitalself-calibration techniquetocompensatecapacitormismatchwithinasingle-channelpipelineADC,and thegainandoffsetmismatchbetweenthechannelsofatime-interleavedADC,isdevel- oped. Thenewcalibrationmethodisvalidatedwithtwohigh-resolutionBiCMOSpro- totypes,a13-bit50-MS/ssingle-channelanda14-bit160-MS/sparallelpipelineADC, bothutilizingahighlylinearfront-endallowingsamplingfrom200-MHzIF-band. Keywords: analogintegratedcircuit,analog-to-digitalconversion,CMOS,BiCMOS, doublesampling, IF-sampling, directconversion, comparator, pipelinedanalog- to-digital converter, switched capacitor, time-interleaving, multi-mode, calibra- tion. Preface TheresearchreportedinthisthesishasbeencarriedoutattheElectronicCircuitDesign Laboratory,HelsinkiUniversityofTechnologybetweenyears1998–2002. Theworkis donewithinseveralresearchprojectsfundedbyFinnishNationalTechnologyAgency (TEKES),NokiaNetworks,andNokiaMobilePhones. Duringtheseyears,Ihadalso a privilege of participating the Graduate School in Electronics, Telecommunications, and Automation (GETA), which partially funded the work. I thank Electronic Circuit Design Laboratory and GETA for making the work possible. I am also grateful for thefollowingfoundationsforthefinancialsupport: EemilAaltosenSäätiö, Elektroni- ikkainsinöörienSäätiö,NokiaOyj:nSäätiö,Tekniikanedistämissäätiö. IwouldliketoexpressmygratitudetomysupervisorProf. KariHalonen,whohas introduced me into the data converter research and given me the opportunity to work relatively freely under these interesting projects. Without his encouragement, thrust, andwayofpushingthedesigngoalsthisworkwouldnothavebeencompleted. Ialso warmlythankProf. DavidA.JohnsandProf. PieroMalcovatiforreviewingthisthesis andfortheirvaluablecommentsandsuggestions. I am specially grateful for Dr. Mikko Waltari, who has been my supervisor and partner in the A/D converter research. His inexhaustible storage of innovative ideas, sovereign technical competence, and strong commitment to the projects we have car- ried out together has been indispensable. The valuable technical contribution of the junior team members in these projects, Tuomas Korhonen, Mikko Aho, and Väinö Hakkarainen,isalsogratefullyacknowledged. TheotherteamIhavebeenworkingwithconsistedofDr. AarnoPärssinen,Jarkko Jussila,Dr.KalleKivekäs,andJussiRyynänen,whoallcontributedtheirowntechnical specialty in the direct conversion receiver research. I am particularly thankful for the highly motivated, but, friendly and cozy atmosphere the team members created. The close cooperation and humorous spirit within this group have been very essential in completingthiswork. IamalsoverygratefultothewholestaffattheElectronicCircuitDesignLaboratory. iv Preface Theyhavecreatedanexceptional,effectiveandcomfortable,atmosphereandhelpedin manyoftheeverydayissuesrelatedtothework. Hugethankstomyfriends,especially,forremainingmeofmoreimportantthings than this work. The various activities and hobbies of the ’VirNuMiToVi’ association haveofferedexcellentcontrastfortheday’swork.Andinparticular,myfellowstudents Dr.KimmoKalliolaandJaniOllikainendeservebigthanksforkeepingupaninspiring, but,entertaining,academicpressureduringthewholestudies. Finally,mywarmestthanksforthesupportandloveIhavereceivedfrommyfamily, mymotherAnja,myfatherMarkku,andmysisterKaisa. Andthebiggestthankstomy dearwife,Nadja,whohassupportedmeduringthedifficulttimes,aswellassharedthe goodmoments. Herlove,care,andlivelinesshavecarriedmeoninthisdoctoralwork. LauriSumanen Espoo,November2002 Symbols and Abbreviations A Amplitude,area,amplifiervoltagegain A Voltagegainoffeedbackamplifier f A OpenloopDC-gain 0 b Numberofoutputcodes i B Bit,effectivestageresolution B Noisebandwidth n C Capacitance,numberofuncorrectedbits C Compensationcapacitance c C Feedbackcapacitance f C Loadcapacitance L C Effectiveholdmodeloadcapacitance L,H C Totalloadcapacitance L,tot C Parasiticoutputcapacitance out C Gate-oxidecapacitance ox C Parasiticinputcapacitance par C Samplingcapacitance s,i d Scalingparameteroftransistorsize D Multiplierofreferencevoltage i D Digitaloutput out vi SymbolsandAbbreviations DNL Differentialnonlinearity e Noise,error,scalingparameteroftransistorcurrent e Quantizationerror q e2 Noisepower E Energyperconversionstep conv ENOB Effectivenumberofbits f Frequency,feedbackfactor f Frequencyofblocker block f Digitalsignalfrequency dig f Inputfrequency in f Localoscillatorfrequency LO f Samplingfrequency S f Signalfrequency sig f Frequencyofspurioustone spur FOM Areafigureofmerit A g Conductance G Interstagegain i G Codinggain code G Fourierseriescoefficientofgainmismatch k g Transconductance m G Processinggain P GBW Gainbandwidthproduct HR Headroom i Stageindex I Current SymbolsandAbbreviations vii I Totalamplifiercurrentconsumption amp I Draincurrent D I Maximaloutputcurrentofamplifier max I Referencecurrent ref IIP Inputinterceptpoint INL Integralnonlinearity IP Interceptpoint j Capacitorindex k Boltzmann’scoefficient,loadcapacitancerelation,numberofstages,error correctioncoefficient K Amplifiercurrentgain,gainerrorcorrectioncoefficient L Channellength m Capacitor switching parameter, number of different stage resolutions, in- dex M Numberofparallelchannels M Implementationmargin IM n Numberofsamplingcapacitors,index N Numberofbits,noisepower N Aperturejitterlimitedresolution aperture N Numberofharmonics H n Numberofcapacitors max N Thermalnoisefloor TH N Thermalnoiselimitedresolution thermal ND A/Dconverternoisedistance ADC NF Noisefigure viii SymbolsandAbbreviations MDS Minimumdetectablesignallevel OSR Oversamplingratio (cid:48) p Non-dominantpoleofamplifier 1 P Powerdissipation D P Poweroftheintermodulationproduct IMD P Outputpower out PA Peak-to-averagesignalpowerratio Q Qualityfactor Q Channelcharge ch Q Numberofquantizationsteps i r Redundancybit,resistance R Resistance r Outputresistanceofatransistor ds R Effectivethermalresistance eff r Switchon-resistance on r Amplifieroutputresistance out R Referencevalue(currentorvoltage) ref S Errorcorrectioncoefficient S Signalrmspower P SNDR Signal-to-noiseanddistortionratio SNR Signal-to-noiseratio SR Slewrate t Time T Absolutetemperature,samplingperiod t Oxidethickness ox
Description:The list of books you might like
