Performance analysis of low jitter high-speed photonic analog-to-digital converters in silicon photonics vorgelegtvon HerrnEdgarKrune,M.Sc. geb. inSauralowka/Kasachstan VonderFakultätIV-ElektrotechnikundInformatik-der TechnischenUniversitätBerlin zurErlangungdesakademischenGrades DoktorderIngenieurwissenschaften -Dr.-Ing.- genehmigteDissertation Promotionsausschuss: Vorsitzender: Prof. Dr.-Ing. StephanVölker Gutachter: Prof. Dr.-Ing. KlausPetermann Gutachter: Prof. Dr. FranzX.Kärtner Gutachter: Dr.-Ing. LarsZimmermann TagderwissenschaftlichenAussprache: 04.09.2017 Berlin2017 IwouldliketothankmyelementaryschoolteacherMrs. E.Lutter. Onlythankstoher strongcommitmentIwasacceptedatthegymnasiumalthoughmygradeswerenotgood enough,sinceIhadonlybeeninGermanyforoneandahalfyearsandhadjustlearnedthe language. Withoutherencouragement,Iwouldnothavetrodtheeducationalpathwhich ledtothisthesis. Abstract Theperformanceofelectronicanalog-to-digitalconverters(ADCs)ismainlylimitedbythe sampling instant precision if high-frequency signals are sampled. Its uncertainty is called timing jitter. The electrical clock generation and its distribution on chip are limited to a jitter of (cid:24) 100fs and no significant improvement was achieved in the last decade. Phys- ical restrictions prevent its further decrease. But mode-locked lasers can provide optical pulsetrainswithordersofmagnitudehighertimingprecision. Thisisexploitedbyphotonic ADCswherethesamplinginstantsaredefinedbyanultra-lowjitteropticalpulsetrain. During the last three decades, silicon photonics has evolved to a CMOS compatible plat- form which enables the integration of optics and electronics on the same chip. This thesis addresses such photonic integrated ADCs in silicon photonics. Possible architectures are discussed and two principle sampling instants are identified, namely, the rising edge of the induced electrical pulses and the center of mass of the optical or the detected pulses. A quantum noise model is introduced enabling the performance analysis of both sampler types. Itisshownthatrisingedgesamplerscanachievejittervaluesdownto(cid:24) 10fs. Cen- ter of mass samplers can achieve even (cid:24) 1fs jitter but the ADC resolution is limited by pulse-to-pulse energy fluctuations to < 9 effective number of bits. It is shown that optical clockdistributionnetworksinduceonlyasmallskewof< 100fsfordelaylinesupto75ps but its temperature dependence still necessitates its compensation. A rising edge triggered opto-electronic clock converter is shown which achieves a fundamental jitter limit of only 10fs,confirmingthesuperiorcharacteristicsofphotonicADCs. Keywords: Analog-to-DigitalConverter,SiliconPhotonics,Jitter,Skew,OpticalClock Distribution Zusammenfassung DiePerformanceelektronischerAnalog-Digital-Umwandler(ADU)hängtvorallemvonder zeitlichen Präzession des Abtastzeitpunktes ab, wenn hohe Frequenzen abgetastet werden. Dessen Unsicherheit wird als zeitlicher Jitter bezeichent. Die elektrische Taktgenerierung und dessen Verteilung auf dem Chip ist beschränkt zu einem Jitter von (cid:24) 100fs und eine VerbesserungistinderletztenDekadenichterreichtworden.PhysikalischeGrenzenverhin- derndessenweitereReduktion.JedochkönnenmodengekoppelteLaseroptischeImpulszü- ge mit einer um Größenordnungen höheren Präzession liefern. Dies wird in photonischen ADU ausgenutzt, wo die Abtastzeitpunkte durch optische Impulszüge mit ultra-geringen Jitterdefiniertwerden. In den letzten drei Dekaden hat sich die Silizium-Photonik zu einer CMOS-kompatiblen Plattform entwickelt, die die Integration von Optik und Elektronik auf demselben Chip er- möglicht. Diese Dissertation untersucht derartige photonisch integrierte ADU in Silizium- Photonik.MöglicheArchitekturenwerdendiskutiertundzweiprinzipielleAbtastzeitpunk- te werden identifiziert. Diese sind die Anstiegsflanke der induzierten elektrischen Impulse sowiederSchwerpunktderoptischenoderderdetektiertenImpulse.EinQuantenrauschmo- del wird vorgestellt, welches die Performanceanalyse beider Samplerarten ermöglicht. Es wirdgezeigt,dassSampler,diedurchAnstiegsflankengetriggertwerden,einenJitterbiszu (cid:24) 10fs erreichen können. Schwerpunkt-Sampler können sogar (cid:24) 1fs Jitter erreichen. In diesem Fall beschränken die Impuls-zu-Impuls-Energiefluktuationen die ADU-Auflösung jedoch zu < 9 effektiven Anzahl an Bits. Es wird gezeigt, dass optische Taktverteilungs- netzwerke nur einen geringen Skew von < 100fs verursachen für Verzögerungen bis zu 75ps. Jedoch erfordert dessen Temperaturabhängigkeit immer noch deren Kompensation. EindurchdieAnstiegsflankegetriggerteropto-elektronischerTaktwandlerwirdgezeigt,der einefundamentaleJittergrenzevonnur10fsaufweistunddadurchdieüberlegeneCharak- teristikphotonischerADUbestätigt. Schlagwörter: Analog-Digital-Umwandler, Silizium-Photonik, Jitter, Skew, Optische Taktverteilung ii Contents 1 Introduction 1 2 SamplerBasics 9 2.1 AmplitudeandTimingErrorsintheSamplingProcess . . . . . . . . . . . 12 2.2 ElectronicAnalog-to-DigitalConverterArchitectures . . . . . . . . . . . . 18 2.3 PerformanceofElectronicAnalog-to-DigitalConverters . . . . . . . . . . 20 3 JitterMeasurement 25 3.1 ClockJitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2 PeriodJitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3 AccumulatedJitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.4 PhaseNoiseMeasurement . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.5 JitterMeasurementofOpticalPulseTrains . . . . . . . . . . . . . . . . . . 35 4 SiliconPhotonicsPlatform 39 4.1 Fiber-ChipInterface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.2 SiliconWaveguides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2.1 Non-LinearPulsePropagation . . . . . . . . . . . . . . . . . . . . 47 4.3 MultimodeInterferenceCoupler . . . . . . . . . . . . . . . . . . . . . . . 51 4.4 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.5 Photodiodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.6 OpticalClockDistributionNetwork . . . . . . . . . . . . . . . . . . . . . 57 5 PhotonicAnalog-to-DigitalConverters 63 5.1 Mode-LockedLaser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.1.1 PulseRepetitionRateMultiplier . . . . . . . . . . . . . . . . . . . 72 5.2 PhotonicAnalog-to-DigitalConverterArchitectures . . . . . . . . . . . . . 73 iii 6 JitterofPhotonicAnalog-to-DigitalConverters 79 6.1 QuantumNoiseModelofPhotodetection . . . . . . . . . . . . . . . . . . 79 6.2 RisingEdgeSampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3 CenterofMassSampling . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.4 PerformanceComparisonofPhotonicSamplingTechniques . . . . . . . . 90 6.5 Measurability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7 Experiments 99 7.1 Skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.2 Non-linearities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.3 Opto-ElectronicClockConverter . . . . . . . . . . . . . . . . . . . . . . . 105 8 Summary 115 A DerivationofPulseTrainIntensitySpectrum 119 B DerivationofthePhotocurrentSpectrum 121 C DerivationofSSBAmplitudeandPhaseNoiseFloor 125 Acronyms 131 ListofFigures 141 ListofTables 143 Bibliography 161 iv Chapter 1 Introduction The first transistor, built on germanium by William Shockley, John Bardeen and Walter Brattain at the Bell Labs in 1947, became the kick-off for a technology which affected the history of human kind in an unprecedented speed and scale. The inventions of the semi- conductorplanarprocessbyJeanA.Hoerni[1]andoftheintegratedcircuits(ICs)parallel byRobertN.Noyce[2]andJackKilby[3]filedforpatentin1959enabledafastevolution of silicon-based integrated electronic circuits. The integration of transistor-based logic on a single chip replaced the vacuum tubes technology and led to digital signal processing in computers. Here, a unique clock signal distributed over the silicon chip corresponds to a conductor in the synchronously switching orchestra of an enormous amount of transistors. Theminiaturization-basedtrendoffasterandmorepowerfulelectronicsbecamefamousas Moore’s law. Based on his observation that the number of transistors in ICs was doubling approximately every two years, Gordon E. Moore published his projection for the future in 1965 [4]. This prediction became impressively accurate in the following decades. The mostimportanttechnologyforICimplementationbecamethecomplementarymetal-oxide- semiconductor (CMOS) technology introduced by Frank Wanlass in 1963 [5]. The more and more dense very-large-scale-integration (VLSI) circuits working at higher switching frequencies led to high requirements for the clock signal and forced IC designers to face newchallenges. Intheidealcase,auniqueclocksignalisswitchingbetweentwovoltagelevelscorrespond- ingtotheONandOFFstateofalogicdevice. Therelationbetweenthetimeperiodofthe ON state to the clock period is called duty cycle. A square wave signal has a duty cycle of50%. Providingthisclocksignalfromasinglepositiontoalldestinationsonchipleads to a hierarchical splitting of electrical wires into multiple versions to support all logic de- vices. The amount of clock destinations seen from a source is called fan-out. To induce a switching process in a CMOS circuit, a threshold voltage at the gate of a transistor has to 1 2 CHAPTER1. INTRODUCTION MMI Coupler Taper Clock ClockA PD Source ClockB Grating Coupler Waveguide Buffer (a) (b) Figure1.1:CDNinH-treebasedarchitecture:(a)Anelectricalclocksignalfromasinglesourceisdistributed byasymmetricalCDNacrossthedieto16receivers. Buffersplacedinfrontofthesplitwiresserveforsignal regenerationandtodrivethefan-out. (b)Anopticalpulsetrainisdistributedbywaveguidesacrossthedieto synchronouslyclockeightelectricalsub-circuits.Thepulsetrainiscoupledoutofafiberintoawaveguidebya gratingandanadiabatictaper.Multimodeinterference(MMI)couplersserveaspowerdividers.Photodetectors (PDs)convertthesignalintoanelectricalpulsetrain. be exceeded. In reality, the provided current and the gate capacity define a charging pro- cess and the higher the capacity or the smaller the provided current, the longer takes the chargingtime. Therefore,thehugeamountofclockreceiversrequiresnumerousrepeatedly inserteddevicestodrivethesesinks. Thesearecalledbufferorrepeaterandcanberealized by inverters. Starting with one clock source and ending up with a huge amount of sinks requires a clock distribution network (CDN) with several hierarchical levels. Numerous buffer stages are necessary for signal regeneration and to provide enough current for the fan-out to minimize the propagation delay [6]. These are placed where the load capacities aretoohigh,suchasinfrontofbranchesorwithinlongwires. CDNs are typically based on tree, spine or grid topologies or their hybrids [7]. In fig. 1.1(a) an H-tree based architecture is shown providing a global clock signal to 16 destina- tionssymmetricallydistributedacrossthedie. Buffersareindicatedastriangles. TheCDN evolution is highly associated with timing uncertainty of the clock distribution. One basic performance characteristic is the skew. It corresponds to a static deviation of the clock ar- rival times between two CDN leaves. Such delay differences are indicated in fig. 1.2 for four CDN branches. It can be induced by unsymmetrical CDNs [6, 8]. Fabrication tol- erances are responsible for wire dimension deviations and performance variations of each activecomponentofthebufferstagesorthesinks[6,8,9]. IntheCDNdesignprocess,skew
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