PCM186x 4-Channel or 2-Channel, 192-kHz, Audio ADCs datasheet

141 Pages·2017·2.3 MB·English

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PCM1860,PCM1861,PCM1862
PCM1863,PCM1864,PCM1865
Burr-Brown Audio
SLAS831D–MARCH2014–REVISEDMARCH2018
PCM186x 4-Channel or 2-Channel, 192-kHz, Audio ADCs
1 Features 2 Applications
• HighSNR Performance: • HomeTheaterandTV
1
– 110-dBSNR(PCM1861/63/65) • VoiceControlledDevices
– 103-dBSNR(PCM1860/62/64) • Bluetooth®Speaker
• ADCSampleRate(f )=8kHzto192kHz • MicrophoneArrayProcessors
S
• UpToFourIndependentADCChannelsAvailable
3 Description
• Single-Ended,2.1-V Full-Scale(FS)Input
RMS
The PCM186x family (PCM1860, PCM1861,
• Differential,4.2-V FSInput
RMS PCM1862, PCM1863, PCM1864, and PCM1865) of
• Hardware(HW)Control:PCM1860/61 audio front-end devices take a new approach to
• Software(SW)Control(I2CorSPI): audio-function integration to ease compliance with
PCM1862/63/64/65 European Ecodesign legislation, while enabling high-
performance end products at reduced cost. The
• SupportforUpToFourDigital Microphones
PCM186x support single-supply operation at 3.3 V,
(SW-ControlledDevices)
and offer an integrated programable gain amplifier
• ProgrammableGainAmplifier(PGA): (PGA) in a small package; this configuration makes it
– FixedGain:0dB,12dB,32dB feasibletoimplementsmaller andsmarterproductsat
areducedcost.
(PCM1860/61)
– SW-ControlledGain: –12dBto+32dB The PCM186x audio front end supports single-ended
(PCM1862/63/64/65) input levels from small-mV microphone inputs to 2.1-
V line inputs, without external resistor dividers.
• IntegratedHigh-PerformanceAudioPLL RMS
The front-end mixer (MIX), multiplexer (MUX), and
• Single3.3-VPower-SupplyOperation PGA also support differential (Diff), pseudo-
• PowerDissipationat3.3V: differential, and single-ended (SE) inputs, making
these devices an ideal interface for products that
– < 85mW (PCM1860/61/62/63)
require interference suppression. The PCM186x
– < 145mW(PCM1864/65)
integrate many system-level functions that assist or
• EnergysenseAudioContentDetectorforAuto replacesomeDSPfunctions.
SystemWakeupandSleep
An integrated band-gap voltage reference provides
• MasterorSlaveAudioInterface excellent PSRR, so that a dedicated analog 3.3-V rail
• AutomaticPGAClippingSuppressionControl maynotberequired.
• PCB-FootprintCompatibilityAcrossAllDevices
DeviceInformation(1)
PARTNUMBER PACKAGE BODYSIZE(NOM)
PCM186x TSSOP(30) 7.80mm×4.40mm
(1) Forallavailablepackages,seethepackageoptionaddendum
attheendofthedatasheet.
SimplifiedApplicationDiagram
IN DOUT
DOUT
MIC
BCK
PCM186x TMS320C5535 PCM5121 TPA3116
LRCK
SW mix
IN
LINE
BCK
PCM5100 TPA3116
LRCK
B
NS
IU
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.
PCM1860,PCM1861,PCM1862
PCM1863,PCM1864,PCM1865
SLAS831D–MARCH2014–REVISEDMARCH2018 www.ti.com
Table of Contents
1 Features.................................................................. 1 10.1 ApplicationInformation..........................................70
2 Applications........................................................... 1 10.2 TypicalApplications..............................................75
3 Description............................................................. 1 11 PowerSupplyRecommendations..................... 79
4 RevisionHistory..................................................... 2 11.1 Power-SupplyDistributionandRequirements......79
11.2 1.8-VSupport........................................................79
5 DeviceComparisonTable..................................... 7
11.3 BrownoutConditions.............................................79
6 PinConfigurationandFunctions......................... 8
11.4 Power-UpSequence.............................................80
7 Specifications....................................................... 12
11.5 LowestPower-DownModes.................................80
7.1 AbsoluteMaximumRatings....................................12
11.6 Power-OnResetSequencingTimingDiagram ....81
7.2 ESDRatings............................................................12
11.7 PowerConnectionExamples................................82
7.3 RecommendedOperatingConditions.....................12
11.8 FadeIn..................................................................83
7.4 ThermalInformation................................................12
12 Layout................................................................... 84
7.5 ElectricalCharacteristics:PGAandADCAC
Performance.............................................................13 12.1 LayoutGuidelines.................................................84
7.6 ElectricalCharacteristics:DC.................................14 12.2 LayoutExample....................................................85
7.7 ElectricalCharacteristics:DigitalFilter....................16 13 RegisterMaps...................................................... 85
7.8 TimingRequirements:ExternalClock.....................16 13.1 RegisterMapDescription......................................85
7.9 TimingRequirements:I2CControlInterface ..........17 13.2 RegisterMapSummary........................................86
7.10 TimingRequirements:SPIControlInterface .......18 13.3 Page0Registers.................................................89
7.11 TimingRequirements:AudioDataInterfacefor 13.4 Page1Registers...............................................129
SlaveMode..............................................................19 13.5 Page3Registers...............................................132
7.12 TimingRequirements:AudioDataInterfacefor 13.6 Page253Registers...........................................133
MasterMode............................................................20 14 DeviceandDocumentationSupport............... 134
7.13 TypicalCharacteristics..........................................21
14.1 DocumentationSupport......................................134
8 ParameterMeasurementInformation................23
14.2 RelatedLinks......................................................134
9 DetailedDescription............................................ 25 14.3 ReceivingNotificationofDocumentation
9.1 Overview.................................................................25 Updates..................................................................134
9.2 FunctionalBlockDiagrams.....................................25 14.4 CommunityResources........................................134
9.3 FeaturesDescription ..............................................28 14.5 Trademarks.........................................................134
9.4 DeviceFunctionalModes........................................60 14.6 ElectrostaticDischargeCaution..........................134
9.5 Programming...........................................................62 14.7 Glossary..............................................................134
10 ApplicationandImplementation........................ 70 15 Mechanical,Packaging,andOrderable
Information......................................................... 135
4 Revision History
NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion.
ChangesfromRevisionC(August2014)toRevisionD Page
• AddedPCM1860,PCM1862,andPCM1864andrelatedcontenttothisdatasheet;thesedeviceswerepreviouslyin
aseparatedatasheet(SLASE55A)....................................................................................................................................... 1
• Changedtitleforclarity........................................................................................................................................................... 1
• ChangedFeaturebulletstoincludenewdevices................................................................................................................... 1
• AddedFeaturebulletstoclarifyhardware-andsoftware-controlleddevices......................................................................... 1
• ChangedApplicationfrom"AutomotiveHeadUnits"to"VoiceControlledDevices".............................................................. 1
• ChangedDescriptionsectiontexttoclarify3.3-Vsupply,integratedPGA,andadditionalfront-endfeatures...................... 1
• ChangedSimplifiedApplicationDiagramtocombinetwopreviousfiguresintoonefigure................................................... 1
• DeletedTypPerformance(3.3-VSupply,–1dB-FSInput)table;redundantcontent............................................................ 7
• ChangedDeviceComparisonTable;updatedforclarity........................................................................................................ 7
• Changedreferencevoltageoutputdcouplingpointtypicalvaluefrom0.5VCCto0.5AVDDinVREFpindescription........9
• ChangedXO(pin9)typefrom"—"to"Digitaloutput"inbothPinFunctionstables ............................................................. 9
• Changed"latchenable"to"wordclock"inLRCKpindescription ......................................................................................... 9
• Changedreferencevoltageoutputdcouplingpointtypicalvaluefrom0.5VCCto0.5AVDDinVREFpindescription .....11
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Revision History (continued)
• Changed"latchenable"to"wordclock"inLRCKpindescription ....................................................................................... 11
• AddedoperatingambienttemperatureandjunctiontemperaturetoAbsoluteMaximumRatingstable.............................. 12
• Changedgroundvoltagedifferencesrangefrom"AGND,DGND"to"AGNDtoDGND" ................................................... 12
• Changedstoragetemperaturemaxvaluefrom125°Cto150°C.......................................................................................... 12
• ChangedCDMvaluefrom±1500Vto±750V..................................................................................................................... 12
• Changed"Operatingjunctiontemperaturerange"to"Operatingambienttemperature,T "inRecommended
A
OperatingConditionstable................................................................................................................................................... 12
• ChangedThermalCharacteristicstabletoThermalInformationtable................................................................................. 12
• ChangedElectricalCharacteristics:PrimaryPGAandADCperformancetoincludesecondaryADCperformance
data,anddeletedseparateElectricalCharacteristics:SecondaryADCPerformancetable ............................................... 13
• Addednewtablenotetoclarifytestconditionat32-dBPGAgain....................................................................................... 13
• Addedminvalueof85dBtoinputchannelsignal-to-noiseratiofor32dB......................................................................... 13
• Changedinputchannelsignal-to-noiseratiofor32dBtypicalvaluefrom93dBto90dB.................................................. 13
• Addedminvalueof–76dBtoinputchannelTHD+N,differentialinputfor32dB .............................................................. 13
• Deleted"perinputpin"and"outofphase"fromfull-scalevoltageinputparameterinElectricalCharacteristics................13
• Changedinputchannelsignal-to-noiseratio,single-endedinputvalueforPCM1865from110dBto106dB;
differentialconditionsusedpreviously.................................................................................................................................. 13
• Changed"EnergysenseDetectionThreshold"to"DefaultEnergysenseSignalDetectionThreshold"inElectrical
Characteristics,SecondaryADCPerformance.................................................................................................................... 13
• ChangedsecondaryADCsamplingratefrom"sameasaudiosamplingrate"tominof8kHzandmaxof192kHz.........13
• ChangedElectricalCharacteristics,DCconditionsfrommastertoslavemode;systemclockfrom256×f to512xf ....14
S S
• ChangedPOWERsectionoftheElectricalCharacteristics,DC;updatedsectionstructureforclarity................................ 14
• DeletedallrowswithXTALascondition;notrequiredfornormaloperation....................................................................... 14
• DeletedallrowswithPowerdown;notavalidoperatingmode ........................................................................................... 14
• ChangedAVDDcurrenttypvaluefor2-channel,3.3-V,activemodefrom16mAto18mA.............................................. 14
• ChangedTotalpowervaluefor2-channel,3.3V,sleepmodefrom24mWto17.6mW.................................................... 14
• ChangedDVDDcurrentfor2-channel,3.3V,standbymodefrom353µAto0.015mA..................................................... 14
• ChangedTotalpowerfor2-channel,3.3V,standbymodeforsoftwaredevicefrom0.59mWto0.64mW ...................... 14
• DVDDcurrentfor2-channel,3.3Vand1.8Vactivemodetypvaluefrom10µAto0.015mA.......................................... 14
• ChangedTotalpowerfor2-channel,3.3Vand1.8Vactivemodefrom68mWto69.2mW............................................. 14
• ChangedTotalpowerfor4-channel,3.3V,activemodefrom145mWto135.3mW ....................................................... 14
• ChangedTotalpowerfor4-channel,3.3Vand1.8V,activemodefrom128mWto117.3mW........................................ 15
• Deletedredundanttext"Validwithrecommendedvaluesonanalograils(AVDD,VREF,andsoon)"fromPSRR...........15
• Changed"HPFfrequencyresponse"to"HPF–3-dBcutofffrequency"inElectricalCharacteristics:DigitalFilter..............16
• AddedmaximumBCKfrequencyrowstoTimingRequirements,ExternalClocktable....................................................... 16
• ChangedallFFTplotXaxesfromlogscaletolinearscale................................................................................................. 21
• AddedFigure7..................................................................................................................................................................... 21
• ChangedFigure9................................................................................................................................................................. 21
• DeletedpreviousFigure11andFigure12........................................................................................................................... 21
• AddedFigure11................................................................................................................................................................... 21
• AddedFigure13................................................................................................................................................................... 22
• AddedFigure15................................................................................................................................................................... 22
• ChangedOverviewsectionforclarity................................................................................................................................... 25
• DeletedTerminologysection;movedcontenttoOverviewsection...................................................................................... 25
• AddedFeatureDescriptionsection,andmovedexistingcontenthere................................................................................ 28
• ChangedtextinAnalogFrontEndsectionforclarity........................................................................................................... 28
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Revision History (continued)
• ChangedMicBiassection;internalresistorisaterminatingresistor................................................................................... 29
• DeletedFigure21andFigure22fromMicBiassection...................................................................................................... 29
• AddednotestatingthatclocksarerequiredtoberunninginordertochangePGAintheProgrammableGain
Amplifiersection................................................................................................................................................................... 31
• AddedtexttoclarifydigitalPGAupdateuseinProgrammableGainAmplifiersection....................................................... 31
• Changednotetoclarifythatthefullscalemovesto4.2V whenindifferentialmodeattheendofthe
RMS
ProgrammableGainAmplifiersection.................................................................................................................................. 31
• AddednewparagraphtoendofStereoPCMSourcessection............................................................................................ 33
• ChangedFigure33;clocktreeupdatedandcorrected........................................................................................................ 36
• AddednewparagraphtotargetADC,DSP1andDSP2clockratesinDeviceClockDistributionandGenerationsection 36
• ChangedClockConfigurationandSelectionsection;relevanttohardware-controlleddevicesonly.................................. 37
• AddednewparagraphregardingregisterMST_SCK_SRCtoClockSourcesforSoftware-ControlledDevicessection....37
• Addednote("InMasterModeon..")toClockSourcesforSoftware-ControlledDevicessection........................................ 38
• ChangedTable7;updateddescriptionsforclarity............................................................................................................... 38
• Changed"CLK_DIV_MST_SCK"to"CLK_DIV_SCK_BCK"and"CLK_DIV_MST_BCK"to"CLK_DIV_BCK_LRCK"
inTable7.............................................................................................................................................................................. 38
• ChangedFigure34;clocktreeupdatedandcorrected........................................................................................................ 38
• Added"TargetClockRatesforADC,DSP#1andDSP#2"section..................................................................................... 39
• ChangedTable9;correctedPLLvaluesbyincreasingPandRby1,andcorrectedDSP1clockdividervalues..............40
• ChangedTable10;correctedPLLvaluesbyincreasingPandRby1,andcorrectedDSP1clockdividervalues............41
• ChangedTable12;correctedPLLvaluesbyincreasingPandRby1,andcorrectedtypoinDSP2columntitle..............43
• ChangedTable13;correctedPLLvaluesbyincreasingPandRby1,andcorrectedtypoinDSP2columntitle..............44
• Addedtext"Theclocktreemustalsobeset..."toSoftware-ControlledDevicesADCNon-AudioMCKPLLMode
section.................................................................................................................................................................................. 45
• ChangedPLLconditionforD=0000toshow1MHz≤(PLLCKIN/P)≤20MHzand1≤J≤63...................................... 45
• ChangedPLLconditionforD≠0000toshow6.667MHz≤(PLLCLKIN/P)≤20MHzand4≤J≤11............................. 45
• ChangedregisternumbersinSoftware-ControlledDevicesManualPLLCalculationsectiontoalignwiththeregister
numbersinTable14............................................................................................................................................................. 46
• ChangedClockHaltandErrorsection;clockerrormovedtoClockssection,andinterruptcapabilitydeleted...................46
• AddedChangingClockSourcesandSampleRatessection............................................................................................... 47
• ChangedSecondaryADC:EnergysenseandAnalogControlsection;energysensesignaldetectionnotavailablein
activemode.......................................................................................................................................................................... 48
• Changedtextfrom"controlsignalsupto1.65V"to"controlsignalsupto4.3V"intheSecondaryADCAnalogInput
Rangesection....................................................................................................................................................................... 49
• Changedsectiontitlefrom"SecondaryADCDCLevelChangeDetection"to"SecondaryADCControlsenseDC
LevelChangeDetection"...................................................................................................................................................... 49
• AddedtexttotheSecondaryADCControlsenseDCLevelChangeDetectionsection;controlsenseisavailablein
bothactiveandsleepmodes................................................................................................................................................ 49
• AddeddetailstotheSecondaryADCControlsenseDCLevelChangeDetectionsectionregardinghowtoread
simple8-bitvaluesfromthesecondaryADC....................................................................................................................... 49
• AddednewsecondparagraphtoEnergysensesection....................................................................................................... 50
• ChangedparagraphafterFigure38inEnergysenseSignalLossFlagsectionforclarity................................................... 51
• ChangedDigitalDecimationFilterssection;clarifiedtwodifferentHPFsinthedevice....................................................... 53
• ChangedtexttoclarifydigitalPGAupdateuseinDigitalPGAsection................................................................................ 53
• ChangedInterruptControllersection;deletedclockerrorasaninterruptsource................................................................ 56
• ChangedtextafterFigure44inInterruptControllersection;clarifiedINTpinsallhavesamelogicsignal......................... 56
• AddedshortdescriptionintheDINToggleDetectionsection.............................................................................................. 56
• AddedClearingInterruptssection........................................................................................................................................ 56
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Revision History (continued)
• ChangedDigitalAudioOutput2Configurationsection;DOUT2notavailableinTDMmode,onlyfor4-chdevices..........58
• AddedTimeDivisionMultiplex(TDMSupport)section........................................................................................................ 58
• ChangedlocationoftimingdiagramstoSpecificationssection,anddeletedInterfaceTimingsection............................... 59
• ChangedtextinBypassingtheInternalLDOtoReducePowerConsumptionsectiontoclarifyTDMmodewith1.8-V
IOVDDoperation.................................................................................................................................................................. 61
• Addedtext"TheI2Ccontrolport.."totheI2CInterfacesection............................................................................................ 64
• ChangedpinnumbersinTable22from"15,16,14"to"23,24,25"................................................................................... 64
• AddedRealWorldSoftwareConfigurationusingEnergySenseandControlsensesection................................................. 65
• AddedmoredetailtoProgrammingDSPCoefficientsonSoftware-ControlledDevicessection,andmovedtonew
location................................................................................................................................................................................. 68
• AddedDualPCM186xTDMFunctionalitysection............................................................................................................... 73
• AddednewparagraphtoendofAnalogFront-EndCircuitForSingle-Ended,Line-InApplicationssection.......................74
• Changed1.8-VSupportsection;clarifiedthatbothIOVDDandLDOmustbedrivenwith1.8Vin1.8-Vmode................ 79
• AddedBrownoutConditionssection..................................................................................................................................... 79
• Addedtestconditiontostep3inPowerUpSequencesection;(PLLrequires<250µs)................................................... 80
• ChangedLayoutsectionforclarity ...................................................................................................................................... 84
• DeletedoldFigure67,PCM1865EVMSignalPartitioning;redundant,andsameinformationshowninFigure74 ..........84
• AddedFigure75................................................................................................................................................................... 85
• Changed"0xFF"to"0xFE"inlastsentenceofRegisterMapDescriptionsection............................................................... 85
• Changedvaluesforregister3,bits6-0;changedfrom"RSV"tocorrectbitnames ........................................................... 86
• Changedbits4and3from1and0toRSV,respectively,inregister27............................................................................. 86
• Changedregister44(0x2C)fromreserved("RSV")toactualbitnames............................................................................. 87
• Changedregisters52and53toregisters51and52,respectively...................................................................................... 87
• ChangedTX_WLENbitoption00descriptionfrom"Reserved"to"32-bit"inPage0,register11...................................... 95
• ChangedGPIO0_FUNCfor001from"SPIMISO(Out:Default)"to"DigitalMICInput0(In)"andfor010from
"RESERVED"to"SPIMISO(Out)"inregister16................................................................................................................ 98
• Changed"DPGA"to"APGA"indescriptioncolumnforbits3,2,1,and0inregister25.................................................. 104
• ChangedDIV_NUMdefaultvalueinpage0,register33from"0000001"to"0000000"................................................. 106
• Changednamesanddescriptionsofmastermodeclockdividersinregisters37,38,and39forclarity.......................... 108
• Changed"Divider"to"Multiplier"inR[3:0]descriptionforregister42................................................................................ 110
• ChangedvaluesforR[3:0]from1,1/2,1/3,1/4,and1/16to1,2,3,4,and16,respectively .......................................... 110
• Changed"Divider"to"Multiplier"inJ[5:0]descriptionforregister43................................................................................ 111
• Changed"Divider"to"Multiplier"inD_LSB[7:0]descriptionforregister44....................................................................... 111
• Changed"Divider"to"Multiplier"inD_MSB[5:0]descriptionforregister45...................................................................... 111
• Changedregister52toregister51..................................................................................................................................... 114
• Changedregister53toregister52..................................................................................................................................... 115
• Changedbit3fromCLKERRtoRSVinregister96........................................................................................................... 123
• Deletedbit3fromCLKERRtoRSVinregister97............................................................................................................. 124
• Changeddefaultvaluesinpage1:register1forbits4,2,1,and0from"1"to"0",andupdateddescriptionsforclarity.129
ChangesfromRevisionB(March2014)toRevisionC Page
• Changed"terminal"to"pin"throughoutdatasheet................................................................................................................ 1
• Addedtablenoteaboutorderableaddendum........................................................................................................................ 1
• DeletedpackagedesignatorsfrompartnumbersinDeviceInformationtable....................................................................... 1
• Changed"THD+Nat-1dBFS"to"DifferentialInputTHD+Nat-1dBFS"............................................................................. 1
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• CorrectedpinnumbersinPinDescriptiontable..................................................................................................................... 9
• CorrectedpinnumbersinPinDescriptiontable-pin11isLDOandpin12isDGND........................................................ 11
• ChangedEnergysenseAccuracytypfrom1dBto3dB........................................................................................................ 13
• ChangedSecondaryADCAccuracyfrom10bitsto12bits ............................................................................................... 13
• AddedParameterMeasurementInformationsection .......................................................................................................... 23
• Addeddefaultvaluesforreservedregisters......................................................................................................................... 85
ChangesfromRevisionA(March2014)toRevisionB Page
• AddedPCM1861examplesystemdiagram........................................................................................................................... 1
• Changedtypicalperformancetable........................................................................................................................................ 1
• UpdatedPage3andPage253registers ............................................................................................................................ 85
ChangesfromOriginal(March2014)toRevisionA Page
• ChangedfromAdvanceInformationtoProductionDatastatus............................................................................................. 1
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5 Device Comparison Table
PARTNUMBER PCM1860 PCM1861 PCM1862 PCM1863 PCM1864 PCM1865
Controlmethod H/W I2CorSPI
Differential
SNRperformanceAweighted 103dB 110dB 103dB 110dB 103dB 110dB
data
Analogfrontend 2.1VRMSMUXwithfixedPGAgains 2.1VRMSMUX,MIX,PGAandauxiliaryADC
Simultaneouschannel
2 2 4
capability
Energysensesignaldetect Yes(fixedthreshold) Yes(programmablethreshold)
Energysensesignalloss No Yes(programmablethreshold)
Controlsense No Yes(programmablethreshold)
Interruptcontroller No Yes
Digitalmicrophonesupport No Yes(2) Yes(4)
ClockPLL BCKtogenerateinternalmasterclock Fullyprogrammable
Lowestpowerstandbymode
7.96mW 0.22mW
(1.8-VIOVDD)
Digitalmixingwithdigitaland
No Yes
analoginputs
Digitaloutputformats Left-justified,I2S Left-justified,right-justified,I2S,TDM
Energysensesignallossanddetect,controlsense,postPGAclipping,RXdigital
Interruptcapabilities Energysensesignaldetect
toggle
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6 Pin Configuration and Functions
DBTPackage:PCM1860andPCM1861
30-PinTSSOP
TopView
VINL2/VIN1M 1 30 VINR3/VIN3P
VINR2/VIN2M 2 29 VINL3/VIN4P
VINL1/VIN1P 3 28 VINR4/VIN3M
VINR1/VIN2P 4 27 VINL4/VIN4M
Mic Bias 5 26 MD0
VREF 6 25 MD1
AGND 7 24 MD3
AVDD 8 23 MD2
XO 9 22 MD4
XI 10 21 MD5
LDO 11 20 MD6
DGND 12 19 INT
DVDD 13 18 DOUT
IOVDD 14 17 BCK
SCKI 15 16 LRCK
Not to scale
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PinFunctions:PCM1860andPCM1861
PIN
TYPE DESCRIPTION
NO. NAME
1 VINL2/VIN1M Analoginput Analoginput2,L-channel(ordifferentialMinputforinput1)
2 VINR2/VIN2M Analoginput Analoginput2,R-channel(ordifferentialMinputforinput2)
3 VINL1/VIN1P Analoginput Analoginput1,L-channel(ordifferentialPinputforinput1)
4 VINR1/VIN2P Analoginput Analoginput1,R-channel(ordifferentialPinputforinput2)
5 MicBias Power Microphonebiasoutput
Power Referencevoltageoutputdecouplingpoint(typically,0.5AVDD).Connect1-µFcapacitor
6 VREF
fromthispintoAGND.
7 AGND Power Analogground
Power Analogpowersupply(typically,3.3V).Connect0.1-µFand10-µFcapacitorsfromthispin
8 AVDD
toAGND.
9 XO Digitaloutput Crystaloscillatoroutput
10 XI Digitalinput Crystaloscillatorinputormasterclockinput(1.8-VCMOSsignal)
Power Internallow-dropoutregulator(LDO)decouplingoutput,orexternal1.8-Vinputtobypass
11 LDO
LDO.Connect0.1-µFand10-µFcapacitorsfromthispintoDGND.
12 DGND Power Digitalground
Power Digitalpowersupply(typically,3.3V).Connect0.1-µFand10-µFcapacitorsfromthispinto
13 DVDD
DGND.
14 IOVDD Power PowersupplyforI/Ovoltages(typically,3.3Vor1.8V).
15 SCKI Digitalinput CMOSlevel(3.3V)masterclockinput
Digital Audiodatawordclock(leftrightclock)input/output(1)
16 LRCK
input/output
Digital Audiodatabitclockinput/output(1)
17 BCK
input/output
18 DOUT Digitaloutput Audiodatadigitaloutput
19 INT Analogoutput Interruptoutput(foranaloginputdetection).Pullhighforactivemode,pulllowforidle.
Analoginput AnalogMUXandgainselectionusingMD6,MD5,andMD2pins,respectively:
000:SECh1(VINL1andVINR1)
001:SECh2(VINL2andVINR2)
010:SECh3(VINL3andVINR3)
20 MD6 011:SECh4(VINL4andVINR4)
100:SECh4with12-dBgain
101:SECh4with32-dBgain
110:DiffCh1(VIN1PandVIN1M,VIN2PandVIN2M)
111:DiffCh2(VIN3PandVIN3M,VIN4PandVIN4M)with12-dBgain
21 MD5 Analoginput AnalogMUXandgainselection(seeMD6pinfordescription)
22 MD4 Analoginput Audioformat:high=left-justified,low=I2S
23 MD2 Analoginput AnalogMUXandgainselection(seeMD6pinfordescription)
24 MD3 DigitalInput Filterselect:0=FIRdecimationfilter,1=IIRlowlatencydecimationfilter
Analoginput AudiointerfacemodeselectionusingMD1andMD0pins,respectively:
00:Slavemode,256×f ,384×f ,512×f autodetect
S S S
25 MD1 01:Mastermode(512×f )
S
10:Mastermode(384×f )
S
11:Mastermode(256×f )
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26 MD0 Analoginput Audiointerfacemodeselection(seeMD1pinfordescription)
27 VINL4/VIN4M Analoginput Analoginput4,L-channel(ordifferentialMinputforinput4)
28 VINR4/VIN3M Analoginput Analoginput4,R-channel(ordifferentialMinputforinput3)
29 VINL3/VIN4P Analoginput Analoginput3,L-channel(ordifferentialPinputforinput4)
30 VINR3/VIN3P Analoginput Analoginput3,R-channel(ordifferentialPinputforinput3)
(1) Schmitttriggerinputwithinternalpull-down(50kΩ,typically).
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ProductFolderLinks:PCM1860 PCM1861 PCM1862PCM1863 PCM1864 PCM1865
PCM1860,PCM1861,PCM1862
PCM1863,PCM1864,PCM1865
SLAS831D–MARCH2014–REVISEDMARCH2018 www.ti.com
DBTPackage:PCM1862,PCM1863,PCM1864,andPCM1865
30-PinTSSOP
TopView
VINL2/VIN1M 1 30 VINR3/VIN3P
VINR2/VIN2M 2 29 VINL3/VIN4P
VINL1/VIN1P 3 28 VINR4/VIN3M
VINR1/VIN2P 4 27 VINL4/VIN4M
Mic Bias 5 26 MD0
VREF 6 25 MS/AD
AGND 7 24 MC/SCL
AVDD 8 23 MOSI/SDA
XO 9 22 MISO/GPIO0/DMIN2
XI 10 21 GPIO1/INTA/DMIN
LDO 11 20 GPIO2/INTB/DMCLK
DGND 12 19 GPIO3/INTC
DVDD 13 18 DOUT
IOVDD 14 17 BCK
SCKI 15 16 LRCK
Not to scale
NOTE:TheDMIN2optionforpin22isonlyavailableonthePCM1864andPCM1865devices.
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ProductFolderLinks:PCM1860 PCM1861 PCM1862PCM1863 PCM1864 PCM1865