PCI-X Protocol Addendum to the PCI Local Bus Specification Revision 2.0

382 Pages·2002·3.7 MB·English

by  Bill Haffner

PCI-X Protocol Addendum to
the PCI Local Bus
Specification
Revision 2.0
July 29, 2002
PCI-X PROTOCOL ADDENDUM TO THE PCI LOCAL BUS SPECIFICATION, REV. 2.0
REVISION REVISION HISTORY DATE
1.0 Initial release. 9/22/99
1.0a Clarifications and typographical corrections. 7/24/00
1.0b Clarifications and errata. 7/29/02
Added Mode 2 with 1.5V signaling, source-synchronous
clocking of two or four subphases per clock. Added ECC,
2.0 7/29/02
device ID messaging, and 16-bit interface. Incorporated the
PCI-X slot and card identification ECN

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in this document, nor does the PCI-SIG make a commitment to update the information
contained herein.
Contact the PCI-SIG office to obtain the latest revision of the specification.
Questions regarding the PCI-X Addendum or membership in the PCI-SIG may be
forwarded to:
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DISCLAIMER
This PCI-X Addendum is provided “as is” with no warranties whatsoever, including any
warranty of merchantability, noninfringement, fitness for any particular purpose, or any
warranty otherwise arising out of any proposal, specification, or sample. The PCI-SIG
disclaims all liability for infringement of proprietary rights, relating to use of information in
this specification. No license, express or implied, by estoppel or otherwise, to any
intellectual property rights is granted herein.

All product names are trademarks, registered trademarks, or servicemarks of their respective
owners.

Copyright © 1999, 2000, 2002 PCI-SIG
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PCI-X PROTOCOL ADDENDUM TO THE PCI LOCAL BUS SPECIFICATION, REV. 2.0
Contents
PREFACE........................................................................................................................19
1. INTRODUCTION...................................................................................................21
1.1. DOCUMENTATION CONVENTIONS......................................................................25
1.2. TERMS AND ABBREVIATIONS.............................................................................27
1.3. FIGURE LEGEND................................................................................................37
1.4. COMPARISON OF TRANSACTIONS IN DIFFERENT BUS MODES............................39
1.5. BURST AND DWORD TRANSACTIONS...............................................................44
1.6. WAIT STATES.....................................................................................................46
1.7. SPLIT TRANSACTIONS........................................................................................46
1.8. BUS WIDTH........................................................................................................46
1.9. COMPATIBILITY AND SYSTEM INITIALIZATION..................................................47
1.10. DEVICE ID MESSAGING.................................................................................48
1.11. PCI-X MODE 2 BUS DRIVE AND TURN AROUND...........................................48
1.12. SUMMARY OF PROTOCOL RULES ...................................................................49
1.12.1. General Bus Rules.....................................................................................49
1.12.2. Initiator Rules...........................................................................................51
1.12.3. Target Rules..............................................................................................53
1.12.4. Bus Arbitration Rules................................................................................54
1.12.5. Configuration Transaction Rules..............................................................56
1.12.6. Parity and ECC Error Protection Rules...................................................56
1.12.7. Bus Width Rules........................................................................................58
1.12.8. Split Transaction Rules.............................................................................59
1.13. PCI-X TRANSACTION FLOW..........................................................................60
2. PCI-X TRANSACTION PROTOCOL.................................................................63
2.1. SEQUENCES........................................................................................................63
2.2. ALLOWABLE DISCONNECT BOUNDARIES AND BUFFER SIZE..............................64
2.3. DEPENDENCIES BETWEEN ADDRESS, BYTE COUNT, AND BYTE ENABLES.........66
2.4. PCI-X COMMAND ENCODING............................................................................70
2.5. ATTRIBUTES.......................................................................................................72
2.6. BURST TRANSACTIONS......................................................................................76
2.6.1. Burst Push Transactions...........................................................................78
2.6.1.1. Common-Clock Burst Push Transactions.........................................81
2.6.1.2. Source-Synchronous Burst Push Transactions.................................85
2.6.2. Burst Reads...............................................................................................89
2.7. DWORD TRANSACTIONS..................................................................................95
2.7.1. DWORD Memory and I/O Transactions...................................................96
2.7.2. Configuration Transactions......................................................................97
2.7.2.1. Configuration Transaction Timing...................................................98
2.7.2.2. Configuration Transaction Address and Attributes........................100
2.7.3. Special Cycle Transactions.....................................................................103
2.7.4. Interrupt Acknowledge Transactions......................................................105
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PCI-X PROTOCOL ADDENDUM TO THE PCI LOCAL BUS SPECIFICATION, REV. 2.0
2.8. DEVICE SELECT TIMING...................................................................................105
2.8.1. Common-Clock Burst Push and DWORD Write Transactions..............106
2.8.2. Source-Synchronous Burst Push Transactions.......................................109
2.8.3. Reads.......................................................................................................110
2.9. WAIT STATES...................................................................................................113
2.9.1. Target Initial Latency.............................................................................113
2.9.2. Wait States on Burst Push and DWORD Write Transactions................116
2.9.3. Wait States on Reads...............................................................................122
2.10. SPLIT TRANSACTIONS..................................................................................127
2.10.1. Basic Split Transaction Requirements....................................................127
2.10.2. Split Completion......................................................................................130
2.10.3. Split Completion Address........................................................................132
2.10.4. Completer Attributes...............................................................................134
2.10.5. Requirements for Accepting Split Completions......................................137
2.10.6. Split Completion Messages.....................................................................137
2.10.6.1. Write Completion Message Class...................................................139
2.10.6.2. Completer Error Message Class......................................................139
2.11. TRANSACTION TERMINATION......................................................................141
2.11.1. Initiator Termination..............................................................................142
2.11.1.1. Initiator Disconnection or Satisfaction of Byte Count....................142
2.11.1.2. Master-Abort Termination..............................................................146
2.11.2. Target Termination and Data Phase Signaling......................................147
2.11.2.1. Single Data Phase Disconnection...................................................148
2.11.2.2. Disconnection at Next ADB...........................................................151
2.11.2.3. Retry Termination...........................................................................154
2.11.2.4. Split Response Termination............................................................155
2.11.2.5. Target-Abort Termination...............................................................156
2.12. BUS WIDTH..................................................................................................158
2.12.1. 64-Bit and 32-Bit Bus Width...................................................................158
2.12.1.1. Address Width................................................................................159
2.12.1.2. Attribute Width...............................................................................162
2.12.1.3. Data Transfer Width.......................................................................162
2.12.2. 16-Bit Bus Width.....................................................................................171
2.12.2.1. Address Width................................................................................173
2.12.2.2. Attribute Width...............................................................................174
2.12.2.3. Data Transfer Width.......................................................................174
2.12.2.3.1. Burst Transactions on a 16-Bit Bus...........................................174
2.12.2.3.2. DWORD Transactions on a 16-Bit Bus.....................................179
2.12.2.3.3. Target Data Phase Signaling on a 16-Bit Bus............................180
2.13. REQUIRED ACCEPTANCE AND COMPLETION RULES FOR SIMPLE DEVICES...182
2.14. QUIESCING DEVICE OPERATION...................................................................184
2.15. SNOOPING PCI-X TRANSACTIONS...............................................................185
2.16. DEVICE ID MESSAGING...............................................................................185
2.16.1. Device ID Message Address...................................................................188
2.16.2. Device ID Message Attributes................................................................190
2.16.3. Device ID Message Format....................................................................191
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PCI-X PROTOCOL ADDENDUM TO THE PCI LOCAL BUS SPECIFICATION, REV. 2.0
2.16.3.1. Vendor-Defined Message Class......................................................191
2.16.3.2. Reserved Message Classes..............................................................191
2.17. PCI-X MODE 2 BUS DRIVE AND TURN-AROUND........................................191
3. DEVICE REQUIREMENTS...............................................................................193
3.1. SOURCE SAMPLING..........................................................................................193
3.2. MESSAGE-SIGNALED INTERRUPTS...................................................................194
3.3. PCI POWER MANAGEMENT.............................................................................194
4. ARBITRATION....................................................................................................197
4.1. ARBITRATION PARKING AND BUS TURN-AROUND...........................................197
4.1.1. PCI-X Mode 1 Arbitration Parking........................................................197
4.1.2. PCI-X Mode 2 Bus Drive and Turn-Around...........................................198
4.1.2.1. Bus Turn-Around Alert and Bus Turn-Around..............................199
4.1.2.2. Interface Low-Power State.............................................................203
4.1.2.3. Bus State Initialization....................................................................207
4.2. ARBITRATION SIGNALING PROTOCOL..............................................................207
4.2.1. Device Requirements..............................................................................209
4.2.2. Arbiter Requirements..............................................................................210
4.3. ARBITER COORDINATION WITH THE PCI HOT-PLUG CONTROLLER.................212
4.4. LATENCY TIMER..............................................................................................212
5. ERROR FUNCTIONS..........................................................................................215
5.1. BUS ERROR PROTECTION.................................................................................215
5.1.1. Parity Mode............................................................................................216
5.1.1.1. Parity Generation............................................................................217
5.1.1.2. Parity Checking...............................................................................217
5.1.1.3. Parity Timing..................................................................................218
5.1.2. ECC Mode...............................................................................................222
5.1.2.1. ECC Basics and Definitions............................................................223
5.1.2.2. ECC Signature Generation..............................................................225
5.1.2.2.1. Seven-Bit ECC Description.........................................................226
5.1.2.2.2. Eight-Bit ECC Description..........................................................228
5.1.2.2.3. Phase Protection Description.......................................................230
5.1.2.3. ECC Checking................................................................................233
5.1.2.4. ECC Timing....................................................................................235
5.1.3. ECC on 16-Bit Transfers........................................................................238
5.1.4. Driving SERR#........................................................................................243
5.2. ERROR HANDLING AND FAULT TOLERANCE....................................................243
5.2.1. Uncorrectable Data Errors.....................................................................243
5.2.1.1. Devices and Software Drivers that Support Recovery from
Uncorrectable Data Errors..................................................................................244
5.2.1.2. Devices or Software Drivers That Do Not Support Recovery from
Uncorrectable Data Errors..................................................................................245
5.2.1.3. Uncorrectable Data Errors in Split Response for Read Transactions
245
5.2.2. Target-Abort and Master-Abort Exceptions...........................................246
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PCI-X PROTOCOL ADDENDUM TO THE PCI LOCAL BUS SPECIFICATION, REV. 2.0
5.2.3. Uncorrectable Address and Attribute Errors.........................................246
5.2.4. Split Transaction Errors.........................................................................247
5.2.5. Corrupted or Unexpected Split Completions..........................................248
5.2.6. Reporting Split Completion Error Messages..........................................249
6. SYSTEM INTEROPERABILITY AND INITIALIZATION...........................251
6.1. INTEROPERABILITY..........................................................................................251
6.1.1. Device and Add-In Card Interoperability Requirements........................251
6.1.2. System Interoperability Requirement......................................................252
6.1.3. Interoperability Matrix...........................................................................253
6.2. INITIALIZATION REQUIREMENTS......................................................................254
6.2.1. Device and Add-in Card Initialization Requirements.............................257
6.2.2. System Initialization Requirements.........................................................260
6.2.3. Mode and Frequency Initialization Sequence.........................................261
6.2.3.1. System Power-Up...........................................................................261
6.2.3.2. Hot Insertion in a PCI-X System....................................................263
6.2.4. Device Number and Bus Number Initialization......................................264
7. CONFIGURATION SPACE FOR TYPE 00H HEADER DEVICES.............267
7.1. PCI-X EFFECTS ON CONVENTIONAL CONFIGURATION SPACE HEADER...........267
7.2. PCI-X CAPABILITIES LIST ITEM......................................................................269
7.2.1. PCI-X ID.................................................................................................270
7.2.2. Next Capabilities Pointer........................................................................270
7.2.3. PCI-X Command Register.......................................................................270
7.2.4. PCI-X Status Register.............................................................................273
7.2.5. ECC Control and Status Register...........................................................280
7.2.6. ECC Address Registers...........................................................................283
7.2.7. ECC Attribute Register...........................................................................284
7.3. USE OF I/O SPACE............................................................................................284
7.4. MODE 2 CONFIGURATION SPACE.....................................................................284
7.4.1. Enhanced Configuration Access Mechanism..........................................285
7.4.2. Extended Capabilities List Items............................................................286
8. PCI-X BRIDGE ADDITIONAL DESIGN REQUIREMENTS.......................289
8.1. SUMMARY OF KEY REQUIREMENTS.................................................................289
8.2. PCI-X BRIDGES AND APPLICATION BRIDGES..................................................290
8.3. ADDRESS DECODING........................................................................................291
8.4. BRIDGE OPERATION.........................................................................................291
8.4.1. Buffer Size Requirements........................................................................291
8.4.2. Forwarding Split Transactions...............................................................293
8.4.2.1. Split Completion Buffer Allocation................................................295
8.4.2.2. Immediate Completion by the Completer.......................................298
8.4.2.3. Split Request Capacity Recommendations.....................................299
8.4.3. Connecting PCI-X and Conventional PCI Interfaces.............................300
8.4.3.1. Conventional Requester, PCI-X Completer....................................300
8.4.3.1.1. Conventional PCI to PCI-X Command Translation and Byte Count
Generation 300
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PCI-X PROTOCOL ADDENDUM TO THE PCI LOCAL BUS SPECIFICATION, REV. 2.0
8.4.3.1.2. Delayed Transaction to Split Transaction Conversion................302
8.4.3.1.3. Conventional PCI to PCI-X Attribute Creation...........................302
8.4.3.2. PCI-X Requester, Conventional Completer....................................303
8.4.3.2.1. PCI-X to Conventional PCI Command Translation....................303
8.4.3.2.2. Split Transaction to Delayed Transaction Conversion................304
8.4.3.2.3. Creating a Split Completion.........................................................304
8.4.4. Transaction Ordering and Passing Rules for Bridges............................305
8.4.5. Required Acceptance Rules for Bridges.................................................308
8.4.6. Forwarding Memory Write Transactions...............................................309
8.4.7. Forwarding Device ID Messages...........................................................312
8.5. EXCLUSIVE ACCESS.........................................................................................313
8.5.1. Starting an Exclusive Access..................................................................314
8.5.2. Continuing an Exclusive Access.............................................................317
8.5.3. Accessing a Locked Bridge.....................................................................318
8.5.4. Completing an Exclusive Access.............................................................319
8.6. PCI-X BRIDGE (TYPE 01H) CONFIGURATION REGISTERS................................320
8.6.1. PCI-X Effects on Conventional Bridge Configuration Space Header....320
8.6.2. PCI-X Bridge Capabilities List Item.......................................................321
8.6.2.1. PCI-X ID.........................................................................................323
8.6.2.2. Next Capabilities Pointer................................................................323
8.6.2.3. PCI-X Secondary Status Register...................................................323
8.6.2.4. PCI-X Bridge Status Register.........................................................326
8.6.2.5. Upstream Split Transaction Register..............................................331
8.6.2.6. Downstream Split Transaction Register.........................................332
8.6.2.7. PCI-X Bridge ECC Control and Status Register............................334
8.6.2.8. PCI-X Bridge ECC Address Registers...........................................338
8.6.2.9. PCI-X Bridge ECC Attribute Register............................................338
8.7. PCI-X BRIDGE ERROR SUPPORT......................................................................339
8.7.1. PCI-X Originating Bus...........................................................................339
8.7.1.1. Uncorrectable Data Errors..............................................................339
8.7.1.1.1. Uncorrectable Data Error on an Immediate Read........................339
8.7.1.1.2. Uncorrectable Data Error on a Non-Posted Write.......................340
8.7.1.1.3. Uncorrectable Data Error on a Split Completion.........................340
8.7.1.1.4. Uncorrectable Data Error on a Posted Write...............................341
8.7.1.2. Master-Abort...................................................................................341
8.7.1.3. Target-Abort...................................................................................342
8.7.2. Conventional PCI Originating Bus.........................................................344
8.7.3. Forwarding Data-Phase Parity and ECC Errors...................................345
8.7.3.1. Parity to Parity................................................................................345
8.7.3.2. ECC to ECC....................................................................................346
8.7.3.3. Parity to ECC..................................................................................347
8.7.3.4. ECC to Parity..................................................................................349
8.7.4. Bridge Internal Error Protection............................................................351
8.8. PCI-X BRIDGE ERROR CLASS SPLIT COMPLETION MESSAGE..........................352
8.9. SECONDARY BUS MODE AND FREQUENCY INITIALIZATION SEQUENCE...........353
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PCI-X PROTOCOL ADDENDUM TO THE PCI LOCAL BUS SPECIFICATION, REV. 2.0
A. APPENDIX—CONVENTIONAL PCI VS. PCI-X PROTOCOL RULE
COMPARISON.............................................................................................................355
B. APPENDIX—USE OF RELAXED ORDERING..............................................361
B.1. RELAXED WRITE ORDERING............................................................................362
B.2. RELAXED READ ORDERING.............................................................................362
B.3. CO-LOCATION OF PAYLOAD AND CONTROL.....................................................363
B.4. OTHER USES OF RELAXED ORDERING..............................................................364
B.5. I2O USAGE MODELS........................................................................................364
B.5.1. I O Messaging Protocol Operation........................................................365
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B.5.2. Message Delivery with the Push Model..................................................365
B.5.3. Message Delivery with the Pull Model...................................................366
B.5.4. Message Delivery with the Outbound Option.........................................367
B.5.5. Message Delivery with Peer to Peer.......................................................368
C. APPENDIX—MINIMAL PCI POWER MANAGEMENT SUPPORT..........369
D. APPENDIX—SETTING PERFORMANCE REGISTERS..............................371
D.1. SETTING THE MAXIMUM MEMORY READ BYTE COUNT REGISTER..................371
D.2. OPTIMIZING THE SPLIT TRANSACTION COMMITMENT LIMITS IN PCI-X BRIDGES
371
E. APPENDIX—ECC APPLICATIONS................................................................373
E.1. ECC IN MODE 1...............................................................................................373
E.1.1. Mode 1 ECC in Embedded Systems........................................................373
E.1.2. Mode 1 ECC in Slot-Based Systems........................................................373
E.2. USE OF PCI-X ECC IN MEMORY APPLICATIONS.............................................374
E.2.1. Features for Memory ECC Applications................................................374
E.2.2. Adjustments for Memory ECC Applications...........................................375
E.3. CONVERTING BETWEEN ECC WIDTHS............................................................376
E.3.1. Combining ECC Signatures that Include Phase/Error Signatures........376
E.3.2. Handling Combined Eight-Bit ECCs in Recovery Software...................378
E.4. DETECTING SINGLE-PIN PROBLEMS ON THE 16-BIT BUS.................................379
E.5. ECC CHECK/CORRECT LOGIC EXAMPLE.........................................................380

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PCI-X PROTOCOL ADDENDUM TO THE PCI LOCAL BUS SPECIFICATION, REV. 2.0
Figures
FIGURE 1-1: FIGURE LEGEND, MODE 1............................................................................37
FIGURE 1-2: FIGURE LEGEND, MODE 2............................................................................38
FIGURE 1-3: TYPICAL CONVENTIONAL PCI WRITE TRANSACTION...................................40
FIGURE 1-4: TYPICAL PCI-X MODE 1 WRITE TRANSACTION...........................................41
FIGURE 1-5: TYPICAL PCI-X 266 (MODE 2) BURST WRITE TRANSACTION.....................42
FIGURE 1-6: TYPICAL PCI-X 533 (MODE 2) BURST WRITE TRANSACTION.....................42
FIGURE 1-7: TYPICAL 16-BIT PCI-X 266 (MODE 2) BURST WRITE TRANSACTION..........43
FIGURE 1-8: TYPICAL 16-BIT PCI-X 533 (MODE 2) BURST WRITE TRANSACTION..........43
FIGURE 1-9: TRANSACTION FLOW WITHOUT CROSSING A BRIDGE...................................61
FIGURE 1-10: TRANSACTION FLOW ACROSS A BRIDGE....................................................62
FIGURE 2-1: BURST TRANSACTION REQUESTER ATTRIBUTE BIT ASSIGNMENTS..............72
FIGURE 2-2: DWORD TRANSACTION REQUESTER ATTRIBUTE BIT ASSIGNMENTS..........72
FIGURE 2-3: COMMON-CLOCK BURST MEMORY WRITE TRANSACTION WITH NO TARGET
INITIAL WAIT STATES, MODE 1.................................................................................82
FIGURE 2-4: COMMON-CLOCK BURST MEMORY WRITE TRANSACTION WITH TWO TARGET
INITIAL WAIT STATES, MODE 1.................................................................................83
FIGURE 2-5: COMMON-CLOCK BURST MEMORY WRITE TRANSACTION WITH NO TARGET
INITIAL WAIT STATES, MODE 2.................................................................................84
FIGURE 2-6: COMMON-CLOCK BURST MEMORY WRITE TRANSACTION WITH TWO TARGET
INITIAL WAIT STATES, MODE 2.................................................................................85
FIGURE 2-7: SOURCE-SYNCHRONOUS BURST PUSH TRANSACTION WITH NO TARGET
INITIAL WAIT STATES................................................................................................87
FIGURE 2-8: SOURCE-SYNCHRONOUS BURST PUSH TRANSACTION WITH TWO TARGET
INITIAL WAIT STATES................................................................................................88
FIGURE 2-9: BURST MEMORY READ TRANSACTION WITH NO TARGET INITIAL WAIT
STATES, MODE 1.......................................................................................................91
FIGURE 2-10: BURST MEMORY READ TRANSACTION WITH TARGET INITIAL WAIT STATES,
MODE 1.....................................................................................................................92
FIGURE 2-11: BURST MEMORY READ TRANSACTION WITH NO TARGET INITIAL WAIT
STATES, MODE 2.......................................................................................................93
FIGURE 2-12: BURST MEMORY READ TRANSACTION WITH TARGET INITIAL WAIT STATES,
MODE 2.....................................................................................................................94
FIGURE 2-13: I/O WRITE TRANSACTION WITH NO WAIT STATES AND DATA TRANSFER,
MODE 1.....................................................................................................................96
FIGURE 2-14: DWORD MEMORY OR I/O READ WITH TWO TARGET INITIAL WAIT STATES
AND DATA TRANSFER, MODE 1.................................................................................96
FIGURE 2-15: I/O WRITE TRANSACTION WITH NO WAIT STATES AND DATA TRANSFER,
MODE 2.....................................................................................................................97
FIGURE 2-16: DWORD MEMORY OR I/O READ WITH TWO TARGET INITIAL WAIT STATES
AND DATA TRANSFER, MODE 2.................................................................................97
FIGURE 2-17: CONFIGURATION WRITE TRANSACTION, MODE 1......................................99
FIGURE 2-18: CONFIGURATION READ TRANSACTION, MODE 1........................................99
FIGURE 2-19: CONFIGURATION WRITE TRANSACTION, MODE 2....................................100
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PCI-X PROTOCOL ADDENDUM TO THE PCI LOCAL BUS SPECIFICATION, REV. 2.0
FIGURE 2-20: CONFIGURATION READ TRANSACTION, MODE 2......................................100
FIGURE 2-21: CONFIGURATION TRANSACTION ADDRESS FORMAT.................................101
FIGURE 2-22: TYPE 0 CONFIGURATION TRANSACTION REQUESTER ATTRIBUTE BIT
ASSIGNMENTS..........................................................................................................103
FIGURE 2-23: SPECIAL CYCLE, MODE 1.........................................................................104
FIGURE 2-24: SPECIAL CYCLE, MODE 2..........................................................................104
FIGURE 2-25: DEVSEL# TIMING, SINGLE ADDRESS CYCLE, 64- OR 32-BIT BUS..........106
FIGURE 2-26: COMMON-CLOCK BURST MEMORY WRITE WITH DEVSEL# DECODE A AND
NO INITIAL WAIT STATES, MODE 1.........................................................................107
FIGURE 2-27: COMMON-CLOCK BURST MEMORY WRITE WITH DEVSEL# DECODE B AND
NO INITIAL WAIT STATES, MODE 1.........................................................................107
FIGURE 2-28: COMMON-CLOCK BURST MEMORY WRITE WITH DEVSEL# DECODE C AND
NO INITIAL WAIT STATES, MODE 1.........................................................................108
FIGURE 2-29: COMMON-CLOCK BURST MEMORY WRITE WITH SUBTRACTIVE DEVSEL#
DECODE AND NO INITIAL WAIT STATES, MODE 1...................................................108
FIGURE 2-30: COMMON-CLOCK BURST MEMORY WRITE WITH DEVSEL# DECODE B AND
NO INITIAL WAIT STATES, MODE 2.........................................................................108
FIGURE 2-31: SOURCE-SYNCHRONOUS BURST PUSH TRANSACTION WITH DEVSEL#
DECODE B AND NO INITIAL WAIT STATES..............................................................109
FIGURE 2-32: SOURCE-SYNCHRONOUS BURST PUSH TRANSACTION WITH DEVSEL#
DECODE C AND NO INITIAL WAIT STATES..............................................................110
FIGURE 2-33: SOURCE-SYNCHRONOUS BURST PUSH TRANSACTION WITH SUBTRACTIVE
DEVSEL# DECODE AND NO INITIAL WAIT STATES................................................110
FIGURE 2-34: BURST READ WITH DEVSEL# DECODE A AND NO INITIAL WAIT STATES,
MODE 1...................................................................................................................111
FIGURE 2-35: BURST READ WITH DEVSEL# DECODE B AND NO INITIAL WAIT STATES,
MODE 1...................................................................................................................111
FIGURE 2-36: BURST READ WITH DEVSEL# DECODE C AND NO INITIAL WAIT STATES,
MODE 1...................................................................................................................112
FIGURE 2-37: BURST READ WITH SUBTRACTIVE DEVSEL# DECODE AND NO INITIAL
WAIT STATES, MODE 1............................................................................................112
FIGURE 2-38: BURST READ WITH DEVSEL# DECODE B AND NO INITIAL WAIT STATES,
MODE 2...................................................................................................................112
FIGURE 2-39: BURST MEMORY WRITE TRANSACTION WITH DEVSEL# DECODE A AND
TWO INITIAL WAIT STATES, MODE 1......................................................................117
FIGURE 2-40: BURST MEMORY WRITE TRANSACTION WITH DEVSEL# DECODE A AND
FOUR INITIAL WAIT STATES, MODE 1.....................................................................117
FIGURE 2-41: BURST MEMORY WRITE TRANSACTION WITH DEVSEL# DECODE B AND
TWO INITIAL WAIT STATES, MODE 1......................................................................118
FIGURE 2-42: BURST MEMORY WRITE TRANSACTION WITH DEVSEL# DECODE B AND
FOUR INITIAL WAIT STATES, MODE 1.....................................................................118
FIGURE 2-43: BURST MEMORY WRITE TRANSACTION WITH DEVSEL# DECODE C AND
TWO INITIAL WAIT STATES, MODE 1......................................................................119
FIGURE 2-44: BURST MEMORY WRITE TRANSACTION WITH DEVSEL# DECODE C AND
FOUR INITIAL WAIT STATES, MODE 1.....................................................................119
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