PCI Local Bus Specification, Revision 3.0

344 Pages·2002·2.96 MB·English

PCI Local Bus Specification
Revision 3.0
August 12, 2002
PCISPECIFICATIONS
REVISION REVISIONHISTORY DATE
1.0 Originalissue 6/22/92
2.0 Incorporatedconnectorandadd-incardspecification 4/30/93
2.1 Incorporatedclarificationsandadded66MHzchapter 6/1/95
2.2 IncorporatedECNsandimprovedreadability 12/18/98
2.3 IncorporatedECNs,errata,anddeleted5voltonlykeyed 3/29/02
add-incards
3.0 Removedsupportforthe5.0voltkeyedsystemboard 8/12/02
connector

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in this document, nor does PCI-SIG make a commitment to update the information
contained herein.
Contact the PCI-SIG office to obtain the latest revision of the specification.
Questions regarding this PCI specification or membership in PCI-SIG may be forwarded to:
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Phone: [phone] (Inside the U.S.)
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DISCLAIMER
This PCI Local Bus Specification is provided "as is" with no warranties whatsoever,
including any warranty of merchantability, noninfringement, fitness for any particular
purpose, or any warranty otherwise arising out of any proposal, specification, or sample.
PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of
information in this specification. No license, express or implied, by estoppel or otherwise,
to any intellectual property rights is granted herein.
All product names are trademarks, registered trademarks, or servicemarks of their respective
owners.

Copyright © 1992, 1993, 1995, 1998, 2002 PCI-SIG
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Contents
PREFACE.........................................................................................................................13
SPECIFICATIONSUPERSEDESEARLIERDOCUMENTS......................................................13
INCORPORATIONOFENGINEERINGCHANGENOTICES(ECNS).......................................13
DOCUMENTCONVENTIONS............................................................................................14
1. INTRODUCTION.....................................................................................................15
1.1. SPECIFICATIONCONTENTS.................................................................................15
1.2. MOTIVATION......................................................................................................15
1.3. PCILOCALBUSAPPLICATIONS.........................................................................16
1.4. PCILOCALBUSOVERVIEW...............................................................................17
1.5. PCILOCALBUSFEATURESANDBENEFITS........................................................18
1.6. ADMINISTRATION...............................................................................................20
2. SIGNALDEFINITION.............................................................................................21
2.1. SIGNALTYPEDEFINITION..................................................................................22
2.2. PINFUNCTIONALGROUPS..................................................................................22
2.2.1. SystemPins................................................................................................23
2.2.2. Address andDataPins..............................................................................24
2.2.3. InterfaceControl Pins...............................................................................25
2.2.4. ArbitrationPins (Bus Masters Only)........................................................27
2.2.5. Error ReportingPins.................................................................................27
2.2.6. Interrupt Pins (Optional)..........................................................................28
2.2.7. Additional Signals.....................................................................................31
2.2.8. 64-Bit Bus ExtensionPins (Optional).......................................................33
2.2.9. JTAG/BoundaryScanPins (Optional)......................................................34
2.2.10. SystemManagement Bus InterfacePins (Optional).................................35
2.3. SIDEBANDSIGNALS............................................................................................36
2.4. CENTRALRESOURCEFUNCTIONS.......................................................................36
3. BUS OPERATION...................................................................................................37
3.1. BUSCOMMANDS................................................................................................37
3.1.1. CommandDefinition.................................................................................37
3.1.2. CommandUsageRules.............................................................................39
3.2. PCIPROTOCOLFUNDAMENTALS.......................................................................42
3.2.1. BasicTransfer Control..............................................................................43
3.2.2. Addressing.................................................................................................44
3.2.3. ByteLaneandByteEnableUsage............................................................56
3.2.4. Bus DrivingandTurnaround....................................................................57
3.2.5. TransactionOrderingandPosting...........................................................58
3.2.6. Combining,Merging,andCollapsing.......................................................62
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3.3. BUSTRANSACTIONS...........................................................................................64
3.3.1. ReadTransaction......................................................................................65
3.3.2. WriteTransaction......................................................................................66
3.3.3. TransactionTermination...........................................................................67
3.4. ARBITRATION.....................................................................................................87
3.4.1. ArbitrationSignalingProtocol..................................................................89
3.4.2. Fast Back-to-BackTransactions...............................................................91
3.4.3. ArbitrationParking...................................................................................94
3.5. LATENCY............................................................................................................95
3.5.1. Target Latency...........................................................................................95
3.5.2. Master DataLatency.................................................................................98
3.5.3. Memory Write Maximum CompletionTimeLimit.....................................99
3.5.4. ArbitrationLatency.................................................................................100
3.6. OTHERBUSOPERATIONS.................................................................................110
3.6.1. DeviceSelection......................................................................................110
3.6.2. Special Cycle...........................................................................................111
3.6.3. IDSEL Stepping.......................................................................................113
3.6.4. Interrupt Acknowledge............................................................................114
3.7. ERRORFUNCTIONS...........................................................................................115
3.7.1. ParityGeneration....................................................................................115
3.7.2. ParityChecking.......................................................................................116
3.7.3. Address ParityErrors.............................................................................116
3.7.4. Error Reporting.......................................................................................117
3.7.5. DelayedTransactions andDataParityErrors.......................................120
3.7.6. Error Recovery........................................................................................121
3.8. 64-BITBUSEXTENSION...................................................................................123
3.8.1. DeterminingBus WidthDuringSystemInitialization.............................126
3.9. 64-BITADDRESSING.........................................................................................127
3.10. SPECIALDESIGNCONSIDERATIONS..............................................................130
4. ELECTRICALSPECIFICATION..........................................................................137
4.1. OVERVIEW.......................................................................................................137
4.1.1. TransitionRoadMap..............................................................................137
4.1.2. Dynamicvs. StaticDrive Specification...................................................138
4.2. COMPONENTSPECIFICATION............................................................................139
4.2.1. 5VSignalingEnvironment......................................................................140
4.2.2. 3.3VSignalingEnvironment...................................................................146
4.2.3. TimingSpecification................................................................................150
4.2.4. IndeterminateInputs and Metastability..................................................155
4.2.5. Vendor ProvidedSpecification................................................................156
4.2.6. Pinout Recommendation.........................................................................157
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4.3. SYSTEMBOARDSPECIFICATION.......................................................................158
4.3.1. ClockSkew..............................................................................................158
4.3.2. Reset........................................................................................................158
4.3.3. Pull-ups...................................................................................................161
4.3.4. Power......................................................................................................163
4.3.5. SystemTimingBudget.............................................................................164
4.3.6. Physical Requirements............................................................................167
4.3.7. Connector PinAssignments....................................................................168
4.4. ADD-INCARDSPECIFICATION..........................................................................171
4.4.1. Add-inCardPinAssignment...................................................................171
4.4.2. Power Requirements...............................................................................176
4.4.3. Physical Requirements............................................................................178
4.4.4. Signal Loading........................................................................................179
5. MECHANICALSPECIFICATION........................................................................181
5.1. OVERVIEW.......................................................................................................181
5.2. ADD-INCARDPHYSICALDIMENSIONSANDTOLERANCES...............................182
5.3. CONNECTORPHYSICALDESCRIPTION..............................................................195
5.4. CONNECTORPHYSICALREQUIREMENTS..........................................................205
5.5. CONNECTORPERFORMANCESPECIFICATION....................................................206
5.6. SYSTEMBOARDIMPLEMENTATION..................................................................207
6. CONFIGURATIONSPACE..................................................................................213
6.1. CONFIGURATIONSPACEORGANIZATION..........................................................213
6.2. CONFIGURATIONSPACEFUNCTIONS................................................................216
6.2.1. DeviceIdentification...............................................................................216
6.2.2. DeviceControl........................................................................................217
6.2.3. DeviceStatus...........................................................................................219
6.2.4. Miscellaneous Registers..........................................................................221
6.2.5. BaseAddresses........................................................................................224
6.3. PCIEXPANSIONROMS ...................................................................................228
6.3.1. PCIExpansionROMContents................................................................229
6.3.2. Power-onSelf Test(POST)Code............................................................232
6.3.3. PC-compatibleExpansionROMs ...........................................................232
6.4. VITALPRODUCTDATA.....................................................................................235
6.5. DEVICEDRIVERS..............................................................................................236
6.6. SYSTEMRESET.................................................................................................236
6.7. CAPABILITIESLIST...........................................................................................237
6.8. MESSAGESIGNALEDINTERRUPTS....................................................................237
6.8.1. MSICapabilityStructure........................................................................238
6.8.2. MSI-XCapability &TableStructures.....................................................244
6.8.3. MSIandMSI-XOperation......................................................................248
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7. 66MHZPCISPECIFICATION.............................................................................255
7.1. INTRODUCTION.................................................................................................255
7.2. SCOPE...............................................................................................................255
7.3. DEVICEIMPLEMENTATIONCONSIDERATIONS..................................................255
7.3.1. ConfigurationSpace................................................................................255
7.4. AGENTARCHITECTURE....................................................................................256
7.5. PROTOCOL........................................................................................................256
7.5.1. 66MHZ_ENABLE(M66EN)PinDefinition............................................256
7.5.2. Latency....................................................................................................257
7.6. ELECTRICALSPECIFICATION............................................................................257
7.6.1. Overview..................................................................................................257
7.6.2. TransitionRoadmapto66MHz PCI......................................................257
7.6.3. SignalingEnvironment............................................................................258
7.6.4. TimingSpecification................................................................................259
7.6.5. Vendor ProvidedSpecification................................................................265
7.6.6. Recommendations....................................................................................265
7.7. SYSTEMBOARDSPECIFICATION.......................................................................266
7.7.1. ClockUncertainty...................................................................................266
7.7.2. Reset........................................................................................................267
7.7.3. Pullups.....................................................................................................267
7.7.4. Power......................................................................................................267
7.7.5. SystemTimingBudget.............................................................................268
7.7.6. Physical Requirements............................................................................268
7.7.7. Connector PinAssignments....................................................................269
7.8. ADD-INCARDSPECIFICATIONS........................................................................269
8. SYSTEM SUPPORTFOR SMBUS.......................................................................271
8.1. SMBUSSYSTEMREQUIREMENTS.....................................................................271
8.1.1. Power......................................................................................................271
8.1.2. Physical andLogical SMBus...................................................................271
8.1.3. Bus Connectivity......................................................................................272
8.1.4. Master andSlaveSupport.......................................................................273
8.1.5. AddressingandConfiguration................................................................273
8.1.6. Electrical.................................................................................................274
8.1.7. SMBus Behavior onPCI Reset................................................................274
8.2. ADD-INCARDSMBUSREQUIREMENTS...........................................................275
8.2.1. Connection..............................................................................................275
8.2.2. Master andSlaveSupport.......................................................................275
8.2.3. AddressingandConfiguration................................................................275
8.2.4. Power......................................................................................................275
8.2.5. Electrical.................................................................................................275
A. SPECIALCYCLEMESSAGES.............................................................................277
A.1. MESSAGEENCODINGS......................................................................................277
A.2. USEOFSPECIFICENCODINGS...........................................................................277
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B. STATEMACHINES...............................................................................................279
B.1. TARGETLOCKMACHINE................................................................................281
B.2. MASTERSEQUENCERMACHINE.......................................................................283
B.3. MASTERLOCKMACHINE...............................................................................284
C. OPERATINGRULES.............................................................................................289
C.1. WHENSIGNALSARESTABLE............................................................................289
C.2. MASTERSIGNALS.............................................................................................290
C.3. TARGETSIGNALS.............................................................................................291
C.4. DATAPHASES..................................................................................................292
C.5. ARBITRATION...................................................................................................292
C.6. LATENCY..........................................................................................................293
C.7. DEVICESELECTION..........................................................................................293
C.8. PARITY.............................................................................................................294
D. CLASS CODES......................................................................................................295
D.1. BASECLASS00H..............................................................................................296
D.2. BASECLASS01H..............................................................................................296
D.3. BASECLASS02H..............................................................................................297
D.4. BASECLASS03H..............................................................................................297
D.5. BASECLASS04H..............................................................................................298
D.6. BASECLASS05H..............................................................................................298
D.7. BASECLASS06H..............................................................................................299
D.8. BASECLASS07H..............................................................................................300
D.9. BASECLASS08H..............................................................................................301
D.10. BASECLASS09H..........................................................................................301
D.11. BASECLASS0AH.........................................................................................302
D.12. BASECLASS0BH.........................................................................................302
D.13. BASECLASS0CH.........................................................................................303
D.14. BASECLASS0DH.........................................................................................304
D.15. BASECLASS0EH.........................................................................................304
D.16. BASECLASS0FH..........................................................................................304
D.17. BASECLASS10H..........................................................................................305
D.18. BASECLASS11H..........................................................................................305
E. SYSTEM TRANSACTIONORDERING..............................................................307
E.1. PRODUCER-CONSUMERORDERINGMODEL....................................................308
E.2. SUMMARYOFPCIORDERINGREQUIREMENTS................................................310
E.3. ORDERINGOFREQUESTS..................................................................................311
E.4. ORDERINGOFDELAYEDTRANSACTIONS.........................................................312
E.5. DELAYEDTRANSACTIONSANDLOCK#...........................................................317
E.6. ERRORCONDITIONS.........................................................................................318
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F. EXCLUSIVEACCESSES......................................................................................319
F.1. EXCLUSIVEACCESSESONPCI.........................................................................320
F.2. STARTINGANEXCLUSIVEACCESS...................................................................321
F.3. CONTINUINGANEXCLUSIVEACCESS...............................................................323
F.4. ACCESSINGALOCKEDAGENT.........................................................................324
F.5. COMPLETINGANEXCLUSIVEACCESS..............................................................325
F.6. COMPLETEBUSLOCK......................................................................................325
G. I/OSPACEADDRESS DECODING FOR LEGACYDEVICES.....................327
H. CAPABILITY IDS..............................................................................................329
I. VITALPRODUCTDATA.....................................................................................331
I.1. VPDFORMAT..................................................................................................333
I.2. COMPATIBILITY................................................................................................334
I.3. VPDDEFINITIONS............................................................................................334
I.3.1. VPDLargeandSmall ResourceDataTags............................................334
I.3.2. VPDExample..........................................................................................337
GLOSSARY....................................................................................................................339

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Figures
FIGURE2-1: PCI PINLIST.................................................................................................21
FIGURE3-1: ADDRESSPHASEFORMATSOFCONFIGURATIONTRANSACTIONS..................48
FIGURE3-2: LAYOUTOFCONFIG_ADDRESS REGISTER...............................................50
FIGURE3-3: HOSTBRIDGETRANSLATIONFORTYPE0CONFIGURATIONTRANSACTIONS
ADDRESSPHASE.........................................................................................................51
FIGURE3-4: CONFIGURATIONREAD.................................................................................56
FIGURE3-5: BASICREADOPERATION..............................................................................65
FIGURE3-6: BASICWRITEOPERATION.............................................................................66
FIGURE3-7: MASTERINITIATEDTERMINATION................................................................68
FIGURE3-8: MASTER-ABORTTERMINATION....................................................................69
FIGURE3-9: RETRY...........................................................................................................73
FIGURE3-10: DISCONNECTWITHDATA...........................................................................74
FIGURE3-11: MASTERCOMPLETIONTERMINATION.........................................................75
FIGURE3-12: DISCONNECT-1WITHOUTDATATERMINATION..........................................76
FIGURE3-13: DISCONNECT-2WITHOUTDATATERMINATION..........................................76
FIGURE3-14: TARGET-ABORT..........................................................................................77
FIGURE3-15: BASICARBITRATION...................................................................................90
FIGURE3-16: ARBITRATIONFORBACK-TO-BACKACCESS...............................................94
FIGURE3-17: DEVSEL# ASSERTION..............................................................................110
FIGURE3-18: IDSELSTEPPING......................................................................................114
FIGURE3-19: INTERRUPTACKNOWLEDGECYCLE..........................................................114
FIGURE3-20: PARITYOPERATION..................................................................................116
FIGURE3-21: 64-BITREADREQUESTWITH64-BITTRANSFER.......................................125
FIGURE3-22: 64-BITWRITEREQUESTWITH32-BITTRANSFER......................................126
FIGURE3-23: 64-BITDUALADDRESSREADCYCLE.......................................................129
FIGURE4-1: ADD-INCARDCONNECTORS.......................................................................138
FIGURE4-2: V/I CURVESFOR5VSIGNALING.................................................................144
FIGURE4-3: MAXIMUMAC WAVEFORMSFOR5V SIGNALING.......................................146
FIGURE4-4: V/I CURVESFOR3.3VSIGNALING..............................................................149
FIGURE4-5: MAXIMUMAC WAVEFORMSFOR3.3VSIGNALING....................................150
FIGURE4-6: CLOCKWAVEFORMS...................................................................................151
FIGURE4-7: OUTPUTTIMINGMEASUREMENTCONDITIONS............................................154
FIGURE4-8: INPUTTIMINGMEASUREMENTCONDITIONS...............................................154
FIGURE4-9: SUGGESTEDPINOUTFORPQFP PCI COMPONENT......................................157
FIGURE4-10: CLOCKSKEWDIAGRAM............................................................................158
FIGURE4-11: RESETTIMING ..........................................................................................161
FIGURE4-12: MEASUREMENTOFTPROP,3.3VOLTSIGNALING.....................................166
FIGURE5-1: PCI RAWADD-INCARD(3.3V,32-BIT)......................................................183
FIGURE5-2: PCI RAWVARIABLEHEIGHTSHORTADD-INCARD(3.3V,32-BIT)...........184
FIGURE5-3: PCI RAWVARIABLEHEIGHTSHORTADD-INCARD(3.3V,64-BIT)...........185
FIGURE5-4: PCI RAWLOWPROFILEADD-INCARD(3.3V,32-BIT)...............................186
FIGURE5-5: PCIADD-INCARDEDGECONNECTORBEVEL............................................187
FIGURE5-6: PCI ADD-INCARDASSEMBLY(3.3V).........................................................188
FIGURE5-7: LOWPROFILEPCIADD-INCARDASSEMBLY(3.3V)..................................189
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FIGURE5-8: PCI STANDARDBRACKET ..........................................................................190
FIGURE5-9: PCI LOWPROFILEBRACKET.......................................................................191
FIGURE5-10: PCI STANDARDRETAINER........................................................................192
FIGURE5-11: I/OWINDOWHEIGHT................................................................................193
FIGURE5-12: ADD-INCARDINSTALLATIONWITHLARGEI/OCONNECTOR...................194
FIGURE5-13: 32-BITCONNECTOR...................................................................................196
FIGURE5-14: 3.3V/32-BITCONNECTORLAYOUTRECOMMENDATION...........................197
FIGURE5-15: 3.3V/64-BITCONNECTOR..........................................................................198
FIGURE5-16: 3.3V/64-BITCONNECTORLAYOUTRECOMMENDATION...........................199
FIGURE5-17: 3.3V/32-BITADD-INCARDEDGECONNECTORDIMENSIONSAND
TOLERANCES............................................................................................................200
FIGURE5-18: 3.3V/64-BITADD-INCARDEDGECONNECTORDIMENSIONSAND
TOLERANCES............................................................................................................201
FIGURE5-19: UNIVERSAL32-BITADD-INCARDEDGECONNECTORDIMENSIONSAND
TOLERANCES............................................................................................................202
FIGURE5-20: UNIVERSAL64-BITADD-INCARDEDGECONNECTORDIMENSIONSAND
TOLERANCES............................................................................................................203
FIGURE5-21: PCI ADD-INCARDEDGECONNECTORCONTACTS....................................204
FIGURE5-22: CONNECTORCONTACTDETAIL.................................................................205
FIGURE5-23: PCI CONNECTORLOCATIONONSYSTEMBOARD......................................208
FIGURE5-24: 32-BITPCIRISERCONNECTOR.................................................................209
FIGURE5-25: 32-BIT/3.3VPCIRISERCONNECTORFOOTPRINT.....................................210
FIGURE5-26: 64-BIT/3.3VPCIRISERCONNECTOR........................................................211
FIGURE5-27: 64-BIT/3.3VPCIRISERCONNECTORFOOTPRINT.....................................212
FIGURE6-1: TYPE00HCONFIGURATIONSPACEHEADER...............................................215
FIGURE6-2: COMMANDREGISTERLAYOUT...................................................................217
FIGURE6-3: STATUSREGISTERLAYOUT........................................................................219
FIGURE6-4: BIST REGISTERLAYOUT............................................................................222
FIGURE6-5: BASEADDRESSREGISTERFORMEMORY....................................................225
FIGURE6-6: BASEADDRESSREGISTERFORI/O..............................................................225
FIGURE6-7: EXPANSIONROM BASEADDRESSREGISTERLAYOUT...............................228
FIGURE6-8: PCI EXPANSIONROM STRUCTURE............................................................229
FIGURE6-9: TYPICALIMAGELAYOUT............................................................................235
FIGURE6-10: EXAMPLECAPABILITIESLIST....................................................................237
FIGURE6-11: MSI CAPABILITYSTRUCTURE..................................................................239
FIGURE6-12: MSI-XCAPABILITYSTRUCTURE..............................................................244
FIGURE6-13: MSI-XTABLESTRUCTURE.......................................................................244
FIGURE7-1: 33MHZPCIVS.66MHZPCITIMING.......................................................257
FIGURE7-2: 3.3VCLOCKWAVEFORM...........................................................................259
FIGURE7-3: OUTPUTTIMINGMEASUREMENTCONDITIONS............................................263
FIGURE7-4: INPUTTIMINGMEASUREMENTCONDITIONS...............................................263
FIGURE7-5: TVAL(MAX) RISINGEDGE...........................................................................264
FIGURE7-6: TVAL(MAX) FALLINGEDGE........................................................................265
FIGURE7-7: TVAL(MIN) ANDSLEWRATE......................................................................265
FIGURE7-8: RECOMMENDEDCLOCKROUTING...............................................................266
FIGURE7-9: CLOCKSKEWDIAGRAM..............................................................................267
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