PCI Express ExpressModule Electromechanical Specification, Revision 1.0

144 Pages·2005·2 MB·English

PCI Express®
ExpressModule™
Electromechanical Specification
Revision 1.0
February 14, 2005
PCI EXPRESS EXPRESSMODULE ELECTROMECHANICAL SPECIFICATION, REV. 1.0

Revision Revision History Date
1.0 Initial release. 02/14/05

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DISCLAIMER
This PCI Express ExpressModule Electromechancial Specification is provided "as is" with no
warranties whatsoever, including any warranty of merchantability, noninfringement,
fitness for any particular purpose, or any warranty otherwise arising out of any proposal,
specification, or sample. PCI-SIG disclaims all liability for infringement of proprietary
rights, relating to use of information in this specification. No license, express or implied,
by estoppel or otherwise, to any intellectual property rights is granted herein.

ExpressModule, PCI, PCI Express, PCIe, and PCI-SIG are trademarks or registered trademarks of
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All other product names are trademarks, registered trademarks, or service marks of their respective
owners.

Copyright © 2005 PCI-SIG
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PCI EXPRESS EXPRESSMODULE ELECTROMECHANICAL SPECIFICATION, REV. 1.0
Contents
1. INTRODUCTION.................................................................................................................11
1.1. TERMS AND DEFINITIONS...............................................................................................11
1.2. REFERENCE DOCUMENTS...............................................................................................12
1.3. SPECIFICATION CONTENTS.............................................................................................12
1.4. OBJECTIVES...................................................................................................................13
1.5. OVERVIEW.....................................................................................................................13
2. EXPRESSMODULE AUXILIARY INTERFACES.............................................................15
2.1. REFERENCE CLOCK........................................................................................................15
2.1.1. Low Voltage Swing, Differential Clocks.................................................................15
2.1.2. Spread Spectrum Clocking (SSC)...........................................................................17
2.1.3. REFCLK Specifications..........................................................................................17
2.1.4. REFCLK Phase Jitter Specification........................................................................21
2.2. MRST# SIGNAL.............................................................................................................22
2.3. WAKE SIGNAL.............................................................................................................22
2.4. INTERNAL STORAGE INTERFACE....................................................................................23
2.4.1. Storage Interface Signal Definitions.......................................................................25
2.5. POWER MANAGEMENT...................................................................................................26
2.5.1. Initial Power-Up (G3 to L0)...................................................................................26
2.5.2. Power Management States (S0 to S3/S4 to S0).......................................................27
2.5.3. Power Down............................................................................................................29
2.6. MANAGEMENT...............................................................................................................29
2.6.1. Capacitive Load of High-power SMBus Lines........................................................30
2.6.2. Minimum Current Sinking Requirements for SMBus Devices................................30
2.6.3. SMBus “Back Powering” Considerations..............................................................31
2.6.4. Power-on Reset.......................................................................................................31
2.6.5. SMBus Termination and Power..............................................................................31
2.6.6. SMBAlert.................................................................................................................31
2.6.7. Management Bus Topology.....................................................................................31
2.6.8. Data Integrity..........................................................................................................32
2.6.9. Basic Management Status Register.........................................................................33
2.6.10. Satellite Management Controller........................................................................34
2.6.11. Remote Management Card Access......................................................................34
2.6.12. VPD (FRU) Information Format.........................................................................35
2.6.13. Using an SMBus Multiplexer with a Host Controller.........................................48
2.6.14. Implementing ExpressModule Management in an IPMI Environment...............48
2.6.15. Sending Data to a Management Controller on a Module...................................49
2.6.16. Receiving Data From a Management Controller on a Module..........................51
2.6.17. SMBAlert Control and Status..............................................................................54
2.6.18. Message Class Values for Management Controller Messaging.........................55
2.6.19. Retention of Output Data....................................................................................55
2.6.20. SMBAlert Signal Handling for Message Transfers.............................................56
2.6.21. Polling for Output Data......................................................................................56
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2.6.22. SMBus NACKs and Error Recovery....................................................................56
2.6.23. PEC Handling.....................................................................................................56
2.6.24. Summary of SMBus Commands Values for Management Controller Messaging57
2.6.25. SMBus Timeout and Hang Handling..................................................................58
2.6.26. Management Controller Messaging Timing.......................................................58
2.6.27. IPMI Management Controller Message Formats...............................................59
2.6.28. Pre-assigned/Reserved Slave Addresses.............................................................61
2.7. AUXILIARY SIGNAL PARAMETRIC SPECIFICATIONS.......................................................63
2.7.1. DC Specifications....................................................................................................63
2.7.2. AC Specifications....................................................................................................64
3. HOT INSERTION/REMOVAL............................................................................................67
3.1. SCOPE............................................................................................................................67
3.2. HOT-PLUG SUB-SYSTEM ARCHITECTURE......................................................................67
3.2.1. Power Enable..........................................................................................................72
3.2.2. Power Fault............................................................................................................72
3.2.3. Wake........................................................................................................................72
3.2.4. Module Power Good...............................................................................................73
3.2.5. Module Reset...........................................................................................................73
3.2.6. Present Detection....................................................................................................73
3.2.7. System Management Bus.........................................................................................73
3.2.8. System Management Bus Alert................................................................................74
3.2.9. Power LED..............................................................................................................74
3.2.10. Attention LED......................................................................................................74
3.2.11. Manual Retention Latch......................................................................................74
3.2.12. Electromechanical Interlock...............................................................................74
3.2.13. Electromechanical Interlock Status....................................................................75
3.2.14. Attention Switch...................................................................................................75
4. MODULE POWER INTERFACE........................................................................................77
4.1. POWER...........................................................................................................................77
4.1.1. Module Primary Power Supply...............................................................................77
4.1.2. Module Auxiliary Power Supply.............................................................................77
4.2. EXPRESSMODULE POWER SUPPLY REQUIREMENTS.......................................................78
4.3. POWER CONSUMPTION...................................................................................................79
4.4. POWER SUPPLY SEQUENCING........................................................................................79
4.5. POWER SUPPLY DECOUPLING........................................................................................79
5. MODULE PCI EXPRESS INTERFACE..............................................................................81
5.1. PCI EXPRESS LINK SIGNALS..........................................................................................81
5.2. PCI EXPRESS ELECTRICAL TOPOLOGIES AND LINK DEFINITIONS..................................81
5.2.1. Topologies...............................................................................................................81
5.2.2. Link Definitions.......................................................................................................82
5.3. PCI EXPRESS ELECTRICAL BUDGETS.............................................................................83
5.3.1. AC Coupling Capacitors.........................................................................................83
5.3.2. Insertion Loss Values (Voltage Transfer Function)................................................83
5.3.3. Jitter Values............................................................................................................86
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PCI EXPRESS EXPRESSMODULE ELECTROMECHANICAL SPECIFICATION, REV. 1.0
5.3.4. Crosstalk.................................................................................................................88
5.3.5. Lane-to-Lane Skew..................................................................................................88
5.3.6. Equalization............................................................................................................89
5.3.7. Skew Within the Differential Pair...........................................................................89
5.4. EYE DIAGRAMS AT THE EXPRESSMODULE INTERFACE..................................................89
5.4.1. ExpressModule Transmitter Path Compliance Eye Diagram................................90
5.4.2. ExpressModule Minimum Receiver Path Sensitivity Requirements.......................91
5.4.3. System Board Transmitter Path Compliance Eye Diagram...................................92
5.4.4. System Board Minimum Receiver Path Sensitivity Requirements..........................94
6. EXPRESSMODULE CONNECTOR....................................................................................97
6.1. CONNECTOR PIN COUNTS..............................................................................................97
6.2. CONNECTOR PIN ASSIGNMENTS.....................................................................................99
6.3. CONNECTOR INTERFACE DEFINITIONS.........................................................................102
6.4. CONNECTOR SIGNAL INTEGRITY REQUIREMENTS AND TEST PROCEDURES..................108
6.5. CONNECTOR ENVIRONMENTAL AND OTHER REQUIREMENTS......................................111
6.5.1. Environmental Requirements................................................................................111
6.5.2. Mechanical Requirements.....................................................................................113
6.5.3. Current Rating Requirement.................................................................................114
6.5.4. Additional Considerations....................................................................................114
7. MODULE MECHANICAL SPECIFICATION..................................................................117
7.1. MECHANICAL OVERVIEW............................................................................................117
7.2. DIMENSIONS AND TOLERANCES...................................................................................118
7.3. SYSTEM DATUM PLANE DEFINITION............................................................................119
7.4. MODULE DESCRIPTION................................................................................................119
7.4.1. Module Materials..................................................................................................120
7.4.2. Singlewide and Doublewide Module Form Factor...............................................122
7.4.3. Module Raw Card.................................................................................................124
7.4.4. Module Ejector and Latch Details........................................................................125
7.4.5. I/O Plate Details...................................................................................................126
7.4.6. Module Air Vent Design for EMI..........................................................................127
7.5. FILLER COMPONENT OR MODULE................................................................................128
7.6. CHASSIS SLOT DESCRIPTION........................................................................................128
7.6.1. Backplane and Chassis Slot Details.....................................................................129
8. DESIGN CONSIDERATIONS...........................................................................................131
8.1. COOLING/THERMAL ENVIRONMENT............................................................................131
8.1.1. Longitudinal Cooling – Default Mode..................................................................132
8.1.2. Lateral Cooling – Alternate Mode........................................................................134
8.1.3. Cooling Consideration for Storage Extension Slot...............................................137
8.1.4. Module EMI Design..............................................................................................138
8.2. MODULE ESD DESIGN.................................................................................................140
8.3. MODULE INTEROPERABILITY.......................................................................................140
8.4. SLOT/MODULE COLOR CODING AND LABELING..........................................................140
8.4.1. Module Hot Remove and Add Capability.............................................................142
8.4.2. Modules That May Require a System Power Down..............................................142
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PCI EXPRESS EXPRESSMODULE ELECTROMECHANICAL SPECIFICATION, REV. 1.0
8.4.3. Internal Storage Modules.....................................................................................142
8.4.4. Optional Module Labeling....................................................................................142
8.4.5. Slot Labeling on the System..................................................................................143
8.4.6. Optional x16 Doublewide Slot Labeling...............................................................143
8.4.7. Slot Numbering and Labeling...............................................................................143

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PCI EXPRESS EXPRESSMODULE ELECTROMECHANICAL SPECIFICATION, REV. 1.0

Figures
FIGURE 2-1: DIFFERENTIAL REFCLK WAVEFORM......................................................................16
FIGURE 2-2: EXAMPLE REFERENCE CLOCK SOURCE TERMINATION.............................................16
FIGURE 2-3: SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT AND SWING.19
FIGURE 2-4: SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT..........................19
FIGURE 2-5: SINGLE-ENDED MEASUREMENT POINTS FOR RISE AND FALL TIME MATCHING........20
FIGURE 2-6: DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE AND PERIOD...................20
FIGURE 2-7: DIFFERENTIAL MEASUREMENT POINTS FOR RISE AND FALL TIME...........................20
FIGURE 2-8: DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK...........................................21
FIGURE 2-9: REFERENCE CLOCK SYSTEM MEASUREMENT POINT AND LOADING.........................21
FIGURE 2-10: POWER UP..............................................................................................................27
FIGURE 2-11: POWER MANAGEMENT STATES...............................................................................28
FIGURE 2-12: POWER DOWN.........................................................................................................29
FIGURE 2-13: EXAMPLE SMBUS TOPOLOGY................................................................................32
FIGURE 2-14: BASIC MANAGEMENT STATUS REGISTER ACCESS..................................................33
FIGURE 2-15: BMC SINGLE-PART WRITE.....................................................................................50
FIGURE 2-16: MULTI-PART WRITE START....................................................................................51
FIGURE 2-17: MULTI-PART WRITE MIDDLE..................................................................................51
FIGURE 2-18: MULTI-PART WRITE END........................................................................................51
FIGURE 2-19: SINGLE-PART READ................................................................................................52
FIGURE 2-20: MULTI-PART READ START......................................................................................52
FIGURE 2-21: MULTI-PART READ MIDDLE...................................................................................53
FIGURE 2-22: BMC MULTI-PART READ END................................................................................53
FIGURE 2-23: MULTI-PART READ RETRY.....................................................................................53
FIGURE 2-24: GET MESSAGE INTERFACE STATUS.........................................................................54
FIGURE 2-25: SET MESSAGE INTERFACE CONTROL......................................................................55
FIGURE 2-26: BMC TO MODULE IPMI STANDARD REQUEST.......................................................59
FIGURE 2-27: BMC TO MODULE IPMI STANDARD RESPONSE.....................................................60
FIGURE 2-28: MODULE TO BMC IPMI STANDARD REQUEST.......................................................61
FIGURE 2-29: MODULE TO BMC IPMI STANDARD RESPONSE.....................................................61
FIGURE 2-30: WAKE RISE AND FALL TIME MEASUREMENT POINTS...........................................65
FIGURE 3-1: TYPICAL HOT-PLUG INTERFACE IMPLEMENTATION..................................................69
FIGURE 5-1: EXAMPLE INTERCONNECT TERMINATED AT THE CONNECTOR INTERFACE................84
FIGURE 5-2: INSERTION LOSS BUDGETS.......................................................................................85
FIGURE 5-3: JITTER BUDGET.........................................................................................................86
FIGURE 5-4: EXPRESSMODULE TRANSMITTER PATH COMPLIANCE EYE DIAGRAM......................90
FIGURE 5-5: REPRESENTATIVE COMPOSITE EYE DIAGRAM FOR EXPRESSMODULE RECEIVER PATH
COMPLIANCE.........................................................................................................................91
FIGURE 5-6: SYSTEM BOARD TRANSMITTER PATH COMPOSITE COMPLIANCE EYE DIAGRAM......92
FIGURE 5-7: TWO PORT MEASUREMENT MODEL..........................................................................94
FIGURE 5-8: REPRESENTATIVE COMPOSITE EYE DIAGRAM FOR SYSTEM BOARD RECEIVER PATH
COMPLIANCE.........................................................................................................................95
FIGURE 6-1: EXPRESSMODULE CONNECTOR FORM FACTOR......................................................103
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PCI EXPRESS EXPRESSMODULE ELECTROMECHANICAL SPECIFICATION, REV. 1.0
FIGURE 6-2: EXPRESSMODULE CONNECTOR FORM FACTOR WITH STORAGE EXTENSION..........104
FIGURE 6-3: RECOMMENDED FOOTPRINTS..................................................................................105
FIGURE 6-4: ADD-IN MODULE EDGE-FINGER DIMENSIONS........................................................106
FIGURE 6-5: ADD-IN MODULE WITH STORAGE EDGE-FINGER DIMENSIONS...............................107
FIGURE 6-6: ILLUSTRATION OF ADJACENT PAIRS.......................................................................111
FIGURE 6-7: CONTACT RESISTANCE MEASUREMENT POINTS.....................................................112
FIGURE 7-1: CHASSIS ASSEMBLY................................................................................................118
FIGURE 7-2: EXPLODED VIEW OF SINGLEWIDE MODULE............................................................120
FIGURE 7-3: SIMPLE CIRCUIT REPRESENTATION OF AFP STEEL USING FOUR-POINT RESISTANCE
METHOD..............................................................................................................................121
FIGURE 7-4: CRITICAL DIMENSIONS...........................................................................................123
FIGURE 7-5: SINGLEWIDE CROSS SECTION.................................................................................124
FIGURE 7-6: DOUBLEWIDE CROSS SECTION................................................................................124
FIGURE 7-7: MODULE RAW CARD REFERENCE DRAWING..........................................................125
FIGURE 7-8: EJECTOR ASSEMBLY...............................................................................................126
FIGURE 7-9: MODULE I/O PLATE................................................................................................127
FIGURE 7-10: MODULE VENT DESIGN........................................................................................128
FIGURE 7-11: CHASSIS REQUIREMENTS......................................................................................129
FIGURE 8-1: LONGITUDINAL SYSTEM AIRFLOW.........................................................................132
FIGURE 8-2: SINGLEWIDE MODULE: REQUIRED CFM VS. MODULE INLET TEMPERATURE,
DEFAULT MODE...................................................................................................................133
FIGURE 8-3: SINGLEWIDE MODULE: REQUIRED PRESSURE DROP RANGE VS. FLOW RATE,
DEFAULT MODE...................................................................................................................134
FIGURE 8-4: UNINTENDED RECIRCULATION...............................................................................135
FIGURE 8-5: SINGLEWIDE MODULE: REQUIRED CFM VS. MODULE INLET TEMPERATURE,
ALTERNATE MODE..............................................................................................................136
FIGURE 8-6: SINGLEWIDE MODULE: REQUIRED PRESSURE DROP RANGE VS. FLOW RATE,
ALTERNATE MODE..............................................................................................................137
FIGURE 8-7: STORAGE SLOT VENTING........................................................................................138
FIGURE 8-8: EMI GASKET PROFILE............................................................................................138
FIGURE 8-9: REQUIRED MODULE I/O PLATE ATTENUATION......................................................139
FIGURE 8-10: MODULE LATCH LABELING LOCATIONS...............................................................141
FIGURE 8-11: REQUIRED MODULE LABEL WITH EXAMPLES.......................................................141
FIGURE 8-12: REQUIRED SLOT LABELING..................................................................................143
FIGURE 8-13: OPEN VENT SYMBOL............................................................................................144
FIGURE 8-14: CLOSED VENT SYMBOL........................................................................................144

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PCI EXPRESS EXPRESSMODULE ELECTROMECHANICAL SPECIFICATION, REV. 1.0
Tables
TABLE 2-1: REFCLCK DC SPECIFICATION AND AC TIMING REQUIREMENTS............................18
TABLE 2-2: MAXIMUM ALLOWED PHASE JITTER WHEN APPLIED TO FIXED FILTER
CHARACTERISTIC...................................................................................................................22
TABLE 2-3: STORAGE SIDEBAND SIGNALS: I2C/SMBUS..............................................................25
TABLE 2-4: STORAGE SIDEBAND SIGNALS: SGPIO......................................................................26
TABLE 2-5: BASIC MANAGEMENT STATUS REGISTER...................................................................33
TABLE 2-6: VPD (FRU) COMMON HEADER.................................................................................35
TABLE 2-7: OEM RESERVED SPACE HEADER..............................................................................36
TABLE 2-8: VPD (FRU) RECORD FORMAT..................................................................................36
TABLE 2-9: VPD (FRU) RECORD TYPES......................................................................................37
TABLE 2-10: BOARD INFO DATA FORMAT....................................................................................38
TABLE 2-11: PRODUCT INFO DATA FORMAT................................................................................39
TABLE 2-12: PRODUCT GUID DATA FORMAT..............................................................................40
TABLE 2-13: EXPRESSMODULE MODULE INFO DATA FORMAT....................................................41
TABLE 2-14: PCI EXPRESS MODULE INFO DATA FORMAT...........................................................42
TABLE 2-15: EXPRESSMODULE MULTIPLEXER RECORD DATA FORMAT......................................43
TABLE 2-16: OEM RECORD DATA FORMAT.................................................................................44
TABLE 2-17: LANGUAGE CODES...................................................................................................45
TABLE 2-18: INTERFACE STATUS FIELD DEFINITION....................................................................54
TABLE 2-19: INTERFACE CONTROL FIELD DEFINITION.................................................................55
TABLE 2-20: MESSAGE CLASS VALUES........................................................................................55
TABLE 2-21: SUMMARY OF SMBUS COMMANDS FOR MESSAGE PROTOCOLS...............................57
TABLE 2-22: SMBUS MESSAGING TIMING SPECIFICATIONS.........................................................58
TABLE 2-23: MANAGEMENT I/O ADDRESSES...............................................................................62
TABLE 2-24: AUXILIARY SIGNAL DC SPECIFICATIONS................................................................63
TABLE 2-25: POWER SEQUENCING AND RESET SIGNAL TIMINGS..................................................64
TABLE 3-1: POWER SIGNALS........................................................................................................70
TABLE 3-2: MANAGEMENT INTERFACE........................................................................................70
TABLE 3-3: USER INTERFACE.......................................................................................................71
TABLE 3-4: EMLS SIGNAL...........................................................................................................75
TABLE 4-1: POWER SUPPLY RAIL REQUIREMENTS.......................................................................78
TABLE 5-1: ALLOCATION OF INTERCONNECT PATH INSERTION LOSS BUDGET.............................85
TABLE 5-2: TOTAL SYSTEM JITTER BUDGET................................................................................87
TABLE 5-3: ALLOCATION OF INTERCONNECT JITTER BUDGET......................................................87
TABLE 5-4: ALLOWABLE INTERCONNECT LANE-TO-LANE SKEW.................................................89
TABLE 5-5: EXPRESSMODULE TRANSMITTER PATH COMPLIANCE EYE REQUIREMENTS..............90
TABLE 5-6: EXPRESSMODULE MINIMUM RECEIVER PATH SENSITIVITY REQUIREMENTS.............91
TABLE 5-7: SYSTEM BOARD TRANSMITTER PATH COMPLIANCE EYE REQUIREMENTS.................92
TABLE 5-8: SYSTEM BOARD MINIMUM RECEIVER PATH SENSITIVITY REQUIREMENTS................94
TABLE 6-1: EXPRESSMODULE CONNECTOR PIN TYPE/COUNT.....................................................97
TABLE 6-2: OPTIONAL STORAGE PIN COUNT/TYPE......................................................................98
TABLE 6-3: EXPRESSMODULE CONNECTOR PIN ASSIGNMENTS....................................................99
TABLE 6-4: SIGNAL INTEGRITY REQUIREMENTS AND TEST PROCEDURES..................................109
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TABLE 6-5: TEST DURATIONS.....................................................................................................112
TABLE 6-6: MECHANICAL TEST PROCEDURES AND REQUIREMENTS...........................................113
TABLE 6-7: END-OF-LIFE CURRENT RATING TEST SEQUENCE....................................................114
TABLE 6-8: ADDITIONAL REQUIREMENTS..................................................................................114
TABLE 7-1: DATUM TABLE.........................................................................................................119
TABLE 7-2: LED COLOR............................................................................................................127
TABLE 8-1: X8 SLOT CONNECTOR INTEROPERABILITY...............................................................140

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