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PCI Express® Base Specification Revision 4.0 Version 0.3 PDF

1053 Pages·2014·11.74 MB·English
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Preview PCI Express® Base Specification Revision 4.0 Version 0.3

PCI Express® Base Specification Revision 4.0 Version 0.3 February 19, 2014 2 Revision Revision History DATE 1.0 Initial release. 07/22/2002 1.0a Incorporated Errata C1-C66 and E1-E4.17. 04/15/2003 1.1 Incorporated approved Errata and ECNs. 03/28/2005 2.0 Added 5.0 GT/s data rate and incorporated approved Errata and ECNs. 12/20/2006 2.1 Incorporated Errata for the PCI Express Base Specification, Rev. 2.0 (February 27, 2009), and added the following ECNs: • Internal Error Reporting ECN (April 24, 2008) • Multicast ECN (December 14, 2007, approved by PWG May 8, 2008) • Atomic Operations ECN (January 15, 2008, approved by PWG April 17, 2008) • Resizable BAR Capability ECN (January 22, 2008, updated and approved by PWG April 24, 2008) • Dynamic Power Allocation ECN (May 24, 2008) • ID-Based Ordering ECN (January 16, 2008, updated 29 May 2008) • Latency Tolerance Reporting ECN (22 January 2008, updated 14 August 2008) • Alternative Routing-ID Interpretation (ARI) ECN (August 7, 2006, last updated June 4, 2007) • Extended Tag Enable Default ECN (September 5, 2008) • TLP Processing Hints ECN (September 11, 2008) • TLP Prefix ECN (December 15, 2008) 03/04/2009 3.0 Added 8.0 GT/s data rate, latest approved Errata, and the following ECNs: • Optimized Buffer Flush/Fill ECN (8 February 2008, updated 30 April 2009) • ASPM Optionality ECN (June 19, 2009, approved by the PWG August 20, 2009) • Incorporated End-End TLP Changes for RCs ECN (26 May 2010) and Protocol Multiplexing ECN (17 June 2010) 11/10/2010 3.1 Incorporated Errata for the PCI Express® Base Specification Revision 3.0 (November 7, 2013) Incorporated the following ECNs: • ECN: Downstream Port containment (DPC) • ECN: Separate Refclk Independent SSC (SRIS) Architecture • ECN: Process Address Space ID (PASID) • ECN: Lightweight Notification (LN) Protocol • ECN: Precision Time Measurement • ECN: Enhanced DPC (eDPC) • ECN: 8.0 GT/s Receiver Impedance • ECN: L1 PM Substates with CLKREQ • ECN: Change Root Complex Event Collector Class Code • ECN: M-PCIe • ECN: Readiness Notifications (RN) 11/7/2013 4.0 Version 0.3: Based on PCI Express® Base Specification Revision 3.1 (November 7, 2013) with some editorial feedback received in December 2013. • Added Chapter 9, Electrical Sub-block: Separated Section 4.3 of the 3.1 Base Specification to create Chapter 9.Added Chapter 9 (Rev0.3-11-30-13_final.docx) • Changes related to Revision 0.3 release • 2/19/2014 PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.3 3 PCI-SIG® disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to update the information contained herein. Contact the PCI-SIG office to obtain the latest revision of this specification. Questions regarding the PCI Express Base Specification or membership in PCI-SIG may be forwarded to: Membership Services www.pcisig.com E-mail:

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