opti :: brochures :: ISA VL Chipset Brochure 1993

2 Pages·1993·1 MB·English

• • • • • •
.................................... 486IPentium™ Write Back .................................... .
The OPTi design team is Features/Benefits
proud to present the 32-bit
• 100% PC/AT compatible
486/Pentium AT solution
• Fully supports the Intel 486 and
with VESA Local bus. As Pentium microprocessor
always, the product • Three chip PC/AT solution: 82C571,
82C572 and 82C206
emphasis is on value. The OPTi
• IX clock source, supporting systems
82C571/572 chipset is crafted to provide
running up to 66 MHz
the highest performance but most cost
• Write Back, direct-mapped cache with
effective system solution without size selections: 64K, 128K, 256K,
compromising quality, compatibility or 512K,1Mb
reliability. • Programmable cache write policy:
write-back or write through
• Fully programmable cache and DRAM
The 82C571/572 is a top-of-the-line
read/write cycles
solution for the server/power user market.
• Supports 3-2-2-2 cache burst read
Flexibility of design without using the most cycle at 66 MHz
expensive support parts has been given • Built-in TAG auto-invalidation circuitry
• Support for two programmable non
key importance. This ensures the total
cacheable/system memory "hole"
system cost to be at the high-end 486 regions
level -and with upgradability to the high • Supports two banks of 64-bit wide
DRAMs with 256K, 512K, 1M , 2M, 4M,
end Pentium performance.
and 8M x 36 page-mode DRAMs
• Supports DRAM configurations up to
The 82C571/572 has a state-of-the-art
128 Mb
cache controller for up to 2 MB of Write • Supports DRAM burst cycles
back cache support. The DRAM controller • DRAM post write buffer
also supports posted writes for faster • Provides Flash ROM support
• 33 MHz asynchronous 32-bit VESA VL
performance on write cycles.
Local Bus support
• Performance oriented snoop-line
The OPTi 82C571/572 provides 486 PC
comparator for VUISA bus masters
power users the horsepower of the 64-bit • Extended DMA page register
Pentium at 60 MHz and 66 MHz as • Asynchronous CPU and VL bus
interface
needed in the future.
• AT bus clock speed programmability
• Low power, high speed CMOS
technology
OPTi
The OPTi 82C571/572 chipset provides a secondary cache memory and the 32-bit DRAM bus.
highly integrated solution for fully It also controls the data flow between the CPU bus,
compatible, high performance PC/AT the DRAM bus, the Local bus, and the 16/8-bit ISA
platforms. Together with the 82C206 integrated
bus.
peripherals controller, this chipset supports the Intel
Pentium processor in the most cost effective and The 82C572 ATC integrates the AT bus interface
feature-rich designs available today. and the data buffers for transfers between the CPU
data bus, Local data bus and the DRAM data bus. It
The OPTi 82C571/572 chipset is comprised of the
also provides ISA to Local bus command
82C571 and the 82C572 controllers. The 82C571
translation.
SYSC provides the control functions for the host
OPTi
CPU interface, the 33 MHz asynchronous 32-bit
82C571/572:
Local bus interface, burst read and write to
The solution
for your high
performance
486/Penlium" Cache needs.
60-66 MHz 64K 101MB
64-bit CPU data bus
AT 24·bit address bus
•
VESA 32·bit data bus AT 16·bit data bus
•
VESA Local Bus Peripherals AT Bus Peripherals
•
•
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All products mentioned in this data sheet are registered trademarks of their respective owners. © OPTi, fnc. 1993