opti :: brochures :: EISA Pentium Chipset Brochure 1993

2 Pages·1993·1 MB·English

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................................. Pentium™ J.lp Write Back Cache EISA ........................... .
EISA provides a high Features/Benefits
performance 32-bit migration
• Fastest 100% EISA compatible
path for PC/ATs based on the
60/66 MHz Pentium write back chipset
32-bit microprocessor
• Patented write back controller
architecture from Intel. OPTi's
-Flexible cache sizes -128K to 1 MB
EISA Pentium chipset provides unprecedented
• High performance, closely coupled, 8 bank
performance, features and cost advantages for
DRAM controller
discriminating OEMs. While the EISA Pentium
-Direct connections for both single and
chipset has been designed to support the full
double density x36 SIMMs
range of Pentium microprocessors, it is
-2MB -256MB main memory with just 8
optimized especially for Pentium processors
SIMMs
which are extremely sensitive to external wait
• Total system performance tuning features
states. This patented Write Back cache
-Hidden refresh
implementation makes this the fastest Pentium
-Programmable holes in memory
chipset available and clearly distinguishes itself
-CPU bus local device support
from the competition. In addition to the WB
-Fast GATEA20/transparent CPU reset
cache, Systems Integrators finally have a -Synchronous EISA bus clock with relaxed
chipset that directly supports both single and skew requirements
double density x36 SIMMs resulting in -Video/system BIOS shadowable and
remarkable DRAM integration. The EISA cacheable
Pentium is targeted at OEMs who must provide • Complete EISA motherboard
a low cost, small-footprint EISNPC yet still • Low power, high speed CMOS technology
provide the performance and rich feature set
necessary to differentiate themselves from the
rest of the pack.
The OPTi chipset craftsman, with their proven
track record in high performance PC/AT
chipsets are proud to offer the EISA Pentium -
and help PC OEMs extend their AT product
lines with top-of-the-line EISA PCs.
OPTi
The OPTi EISA Pentium chipset consists of two The Data Bus Controller -82C697 -integrates data
208-pin QFP devices: theSYSC, the BUSC and 2 buffers and provides control for synchronous data
1~ O-pin DBC buffer chips. pipelining. It also provides control for bus conversion,
The SYSC write back-memory cache controller -82C693 - Parity generation and checking and an EISA ID register.
controls the memory subsystem for EISA bus controller
The high levels of integration and performance provided
accesses between the CPU, EISNISA masters and DMA
by these 4 devices enable OEMs to plan the evolution of
devices. The memory subsystem consists of up to 8 banks
their Pentium PC/ATs to EISNPCs. This chipset enables
of DRAM with hidden refresh and from 128K to 1M B of
OEMs to move ahead aggressively with high performance
write back cache translates bus control signals and
EISA platforms in order to participate successfully in the
addresses between the CPU, EISA, ISA and DMA
migration of 32-bit PCs to EISA.
masters and slaves.
The BUSC -82C696 -integrates the motherboard 1/0
logic defined by the EISA specification: two 8254 timers,
EISA NMl/time-out logic, two EISA 8259 interrupt
controllers, a 32-bit DMA controller and the EISA system
OPTi Baby
arbiter.
EISA 486
Pentium -
robust, high
performance
design for
high volume
EISA pes.
Write Back
Cache
Pentium
128K-1MB
SD Bus
Local
Bus
Peripherals
DRAM
MD Bus 2MB -256 MB
LA Bus
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All products mentioned in this data sheet are registered trademarks of their respective owners. © OPTi, Inc. 1993