opti :: brochures :: DXSLC Brochure 1992

2 Pages·1992·0.95 MB·English

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___________ . _______ . ____ . _____ .386/486 Low Cost Write Back. ___ . ____ ._._. _____________ . ___ ._
...~ . he OPTi DXSlC was Features/Benefits
designed with two major • One 160-pin CMOS Plastic Flat
Package (PFP) plus 82C206
objectives in mind. First,
• Internal buffers and termination to
support the high volume, reduce external parts count
high performance 386/486 • Copy-back Direct-Mapped Cache with
size of 64Kb, 128Kb, 256Kb and 512Kb
Vl market. Second, be the most cost
• Up to 10% performance enhancement
efficient solution, even, in this extremely from write-through cache scheme
competitive market. The DXSlC redefines • Supports 2,1,1,1 or 3,2,2,2 cache
cycles
chipset solutions for that "value" market in
• On-chip comparator determines cache
a single broad-stroke. hit or miss
• Up to 64-MB of local high-speed, page-
mode, DRAM memory space
The DXSlC vehicle provides all the
• Burst-line-fill during Cache-Read-Miss
above values-but still in,the OPTi tradition
• Control of two non-cacheable regions
of reliability, compatibility, support and • Shadow RAM support for System BIOS,
Video Bios and adapter card BIOS
service throughout the design and after
• Optional caching of shadowed Video
sales. BIOS
• Hidden refresh support to enhance
system performance
The DXSlC is designed to be the best
• 8042 emulation for fast CPU-reset and
combination of cost-effective packaging gateA20 generation
and partitioning, while keeping the feature • Turbolslow speed selection
• AT-bus clock selectable from ClKI
set robust.
(/6,/5,/4,/3)
• CAS before RAS refresh reduces
The DXSlC is the "only" solution if you power consumption
• Optional 0 or 1 wait state for Cache
want to have a competitive solution in
Write-Hit
today's and tomorrow's markets. • 387 Coprocessor support for 386 mode
• Internal CD and CA bus pull-up
resistors to save components and
board real-estate
• Comprehensive VESA Vl and OPTi
High Performance local Bus support
• low cost, low power, 1.0 f.1.CMOS
Technology
OPTi
The OPTi 495SLC is a "Super Low Cost", a write-back cache controller, a local DRAM
two chip solution offering optimal controller, the CPU state machine, the AT bus
performance for low to mid-range state machine and data buffers, all in a single
386/486 based AT systems. The OPTi 495SLC 160-pin PFP. New on-chip hardware provides
is designed for 386 systems running from 20, the hooks for OPTi and VESA local bus device
25, 33 and 50 MHz. The 82C495SLC integrates support.
Vital Statistics 486 DXSLC
Frequency_ _ 25/33/40/50
VLSI+TIL 2+16
Pals 0
Write-back Cache 64k-512k
DRAM capacity 64M OPTi
Video/system BIOS shadow/cache Yes DXSLC:
Synchronous AT bus clock 8.33/8.25/8.0 The super
Local Bus device support Yes low-cost
Landmark v2.0 (MHz) @ 66MHz 223.04 leader.
Power Meter v1.3 (MIPS) @ 66MHz 29.304
Norton SI v6.QJCI) @ 66 MHz 144.2
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All produc1s mentioned in this data sheet are registered trademarks of their respective owners. © OPTi, Inc. 1992