Op Amps for Everyone

284 Pages·2013·7.89 MB·English

by  Bruce Carter (Auth.)

Op Amps for Everyone
Op Amps for Everyone
Fourth Edition
Bruce Carter
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13 14 15 16 10 9 8 7 6 5 4 3 2 1
List of Figures
Figure 2.1 Ohm’s Law 8
Figure 2.2 Voltage Divider Rule 8
Figure 2.3 Superposition Example 9
Figure 2.4 When V is Grounded 9
1
Figure 2.5 When V is Grounded 10
2
Figure 2.6 The Non-Inverting Op Amp 11
Figure 2.7 The Inverting Op Amp 12
Figure 2.8 The Adder Circuit 13
Figure 2.9 The Differential Amplifier 14
Figure 2.10 Typical Open-Loop Op Amp Response 15
Figure 3.1 Split-Supply Op Amp Circuit 20
Figure 3.2 Single-Supply Inverting Op Amp Circuit 20
Figure 3.3 Single-Supply Non-Inverting Op Amp Gain Circuit 21
Figure 3.4 Cartesian Coordinates 23
Figure 3.5 Schematic for Case 1: V 51mV 1b 25
OUT IN
Figure 3.6 Case 1 Example Circuit 28
Figure 3.7 Schematic for Case 2: V 51mV 2b 29
OUT IN
Figure 3.8 Case 2 Example Circuit 31
Figure 3.9 Schematic for Case 3: V 51mV 1b 31
OUT IN
Figure 3.10 Case 3 Example Circuit 32
Figure 3.11 Schematic for Case 4: V 52mV 2b 33
OUT IN
Figure 3.12 Case 4 Example Circuit 35
Figure 3.13 Case 9 Circuit 36
xi
xii List of Figures
Figure 3.14 Case 10 Circuit 36
Figure 3.15 Case 13 (Inverting Attenuator) Circuit 37
Figure 3.16 Case 11 Circuit 37
Figure 3.17 Case 12 Circuit 37
Figure 3.18 Case 8 Circuit 38
Figure 3.19 Case 7 Circuit 38
Figure 3.20 Universal Op Amp Circuit 39
Figure 3.21 Universal Op Amp Calculator 40
Figure 3.22 Universal Op Amp Board 41
Figure 4.1 The Ideal Op Amp 44
Figure 4.2 Op Amp Open-Loop Response 45
Figure 4.3 Undercompensated Op Amp 45
Figure 4.4 Electronics Version of the Feedback Diagram and Equations 46
Figure 4.5 The Feedback Loop Analysis Figure Modified to Show a
Non-Inverting Op Amp Stage 47
Figure 4.6 The Feedback Loop Analysis Figure Modified to Show an
Inverting Op Amp Stage 47
Figure 4.7 Current Feedback Amplifier Model 48
Figure 4.8 Single Ended Op Amp Schematic Symbol 50
Figure 4.9 Fully Differential Op Amp Schematic Symbol 50
Figure 4.10 Closing the Loop on a Single-Ended Op Amp 51
Figure 4.11 Closing the Loop on a Fully Differential Op Amp 51
Figure 4.12 Single-Ended to Differential Conversion 52
Figure 4.13 Relationship between V , V , and V 54
IN OUT1 OUT2
Figure 4.14 Using a Fully Differential Op Amp to Drive an Analog-to-Digital
Converter 54
Figure 4.15 Instrumentation Amplifier 55
List of Figures xiii
Figure 4.16 High-Precision Differential Amplifier 56
Figure 4.17 Difference Amplifier 56
Figure 4.18 High Side Current Monitor 57
Figure 4.19 Commercial Difference Amplifier 58
Figure 4.20 A Better Way to Use a Buffer Amplifier 60
Figure 4.21 Paralleling Buffer Amplifiers 61
Figure 5.1 Focusing on the Power Supply Characteristics 66
Figure 5.2 Focusing on the Input Signal 67
Figure 5.3 Focusing on the Analog-to-Digital Converter 68
Figure 5.4 Focusing on the Operational Amplifiers 69
Figure 5.5 Single-Ended to Fully Differential AC Coupled Interface 70
Figure 5.6 Single-Ended to Fully Differential AC Coupled Interface 71
Figure 6.1 Unity-Gain Sallen(cid:1)Key Low-Pass Filter 74
Figure 6.2 Second Order Unity-Gain Tschebyscheff Low-Pass with 3 dB Ripple 76
Figure 6.3 Low-Pass Response (cid:1) Go to Section 6.3.2 78
Figure 6.4 High-Pass Response (cid:1) Go to Section 6.3.3 78
Figure 6.5 Narrow (Single-Frequency) Band Pass (cid:1) Go to Section 6.3.4 79
Figure 6.6 Wide Band Pass (cid:1) Go to Section 6.3.6 79
Figure 6.7 Single-Frequency Notch Filter 79
Figure 6.8 Low-Pass Filter 80
Figure 6.9 High-Pass Filter 81
Figure 6.10 Narrow Bandpass Filter 82
Figure 6.11 Wide Bandpass Filter 83
Figure 6.12 Notch Filter 85
Figure 6.13 Variable-Frequency Notch Filter 85
Figure 6.14 Open-loop Response 86
xiv List of Figures
Figure 6.15 Bandpass Response 87
Figure 6.16 Notch Filter Response 89
Figure 6.17 Three-Pole Low-Pass Filter 90
Figure 6.18 Three-Pole High-Pass Filter 91
Figure 6.19 Twin-T Bandpass Filter Response 91
Figure 6.20 Modified Twin-T Topology 92
Figure 6.21 Two Twin-T Networks Inside the Feedback Loop 93
Figure 6.22 Stagger-Tuned Filter Response 94
Figure 6.23 Multiple-Peak Bandpass Filter 94
Figure 6.24 Single-Amplifier Twin-T Notch Filter 95
Figure 6.25 Twin-T Band Reject Filter 96
Figure 6.26 Single-Amplifier Twin-T Notch and Bandpass Filter 97
Figure 6.27 Universal Filter Schematic 98
Figure 6.28 Universal Filter Calculator 99
Figure 6.29 Universal Filter Board 100
Figure 6.30 Notch Filter Calculator 101
Figure 6.31 Notch Filter PCB 102
Figure 6.32 Twin-T Filter Calculator 103
Figure 6.33 Twin-T PCB 103
Figure 7.1 A Traditional Radiofrequency Stage 106
Figure 7.2 Non-Inverting Radiofrequency Op Amp Gain Stage 107
Figure 7.3 Frequency Response Peaking 110
Figure 7.4 Noise Bandwidth 112
Figure 7.5 Typical Global System for Mobile Communications (GSM)
Cellular Base Station Receiver Block Diagram 113
Figure 7.6 Broadband Radio frequency Intermediate-Frequency Amplifier 114
Figure 7.7 Wideband Response 114
List of Figures xv
Figure 7.8 Intermediate-Frequency Amplifier Response 117
Figure 7.9 Single-Ended to Differential Output Drive Circuit 118
Figure 8.1 Rail-to-Rail Output (RRO) Stage 120
Figure 8.2 Input Circuit of a Non-Rail-to-Rail Input Op Amp 122
Figure 8.3 Input Circuit of a Rail-to-Rail Input Op Amp 123
Figure 8.4 Input Offset Voltage and Bias Current Changes with Input
Common-Mode Voltage 123
Figure 10.1 Voltage Regulator Operation 141
Figure 10.2 Switching Regulator 144
Figure 10.3 Overvoltage Protection Circuit 145
Figure 10.4 Active Load 146
Figure 10.5 Voltage Regulator Calculator 148
Figure 11.1 Digital Control System 152
Figure 11.2 DAC Current Sink to Actuator Interface Circuit 152
Figure 11.3 Oscillator Schematics 154
Figure 11.4 Oscillator Outputs 154
Figure 11.5 Comparator Oscillator Analysis 155
Figure 11.6 Composite Op Amp 156
Figure 11.7 Composite High-Frequency Op Amp 157
Figure 11.8 Composite High-Speed Op Amp with Power Boosting 158
Figure 11.9 High-Speed Bridged Hybrid Amplifier 159
Figure 12.1 Tina-TI Simulation 163
Figure 12.2 Filter Pro Opening Screen 165
Figure 12.3 Filter Pro Step 2 166
Figure 12.4 Filter Pro Step 3 167
Figure 12.5 Filter Pro Step 4 168
Figure 12.6 Filter Pro Final Design 168
xvi List of Figures
Figure 12.7 Webench Opening Screen 169
Figure 12.8 Webench Filter Design Section 169
Figure 12.9 Webench Filter Parameter Entry 170
Figure 12.10 Webench Final Design 171
Figure 12.11 OpAmp Error Budget Top Box 173
Figure 12.12 OpAmp Error Budget Parameter Entry and Results 174
Figure 12.13 LT Spice Filter Design 175
Figure 12.14 LT Spice Simulation Results 176
Figure 13.1 Op Amp Attenuator Done Wrong 180
Figure 13.2 Op Amp Attenuator Done Correctly 180
Figure 13.3 Similar Schematic Symbols, Very Different Parts! 181
Figure 13.4 Example Op Amp Schematic 181
Figure 13.5 Example Comparator Schematic 182
Figure 13.6 Different Ways of Dealing with Unused Op Amp Sections 184
Figure 13.7 Unexpected DC Gain 186
Figure 13.8 Incorrect and Correct Application of Current Feedback Amplifiers 187
Figure 13.9 Voltage Feedback vs. Current Feedback Amplifier
Stability vs. Load Resistor 187
Figure 13.10 Capacitor in Feedback Loop of Current Feedback Amplifier 188
Figure 13.11 Incorrect DC Operating Point 189
Figure 13.12 Correct DC Operating Point 189
Figure 13.13 Common-Mode Error 190
Figure 13.14 Effects of V on Outputs 191
OCM
Figure 13.15 Terminating a Fully Differential Amplifier 192
Figure 13.16 Using an Input Stage with a Fully Differential Amplifier 192
Figure A.1 Gain and Phase Margin 199
Figure A.2 Open-Loop Parameters 199
List of Figures xvii
Figure A.3 Input Parasitic Elements 202
Figure A.4 Slew Rate 212
Figure A.5 Offset Voltage Adjust 218
Figure B.1 Gaussian Distribution of Noise Energy 227
Figure B.2 Noise Colors 229
Figure B.3 Typical Op Amp Noise Characteristics 231
Figure C.1 Digital and Analog Plane Placement 241
Figure C.2 Broadcasting from PCB Traces 243
Figure C.3 A Careful Board Layout 243
Figure C.4 Resistor High-Frequency Model 244
Figure C.5 Capacitor High-Frequency Model 245
Figure C.6 Inductor High-Frequency Model 246
Figure C.7 Loop and Slot Antenna Board Trace Layouts 249
Figure C.8 PCB Trace Corners 249
Figure C.9 PCB Trace-to-Plane Capacitance Formula 250
Figure C.10 Coupling Between Parallel Signal Traces 251
Figure C.11 Via Inductance Measurements 251
Figure C.12 Typical Logic Gate Output Structure 253
Figure C.13 Capacitor Self-Resonance 254
Figure C.14 PCB Shield 256
Figure C.15 Common Op Amp Pinouts 257
Figure C.16 Mirror-Image Layout for Quad Op Amp Package 257
Figure C.17 Quad Op Amp Package Layout with Half-Supply Generator 258
Figure D.1 Simulated Inductor 262
Figure D.2 Graphic Equalizer 262
Figure D.3 Constant Current Generator 263