On the Metrology of Nanoscale Silicon Transistors above 100 GHz

235 Pages·2011·10.43 MB·English

by  Kenneth Yau

ON THE METROLOGY OF NANOSCALE SILICON TRANSISTORS
ABOVE 100 GHz
by
Kenneth Hoi Kan Yau
A thesis submitted in conformity with the requirements
for the degree of Doctor of Philosophy
Graduate Department of Electrical and Computer Engineering
University of Toronto
(cid:2)c Kenneth Hoi Kan Yau, 2011
On the Metrology of Nanoscale Silicon Transistors Above 100 GHz
Kenneth Hoi Kan Yau
Doctor of Philosophy, 2011
Graduate Department of Electrical and Computer Engineering
University of Toronto
Abstract
T
HIS thesis presents the theoretical and experimental framework for the development of
accurate on-wafer S-parameter and noise parameter measurements of silicon devices in
the upper millimetre-wave frequency range between 70 GHz and 300 GHz. Novel integrated
noise parameter test setups were developed for nanoscale MOSFETs and SiGe HBTs and val-
idated up to 170 GHz. In the absence of accurate foundry models in this frequency range,
the experimental findings of this thesis have been employed by other graduate students to
design the first noise and input impedance matched W- and D-band low-noise amplifiers in
nanoscale CMOS and SiGe BiCMOS technologies. The results of the D-band S-parameter
characterization techniques and of the new Y-parameter based noise model have been used by
STMicroelectronics to optimize the SiGe HBT structure for applications in the D-band.
In the first half of the thesis, theoretical analysis indicates that, for current silicon devices,
distributiveeffectsinteststructureparasiticswillbecomesignificantonlybeyond300GHz. This
conclusion is supported by experiments which compare the lumped-element based open-short
andthetransmissionlinebasedsplit-thrude-embeddingtechniquestothemultilinethru-reflect-
line (TRL) network analyzer calibration algorithm.
Electromagnetic simulations and measurements up to 170 GHz demonstrate that, for mi-
crostrip transmission lines with metal ground plane placed above the silicon substrate, the line
capacitance per unit length remains a weak function of frequency. Based on this observation,
the multiline TRL algorithm has been modified to include a dummy short de-embedding struc-
ture. This allowed for the first time to perform single step calibration and de-embedding of
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silicon devices using on-silicon calibration standards. The usefulness of the proposed method
was demonstrated on the extraction of the difficult-to-measure SiGe HBT and nanoscale MOS-
FET model parameters, including transcondutance delay, τ, gate resistance, source resistance,
drain-source capacitance, and channel resistance, R .
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Building on the small-signal characterization technique developed in the first half, a new Y-
parameterbasednoisemodelforSiGeHBTs,thatincludesthecorrelation betweenthebaseand
collector shot noise currents, is proposedin the second half of the thesis along with a method to
extract thenoise transittime parameter. With this model, thehigh frequency noise parameters
of a SiGe HBT can becalculated from the measured Y-parameters, withoutrequiring any noise
figure measurements.
Finally, to validate the proposed noise model, the first on-wafer integrated noise parameter
measurement systems were designed and measured in the W- and D-bands. The systems
enable millimetre-wave noise parameter measurements with the multi-impedance method by
integrating theimpedancetunerandan entire millimetre-wave noisereceiver on thesamedieas
the device-under-test. Good agreement was obtained between the noise parameters calculated
from the Y-parameter measurements and those obtained from direct noise figure measurements
with the integrated systems. The results indicate that the minimum noise figure of state-of-the-
art advanced SiGe HBTs remains below 5 dB throughout the D-band, making them suitable
for a variety of commercial products in this frequency range.
Acknowledgements
I am grateful for the guidance and support provided by my advisor, Prof. Sorin Voinigescu,
during my pursuit of this thesis research. Without his experience, insight, and advice, a thesis
of this magnitude would not be possible. I am indebted to Prof. Wai Tung Ng, Prof. George
Eleftheriades, Prof. Anthony Chan Carusone, and Prof. Sean Hum for participating in the
Departmental and University thesis defenses. Their critique of the thesis made it a better piece
of work. I would also like to acknowledge the comments from my external examiner, Dr. Jack
Pekarik, of IBM Corporation, Essex Junction VT, in the preparation of the final version of the
thesis.
The fabrication of the silicon test structures and circuits was provided by STMicroelec-
tronics, Crolles, France, and the Taiwan Semiconductor Manufacturing Company (TSMC),
Hsinchu, Taiwan. The thesis would not be possible without the assistance of Dr. Pascal Cheva-
lier, Dr. Gregory Avenier, and Dr. Alain Chantre of STMicroelectronics, and Dr. Ming-Ta
Yang of TSMC. Financial and equipment grant support received from the Natural Science and
Engineering Council of Canada (NSERC) are gratefully acknowledged.
The pursuit of the doctorate degree was not a solitary effort. Throughout the years, I am
fortunate to have worked with a group of wonderfulcolleagues. I am thankfulfor the friendship
and assistance of Ricardo Aroca, Andreea Balteanu, Theodoros Chalvatzis, Timothy Dickson,
Ekaterina Laskin, Alain Mangan, Ioannis Sarkas, Shahriar Shahramian, and Terry Yao. The
long nights were made possible with all your help.
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Finally,Iwouldliketothankmyparents,mybrother,andmywife,Janice. Theirunwavering
love, care, and support provided me with the energy I need to pursuit this research project.
“but those who hope in the LORD will renew their strength. They will soar on
wings like eagles; they will run and not grow weary, they will walk and not be
faint.”
Isaiah 40:31
Table of Contents
Abstract ii
Acknowledgements iv
List of Tables x
List of Figures xxiii
List of Abbreviations xxiv
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Silicon On-Wafer Device Characterization: State of the Art . . . . . . . . . . . . 4
1.3 Thesis Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Fundamentals of On-Wafer S-Parameter Characterization 7
2.1 Scattering Parameter Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 Switch Term Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.2 Cascade Error Box Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.3 12-Term VNA Error Model . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.4 First-Tier and Second-Tier Calibrations . . . . . . . . . . . . . . . . . . . 18
2.1.5 Multiline TRL Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2 De-Embedding of DUT Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
vi
Table of Contents vii
2.2.1 Open De-Embedding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2.2 Two-Step Open-Short De-Embedding . . . . . . . . . . . . . . . . . . . . 29
2.2.3 Split-Thru De-Embedding . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3 Fundamentals of Millimetre-Wave Transistor Noise 35
3.1 Thermal Noise Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.2 Description of a Noisy Two-Port Network . . . . . . . . . . . . . . . . . . . . . . 39
3.3 Noise Figure and Noise Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.4 Noise Metrology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.4.1 The Y-Factor Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.4.2 Cold-Source Noise Measurements . . . . . . . . . . . . . . . . . . . . . . . 46
3.4.3 Validity Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4 W- and D-Band On-Wafer S-Parameter Calibration and De-Embedding 51
4.1 Calibration, De-Embedding and Their Equivalence . . . . . . . . . . . . . . . . . 52
4.2 VNA Calibration Algorithms for Silicon On-Wafer Characterization . . . . . . . 55
4.3 Multiline TRL for On-Wafer Calibration and De-Embedding . . . . . . . . . . . 57
4.3.1 Multiline TRL for Silicon Device Characterization . . . . . . . . . . . . . 58
4.3.2 Transmission Line Characteristic Impedance Determination . . . . . . . . 61
4.3.3 Ground Inductance Extraction . . . . . . . . . . . . . . . . . . . . . . . . 63
4.4 Experimental Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.4.1 Microstrip Transmission Lines. . . . . . . . . . . . . . . . . . . . . . . . . 66
4.4.2 Metal-Insulator-Metal Capacitor . . . . . . . . . . . . . . . . . . . . . . . 75
4.4.3 Transformer and Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.4.4 Directional Coupler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.4.5 65 nm n-MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.4.6 130 nm SiGe HBTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.4.7 Ground Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.4.8 Comparison with Open-Short De-Embedding . . . . . . . . . . . . . . . . 94
Table of Contents viii
4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5 SiGe HBT Noise Modelling 100
5.1 Derivation of Noise Parameter Equations . . . . . . . . . . . . . . . . . . . . . . 100
5.1.1 Noise Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.1.2 Thermal Noise Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.1.3 Shot Noise Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.1.4 SiGe HBT Noise Parameter Equations . . . . . . . . . . . . . . . . . . . . 103
5.2 Noise Parameter Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.2.1 Junction Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.2.2 Access Resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.2.3 Noise Transit Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6 Design of On-Wafer Noise Parameter Measurement Systems 111
6.1 SiGe BiCMOS Source-Pull Systems . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.1.1 Analog W-Band Microstrip Tuner . . . . . . . . . . . . . . . . . . . . . . 119
6.1.2 Digital W-Band Microstrip Tuner . . . . . . . . . . . . . . . . . . . . . . 122
6.1.3 Digital D-Band Microstrip Tuner . . . . . . . . . . . . . . . . . . . . . . . 123
6.2 65 nm CMOS Source-Pull System. . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.2.1 W-Band Downconverters . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.2.2 W-Band Microstrip Tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
7 On-Wafer Source-Pull Noise Parameter Measurements 131
7.1 Calibration and Measurement Procedure . . . . . . . . . . . . . . . . . . . . . . . 131
7.1.1 S-Parameter Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7.1.2 Noise Parameter Measurements . . . . . . . . . . . . . . . . . . . . . . . . 132
7.2 SiGe BiCMOS Source-Pull Noise Parameter Systems . . . . . . . . . . . . . . . . 133
7.2.1 Compact Model Validation . . . . . . . . . . . . . . . . . . . . . . . . . . 134
7.2.2 Extraction of Noise Transit Time . . . . . . . . . . . . . . . . . . . . . . . 143
Table of Contents ix
7.2.3 W-Band Analog and Digital Microstrip Tuners . . . . . . . . . . . . . . . 145
7.2.4 D-Band Digital Microstrip Tuner . . . . . . . . . . . . . . . . . . . . . . . 149
7.2.5 W-Band SiGe HBT Noise Parameters . . . . . . . . . . . . . . . . . . . . 152
7.2.6 D-band SiGe HBT Noise Parameters . . . . . . . . . . . . . . . . . . . . . 156
7.2.7 Impact of Shot Noise Correlation . . . . . . . . . . . . . . . . . . . . . . . 161
7.2.8 SiGe HBT Noise Parameters in Different Technology Generations and
Process Splits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
7.3 65 nm CMOS Source-Pull Noise Parameter System . . . . . . . . . . . . . . . . . 170
7.3.1 W-Band NF of GP and LP n-MOSFETs . . . . . . . . . . . . . . . . . 170
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7.3.2 W-Band Microstrip Tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
7.3.3 W-Band Low Noise Amplifier Noise Parameters . . . . . . . . . . . . . . . 176
7.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
8 Conclusions 183
8.1 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
8.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
8.3 List of Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
A Matlab Code 186
A.1 Second-Tier Multiline TRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
B Summary of Network Analyzer Calibration Algorithms 196
B.1 Short-Open-Load-Thru. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
B.2 Line-Reflect-Match and Line-Reflect-Reflect-Match . . . . . . . . . . . . . . . . . 197
B.3 Thru-Reflect-Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Bibliography 199
List of Tables
2.1 Vector network analyzer 12-term error model parameters. . . . . . . . . . . . . . 14
4.1 Summary of simulated line capacitance per unit length . . . . . . . . . . . . . . . 69
6.1 MOSFET switch model parameters for 0.13μm×2μm gate fingers at 82 GHz. . . 120
6.2 65 nm GP and LP n-MOSFET device parameters. . . . . . . . . . . . . . . . . . 126
6.3 65 nm LP n-MOSFET switch parameters for 1 μm wide fingers at 82 GHz. . . . 128
x