Number systems and Digit Serial Arithmetic

243 Pages·2007·1.24 MB·English

Ph.D. Thesis
Number systems
and
Digit Serial Arithmetic
Asger Munk Nielsen
Dept. of Mathematics and Computer Science
Odense University
Denmark
August 1997

Acknowledgments
I would like to thank my adviser professor Peter Kornerup for his supportive
and \mentor like" attitude, which has made the writing of this thesis a plea-
sure. I would also like to thank dr. Jean-Michel Muller, Laboratoire LIP and
CNRS, Ecole Normale Sup(cid:19)erieure de Lyon and David W. Matula, SEAS, South-
ern Methodist University, Texas for inviting me to visit their respective groups
and hosting enjoyablestays. Thanks are also due to the Danish ResearchCouncil
for (cid:12)nancial support, and to Marc Daumas and Guy Even for useful help and
valuable friendship.
Asger Munk Nielsen
Odense, August 1997.
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Summary
Chapter 1 gives a brief introduction to number representations and the con-
cept of parallel and digit serial arithmetic computation.
Chapter 2 presents a thorough analysis of radix representations of elements
from general rings, in particular the questions of redundancy, completeness and
mappings into such representations are studied. After a brief description of the
moreusualrepresentationsofintegers,amoredetailedanalysisofvariouscomplex
number systems is performed. This includes the \classical" complex number
systems for the Gaussian integers, as well as the Eisenstein integers.
Chapter 3 deals with base and digit-set conversion in the general context of
radix polynomials. Both parallel and serial conversion techniques,as well as con-
version into redundant and non redundant digit sets are examined. Examplesare
given in the form of conversion procedures for various complex number systems.
In Chapter 4, after a short introduction to the classical borrow-save adder,
similaradders for some classical real and complexnumber systemsare presented.
A possible application for the presented adders are discussed, in the form of a
recon(cid:12)gurable multiplier.
Chapter 5 presents dedicated on-line operators for computation with com-
p
plex numbers. The numbers are convenientlyrepresented in base 2 or (cid:0)2 with
borrow-save encoding of the digits. The presented solutions are compared with
equivalent operators obtained from real on-line operators, (cid:12)nally estimates of
the theoretical lower bound on the on-line delay of some complex operators are
calculated.
Chapter 6 presents an on-line comparator, capable of extracting the mini-
mum and maximum of two redundant radix (cid:12) numbers. An on-line algorithm
with zero on-line delay is developed. Based on this algorithm a (cid:12)nite state trans-
ducer, with O(1) states and O((cid:12)) transitions, is devised. As an example of the
utilization of the on-line comparator module, circuits sorting redundant numbers
are shown, as well as an application in image processing.
In Chapter 7 a new on-line algorithm for fast evaluation of logarithms and
exponentials is proposed. This algorithm is derived from the widely studied
Briggs-De Lugish iteration. Various compromises between the on-line delay and
the size of the required comparison constants are explored.
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In Chapter 8 a formal account of digit serial number representations is de-
veloped, by describing them as strings from a language. A pre(cid:12)x of a string
represents an interval approximating a number by enclosure. Standard on-line
representations are shown to be a special case of the general digit serial repre-
sentations. Matrices are introduced as representations of intervals and a (cid:12)nite-
state transducer is used for mapping strings into intervals. Homographic and
bi-homographic functions are used for representing basic arithmetic operations
on digit serial numbers, and (cid:12)nally a digit serial representation of (cid:13)oating point
numbers is introduced.
Chapter 9 covers the background and motivation for a new (cid:13)oating point
paradigm: Pipelined Packet-Forwarding Floating Point Arithmetic. The idea
behind this project is to enhance the use of redundancy in modern pipelined pro-
cessors, thereby achieving better utilization of the (cid:13)oating point functional units.
Bydividing(cid:13)oating point operands into packets that are produced and consumed
in a temporally staggered format, pipeline stalling e(cid:11)ects due to operand depen-
dencies can be reduced.
Contents
Acknowledgments i
Summary iii
1 Introduction 1
1.1 Radix Representations . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 LSD-(cid:12)rst Digit Serial Computation . . . . . . . . . . . . . . . . . 4
1.3 MSD-(cid:12)rst Digit Serial Computation . . . . . . . . . . . . . . . . . 6
1.3.1 On-Line Arithmetic . . . . . . . . . . . . . . . . . . . . . . 8
1.3.2 The Merits of Digit Serial Arithmetic . . . . . . . . . . . . 11
1.4 Alternative Number Systems . . . . . . . . . . . . . . . . . . . . . 13
1.4.1 Interval Arithmetic . . . . . . . . . . . . . . . . . . . . . . 13
1.4.2 Continued Fractions . . . . . . . . . . . . . . . . . . . . . 14
1.4.3 Floating Point Systems . . . . . . . . . . . . . . . . . . . . 16
1.5 Motivation Behind the Thesis . . . . . . . . . . . . . . . . . . . . 17
I Number Systems and Conversion Algorithms 19
2 Radix Representations of Rings 21
2.1 On the Representation of Numbers . . . . . . . . . . . . . . . . . 22
2.2 Determining a Radix Representation . . . . . . . . . . . . . . . . 28
2.3 Representing the Integers. . . . . . . . . . . . . . . . . . . . . . . 34
2.4 Representing Complex Numbers . . . . . . . . . . . . . . . . . . . 36
2.4.1 Representing the Gaussian Integers . . . . . . . . . . . . . 36
2.4.2 Complex Number Systems with Integer Radix . . . . . . . 38
2.4.3 Imaginary Radix Number systems . . . . . . . . . . . . . . 39
2.4.4 Complex Radix Number Systems . . . . . . . . . . . . . . 41
2.5 Representing Eisenstein Integers . . . . . . . . . . . . . . . . . . . 44
2.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3 Base and Digit Set Conversion 49
3.1 General Considerations . . . . . . . . . . . . . . . . . . . . . . . . 50
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vi CONTENTS
3.2 Base Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.3 Conversion into Non-Redundant Digit Sets . . . . . . . . . . . . . 54
3.4 Conversion into Redundant Digit Sets . . . . . . . . . . . . . . . . 61
3.4.1 Digit Set Conversion into Redundant Integer Systems . . . 65
3.4.2 Digit Set Conversion into Redundant Complex Number
Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4 Borrow-Save Adders for Real and Complex Number Systems 71
4.1 Borrow-Save Addition . . . . . . . . . . . . . . . . . . . . . . . . 72
4.1.1 Hybrid Addition and Subtraction . . . . . . . . . . . . . . 73
4.1.2 Negative-Base Borrow Save Addition . . . . . . . . . . . . 75
4.2 Carry-Free Addition in Complex Number Systems . . . . . . . . . 77
4.2.1 The Two-Register Solution . . . . . . . . . . . . . . . . . . 78
4.2.2 A Non-Conventional Representation . . . . . . . . . . . . . 78
4.2.3 The Knuth Number System . . . . . . . . . . . . . . . . . 79
4.2.4 Penneys Complex Number System . . . . . . . . . . . . . 81
4.3 Addition of Several Terms . . . . . . . . . . . . . . . . . . . . . . 82
4.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
II On-Line Arithmetic 87
5 On-line Operators for Complex Valued Arithmetic 89
5.1 On-Line Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.1.1 On-line Adder Synthesis . . . . . . . . . . . . . . . . . . . 92
5.2 Complex On-line Multiplication . . . . . . . . . . . . . . . . . . . 97
5.3 Multiplication by a Constant . . . . . . . . . . . . . . . . . . . . . 101
5.3.1 Other Approaches . . . . . . . . . . . . . . . . . . . . . . . 102
5.4 Related Operators . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.5 Lower Bound on On-line Delay for Complex Operators . . . . . . 107
5.6 On-line Multiplication With Low Delay . . . . . . . . . . . . . . . 109
p
5.7 Complex Multiplication Using a Base 2i System . . . . . . . . . 110
5.8 Comparison With the radix 2 Approach . . . . . . . . . . . . . . 111
5.9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6 An On-line Comparator and Related Algorithms 115
6.1 The algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.2 A Finite State Transducer Implementation . . . . . . . . . . . . . 120
6.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.3.1 Image Processing . . . . . . . . . . . . . . . . . . . . . . . 122
6.3.2 On-line Sorting . . . . . . . . . . . . . . . . . . . . . . . . 123
6.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
CONTENTS vii
7 On-lineAlgorithmsforComputingExponentialsand Logarithms127
7.1 Selection of Digits and Domain of Convergence . . . . . . . . . . . 128
7.1.1 Computing Exponentials . . . . . . . . . . . . . . . . . . . 128
7.1.2 Computing Logarithms . . . . . . . . . . . . . . . . . . . . 130
7.2 On-Line Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . 132
7.2.1 Hardware Requirements . . . . . . . . . . . . . . . . . . . 135
7.3 Choice of Constants and On-line Delay . . . . . . . . . . . . . . . 135
7.4 Digitization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7.4.1 Applying Digitization to the Output of On-line Exp/Log
Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
7.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
8 A General Framework for MSD-First Digit Serial Arithmetic 143
8.1 Digit Serial Representations of Numbers . . . . . . . . . . . . . . 144
8.2 Homographic Matrix Coding . . . . . . . . . . . . . . . . . . . . . 151
8.3 Operations Computable With Homographic Functions . . . . . . . 156
8.4 The Cube . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
8.5 Digit Serial Floating Point Operands . . . . . . . . . . . . . . . . 163
8.6 Determining the Range of the Function . . . . . . . . . . . . . . . 165
8.7 Testing for Emission of Output . . . . . . . . . . . . . . . . . . . 170
8.8 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
8.8.1 Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . 171
8.8.2 Arithmetic Unit . . . . . . . . . . . . . . . . . . . . . . . . 172
8.8.3 Root Evaluation . . . . . . . . . . . . . . . . . . . . . . . 173
8.8.4 Interval inclusion test . . . . . . . . . . . . . . . . . . . . . 173
8.9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
III Floating Point Arithmetic 177
9 Pipelined Packet-Forwarding Floating Point Arithmetic 179
9.1 The IEEE Floating Point Standard . . . . . . . . . . . . . . . . . 179
9.1.1 Rounding Modes . . . . . . . . . . . . . . . . . . . . . . . 180
9.2 Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
9.3 Floating Point Functional Units . . . . . . . . . . . . . . . . . . . 183
9.4 A Redundant Floating Point Format . . . . . . . . . . . . . . . . 185
9.5 Rounding of Packet-Forwarding Floating Point Operands . . . . . 189
9.6 Packet-Forwarding Floating Point Multiplication . . . . . . . . . . 190
9.7 Packet-Forwarding Floating Point Addition . . . . . . . . . . . . . 190
9.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Conclusion 195
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A Implementation of Logic Blocks 197
B Circuit Transformation 201
B.1 Trading Time for Space . . . . . . . . . . . . . . . . . . . . . . . . 201
B.2 Initialization of Registers . . . . . . . . . . . . . . . . . . . . . . . 203
C A Recon(cid:12)gurable Multiplier 207
C.1 Reducing the Number of Partial Products by Booth Recoding . . 208
C.2 Partial Product Generation . . . . . . . . . . . . . . . . . . . . . 211
C.3 Recon(cid:12)gurable Borrow-Save Adders . . . . . . . . . . . . . . . . . 214
D Pipelined Packet-Forwarding Floating Point: I. Foundations and
a Rounder 217
E Pipelined Packet-Forwarding Floating Point: II. An Adder 227
Sammenfatning (Summary in Danish) 237