NASA Technical Reports Server (NTRS) 20130009446: On-Chip Power-Combining for High-Power Schottky Diode-Based Frequency Multipliers

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by  NASA Technical Reports Server (NTRS)

Electronics/Computers
DSP/FPGA Design for a High-Speed Programmable S-Band
Space Transceiver
Goddard Space Flight Center, Greenbelt, Maryland
Traditional command uplink re- mand receiver. There are several driv- The demodulator operates on the
ceivers are very limited in performance ers available for the modulation tech- two selected modes, BPSK and GMSK.
capability, take a long time to acquire, nique. Those drivers include receiver The bit rate covers multiple octaves
cannot operate on both uplink bands complexity, power consumption, spec- and includes a bit synchronizer func-
(NASA & AFSCN), and only support tral efficiency, and CCSDS (Consulta- tion. The modulator is unique in that it
low-rate communications. As a result, tive Comm ittee for Space Data Sys- operates with high Doppler, over a
transceivers end up on many programs’ tems) framework recommendations. large bit rate range, and in a space en-
critical paths, even though they should Previous res earch suggests that GMSK vironment. In addition, this demodula-
be a standard purchased spacecraft sub- (Gaussian Minimum Shift Keying) and tor attempts to maximize low power,
system. Also, many missions are im- BPSK (Binary Phase Shift Keying) are small size, and ease of modification to
pacted by the low effective uplink good choices for the uplink modula- new applications.
throughput. In order to tackle these tion format. This approach is sup- Novel features of the innovation in-
challenges, a transceiver was developed ported by CCSDS and helps reduce re- clude DSP logic for multiple modulation
that will provide on-site frequency ceiver complexity. types in a low-power and rad-tolerant
agility, support of high uplink rates, and Analysis and derived simulations platform. Advantages include on-the-fly
operation on both NASA and AFSCN were performed for power, bandwidth, programmable low-power receive com-
frequency bands. clock generator, bit synchronizer, and munications for spacecraft.
The device is a low-power, high-relia- carrier loop. At the time of this report- This work was done by Jeffrey Janicik and
bility, and high-performance digital ing, the code was not yet written, and Assi Friedman of Innoflight, Inc. for Goddard
signal processing (DSP) demodulator will evolve from the existing analysis Space Flight Center. Further information is con-
for an on-orbit programmable com- and simulation. tained in a TSP (see page 1).GSC-16030-1
On-Chip Power-Combining for High-Power Schottky Diode-
Based Frequency Multipliers
High-power solid-state sources operate at terahertz frequencies.
NASA’s Jet Propulsion Laboratory, Pasadena, California
A 1.6-THz power-combined Schottky
frequency tripler was designed to handle
approximately 30 mW input power. The Multiplier
design of Schottky-based triplers at this Chips
frequency range is mainly constrained
by the shrinkage of the waveguide di-
mensions with frequency and the mini- Input
mum diode mesa sizes, which limits the Waveguide
maximum number of diodes that can be
placed on the chip to no more than two.
Output
Hence, multiple-chip power-combined Waveguide
schemes become necessary to increase DC Bias
the power-handling capabilities of high-
frequency multipliers. However, the tra-
ditional power-combining topologies
that are used below 1 THz present some
inconvenience beyond 1 THz. The use
of Y-junctions or hybrid couplers to di-
vide/combine the input/output power
0 300 600µm
at these frequency bands increases un-
necessarily the electrical path of the sig- 1.9 THz On-Chip Power-Combining (2 chips).
NASA Tech Briefs, January 2013 13
nal in the range of frequencies where ment and symmetry of the circuits can Fellow at NASA’s Jet Propulsion Laboratory;
waveguide losses are considerable. Also, be very well preserved. Contrary to tradi- Alain E. Maestrini of the University of Paris;
guaranteeing a perfect alignment of the tional frequency triplers, in this design Bertrand Thomas of Radiometer Physics; and
very small chips during assembly, in the input and output waveguides are Cecile D. Jung of ORU for NASA’s Jet Propul-
order to preserve the balanced nature of perpendicular to the waveguide chan- sion Laboratory. Further information is con-
the multiplier, is practically impossible nels where the diodes are located. tained in a TSP (see page 1).
with the subsequent impact on the mul- Therefore, the multiplier block is easier In accordance with Public Law 96-517,
tiplier performance. to fabricate with silicon micromachining the contractor has elected to retain title to this
The design presented here overcomes technology instead of regular machin- invention. Inquiries concerning rights for its
these difficulties by performing the ing. The expected conversion efficiency commercial use should be addressed to:
power-combining directly on-chip. Four of the tripler is ≈2 to 3% over a ≈20% Innovative Technology Assets Management
E-probes are located at a single input bandwidth, which is similar to that JPL
waveguide in order to equally pump which is simulated for an equivalent sin- Mail Stop 202-233
four mulitplying structures (featuring gle-chip tripler driven with one fourth 4800 Oak Grove Drive
two diodes each). The produced output the input power. Pasadena, CA 91109-8099
power is then recombined at the output This work was done by Goutam Chattopad- E-mail: [email protected]
using the same concept. The four multi- hyay, Imran Mehdi, Erich T. Schlecht, and Refer to NPO-48155, volume and number
plying structures are physically con- Choonsup Lee of NASA’s Jet Propulsion Lab- of this NASA Tech Briefs issue, and the
nected on one chip, so that the align- oratory and Caltech; Jose V. Siles – Fulbright page number.
FPGA Vision Data Architecture
This is an aid to any FPGA vision processing, and can be used by the automotive industry to
detect collisions before they occur, and for robotic autonomous navigation for disaster relief.
NASA’s Jet Propulsion Laboratory, Pasadena, California
JPL has produced a series of FPGA quirements. Some required serial ac- and writes of different sizes. R32 means
(field programmable gate array) vision cess to data, and some were random ac- a read agent of width 32 bits, and W8
algorithms that were written with cus- cess. There were 8-bit, 16-bit, and 32-bit means a write agent of width 8 bits. Each
tom interfaces to get data in and out of input/output widths. Three modules memory bank has a single arbiter that
each vision module. Each module has could connect directly together in a se- handles all memory requests to its bank.
unique requirements on the data inter- ries or go directly to memory, depend- Each agent maps to a single arbiter, but
face, and further vision modules are ing on runtime configuration options. because this mapping will be dependent
continually being developed, each with One of the larger difficulties was posed upon the memory devices used and the
their own custom interfaces. by the random read access. For indus- number of memory devices available
Each memory module had also been try-standard buses such as AMBA, PLB, (i.e. two DDR banks vs. six SSRAM
designed for direct access to memory or or OPB, a single random-read request banks), there is a large multiplexer
to another memory module. On the de- can take 5 to 10 clock cycles, locking called the “vision agent to bank map-
velopment board originally used (an out all other users on the bus until the ping,” which assigns agents to appropri-
Alpha Data XRC4), there were six inde- request was complete. This is far too ate arbiters and memory banks.
pendent SSRAM (synchronous static slow for the vision modules and would Each agent can queue multiple mem-
RAM) banks that allowed each module effectively reduce performance by 2 to ory requests and queue multiple re-
sole access. For a flight mission, there 5 times. sponses from memory. This allows burst-
likely would be between one and three An architecture was created that met ing of data for high throughput, and
memory banks, and arbitration of those the same data throughput as the prior de-couples the action of requesting
banks would need to be supported, in- custom interface that had no arbitra- memory from the action of receiving
terleaving access to individual memory tion. The new architecture also allowed data. Many of the vision modules have
banks between multiple modules. for multiple memory types (DDR, one part dedicated to computing the lo-
An FPGA data architecture was re- DDRII, SSRAM, NAND memory) with- cation of the next request, and a sepa-
quired to allow arbitration to onboard out any modification of the FPGA vision rate part dedicated to handling the data
DDR (double data rate) and/or SSRAM modules themselves. at that location.
memory, and to allow up to 10 to 30 in- The current Rover Navigation FPGA This work was done by Arin C. Morfopoulos
dependent agents access to that mem- Vision system contains five vision mod- and Thang D. Pham of Caltech for NASA’s Jet
ory. It also required a method of ex- ules: Rectification, Filtering, Disparity, Propulsion Laboratory. Further information is
changing data directly between modules Feature Detector (via a Harris detector), contained in a TSP (see page 1).
without reducing the throughput of and Visual Odometry score computation This invention is owned by NASA, and a
memory access. This architecture also (via a sum of absolute differences opera- patent application has been filed. Inquiries
had to support both low-latency reads tor). Further modules to handle path concerning nonexclusive or exclusive license for
and writes, and offer high throughput. planning are likely. its commercial development should be ad-
Each FPGA vision module had Each vision module has an “agent” — dressed to the Patent Counsel, NASA Manage-
slightly different input and output re- an interface to memory for both reads ment Office–JPL. Refer to NPO-47869.
14 NASA Tech Briefs, January 2013