Nano-CMOS and post-CMOS electronics : circuits and design, Volume 2

439 Pages·2016·15.27 MB·English

by  Mohanty, Saraju P., Srivastava, Ashok N

MATERIALS,CIRCUITS&DEVICESSERIES30
Nano-CMOS
and Post-CMOS
Electronics:
Circuits and Design
Othervolumesinthisseries:
Volume2 AnalogueICDesign:Thecurrent-modeapproachC.Toumazou,F.J.Lidgeyand
D.G.Haigh(Editors)
Volume3 Analogue-DigitalASICs: Circuittechniques, designtoolsandapplications
R.S.Soin,F.MalobertiandJ.France(Editors)
Volume4 Algorithmic and Knowledge-based CAD for VLSI G.E. Taylor and G. Russell
(Editors)
Volume5 SwitchedCurrents:Ananaloguetechniquefordigitaltechnology
C.Toumazou,J.B.C.HughesandN.C.Battersby(Editors)
Volume6 High-frequencyCircuitEngineeringF.Nibleretal.
Volume8 Low-powerHigh-frequencyMicroelectronics:Aunifiedapproach
G.Machado(Editor)
Volume9 VLSITesting:Digitalandmixedanalogue/digitaltechniquesS.L.Hurst
Volume10 DistributedFeedbackSemiconductorLasersJ.E.Carroll,J.E.A.Whiteawayand
R.G.S.Plumb
Volume11 SelectedTopicsinAdvancedSolidStateandFibreOpticSensors
S.M.Vaezi-Nejad(Editor)
Volume12 StrainedSiliconHeterostructures:MaterialsanddevicesC.K.Maiti,
N.B.ChakrabartiandS.K.Ray
Volume13 RFICandMMICDesignandTechnologyI.D.RobertsonandS.Lucyzyn(Editors)
Volume14 DesignofHighFrequencyIntegratedAnalogueFiltersY.Sun(Editor)
Volume15 FoundationsofDigitalSignalProcessing:Theory,algorithmsandhardware
designP.Gaydecki
Volume16 WirelessCommunicationsCircuitsandSystemsY.Sun(Editor)
Volume17 TheSwitchingFunction:AnalysisofpowerelectroniccircuitsC.Marouchos
Volume18 SystemonChip:NextgenerationelectronicsB.Al-Hashimi(Editor)
Volume19 TestandDiagnosisofAnalogue,Mixed-signalandRFIntegratedCircuits:
ThesystemonchipapproachY.Sun(Editor)
Volume20 LowPowerandLowVoltageCircuitDesignwiththeFGMOSTransistor
E.Rodriguez-Villegas
Volume21 TechnologyComputerAidedDesignforSi,SiGeandGaAsIntegratedCircuits
C.K.MaitiandG.A.Armstrong
Volume22 NanotechnologiesM.Wauteletetal.
Volume23 UnderstandableElectricCircuitsM.Wang
Volume24 FundamentalsofElectromagneticLevitation:Engineeringsustainability
throughefficiencyA.J.Sangster
Volume29 Nano-CMOSandPost-CMOSElectronics:DevicesandModelling
SarajuP.MohantyandAshokSrivastava
Nano-CMOS
and Post-CMOS
Electronics:
Circuits and Design
Edited by
Saraju P. Mohanty
and Ashok Srivastava
TheInstitutionofEngineeringandTechnology
PublishedbyTheInstitutionofEngineeringandTechnology,London,UnitedKingdom
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Firstpublished2016
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Contents
Preface xiii
1 Self-healinganalog/RFcircuits 1
1.1 Introduction 1
1.2 Indirectperformancesensing 3
1.3 Pre-siliconindirectsensormodelingviaSR 4
1.3.1 L -normregularization 5
0
1.3.2 L -normregularization 7
1
1.3.3 AccuracyofL -normregularization 9
1
1.4 Post-siliconindirectsensorcalibrationviaBayesianmodelfusion 11
1.4.1 Priorknowledgedefinition 12
1.4.2 MAPestimation 14
1.5 On-chipself-healingflow 17
1.6 Casestudy 20
1.6.1 25GHzdifferentialColpittsVCO 20
1.6.2 60GHzLNA 26
1.7 Conclusion 32
References 32
2 On-chipgatedelayvariabilitymeasurementinscaled
technologynode 35
2.1 Introduction 35
2.2 Classificationofvariability 36
2.3 Sourcesofvariability 38
2.3.1 Randomdopantfluctuations 38
2.3.2 Lineedgeroughness 38
2.3.3 Oxidethicknessvariation 39
2.4 Relatedworkonvariabilitymeasurement 39
2.4.1 Gatedelayvariability 39
2.4.2 Riseandfallgatedelayvariability 41
2.5 Gatedelaymeasurementusingreconfigurableringoscillator 42
2.5.1 Gatedelaymeasurementcell 42
2.5.2 Reconfigurableringoscillatorstructure 43
2.5.3 Measuredresults 48
2.5.4 Poly-pitcheffect 49
2.5.5 Lengthofdiffusioneffect 51
2.5.6 Delayvariationduetolayoutorientation 52
vi Nano-CMOSandpost-CMOSelectronics:circuitsanddesign
2.5.7 Delayvariationduetosupplyvoltage 52
2.5.8 Measuredaccuracyofthedelaymeasurement 53
2.5.9 Comparisonwithotherworks 55
2.6 MeasurementofriseandfalldelaysusingstandardRO 56
2.7 RiseandfallgatedelaymeasurementusingRRO 57
2.7.1 Gatedelaymeasurementcell 57
2.7.2 Riseandfalldelaysofnon-invertinggate 58
2.7.3 Riseandfalldelaysofinvertinggate 60
2.8 Testchipandmeasurementresults 61
2.8.1 Measurementofdutycycle 61
2.9 Measuredresults 62
2.9.1 Impactofbody-bias 63
2.9.2 Impactofsupplyvoltage 65
2.9.3 Measurementaccuracy 65
2.9.4 Comparisonwiththeexistingtechniques 65
2.10Summaryandconclusions 66
References 67
3 NanoscaleFinFETdevicesforPVT-awareSRAM 71
3.1 Introduction 71
3.2 NanoscaleFinFETdevices 72
3.2.1 BulkFinFET 73
3.2.2 SOIFinFET 75
3.3 FinFET-basedSRAMtopologies 79
3.3.1 IG-FinFET-based6TSRAM 80
3.3.2 Back-gatebiasIG-FinFET-based6TSRAM 82
3.3.3 IG-FinFET-basedPPN10TSRAM 83
3.3.4 Stabilityanalysis 88
3.4 FinFET-basedSRAMdesignchallenges 91
3.5 PVT-awareSRAMdesign 92
3.5.1 PVTmitigationtechniques 93
3.5.2 PVT-awareSRAMdesigns 95
3.5.3 Stabilityanalysis 103
3.6 Conclusion 106
References 106
4 Datastabilityandwriteabilityenhancementtechniques
forFinFETSRAMcircuits 113
4.1 Introduction 113
4.2 Six-FinFETSRAMcells 114
4.2.1 Conventionalsix-FinFETSRAMcell 114
4.2.2 Independent-gateFinFETSRAMcell 116
4.2.3 SRAMcellwithasymmetricallyoverlap/underlap
engineeredFinFETs 117
Contents vii
4.2.4 HybridSRAMcellwithasymmetricallyoverlapped/
underlappedbitlineaccesstransistors 120
4.2.5 SRAMcellwithasymmetricallygate-underlapped
transistors 121
4.2.6 Single-endedreadSRAMcellwithunderlap
engineeredsymmetrical-FinFETs 125
4.3 FabricationandSRAMcellareacomparison 127
4.4 Casestudy:8KBitmemoryarraysdesignedwithdifferent
SRAMcells 128
4.4.1 Readstaticnoisemargin 128
4.4.2 Holdstaticnoisemargin 129
4.4.3 Writevoltagemargin 130
4.4.4 Dataaccessspeed 131
4.4.5 Leakagepowerconsumption 132
4.5 Variationsofunderlap(overlap)lengthsduetoprocess
imperfections 133
4.6 Conclusions 138
References 138
5 Low-leakagetechniquesfornanoscaleCMOScircuits 141
5.1 Introduction 141
5.2 Devicescaling 142
5.2.1 Constantvoltagescaling 144
5.2.2 Constantfieldscaling 144
5.2.3 Generalizedscaling 145
5.3 Powerdissipation 145
5.3.1 Leakagepowerdissipation 145
5.3.2 Leakagecurrentcomponents 146
5.4 Issueofleakagecurrent 148
5.5 Variabilityissuesandawaredesign 148
5.6 Leakagereductiontechniques 150
5.6.1 MTCMOStechnique 150
5.6.2 Forcedstacktechnique 152
5.6.3 DualthresholdCMOS(DTCMOS)technique 154
5.6.4 SCCMOS(supercut-offCMOS)technique 154
5.6.5 Leakagefeedbacktechnique 156
5.6.6 VariablethresholdCMOS(VTCMOS)technique 157
5.6.7 LECTORtechnique 158
5.6.8 Sleepystacktechnique 158
5.6.9 Sleepykeepertechnique 159
5.6.10VCLEARITtechnique 160
5.6.11GALEORtechnique 161
5.7 Leakageanalysis 162
5.8 Conclusion 167
References 167
viii Nano-CMOSandpost-CMOSelectronics:circuitsanddesign
6 ThermaleffectsincarbonnanotubeVLSIinterconnects 173
6.1 Introduction 173
6.2 PresentstatusofVLSIinterconnect 174
6.3 SurveyofCNT-basedinterconnects 175
6.4 Electricalproperties 176
6.4.1 Equivalentresistance(R ) 177
eqv
6.4.2 Equivalentinductance(L ) 180
eqv
6.4.3 Equivalentcapacitance(C ) 181
eqv
6.4.4 Effectivemeanfreepath(λ ) 182
eff
6.4.5 Equivalentcircuit 184
6.5 Thermalproperties 185
6.5.1 ThermalpropertiesofSWCNTs 185
6.5.2 ThermalpropertiesofSWCNTbundle 187
6.5.3 ThermalpropertiesofMWCNT 189
6.5.4 IterativeschemeforRandT 190
6.5.5 Temperatureprofilinginsidetheinterconnect 191
6.5.6 PerformancesintermsofS-parameters 193
6.6 Conclusion 196
References 196
7 Lumpedelectro-thermalmodelingandanalysisofcarbon
nanotubeinterconnects 201
7.1 Introduction 201
7.2 ElectricalmodelingofCNTs 202
7.3 ThermalmodelingforCNTs 205
7.4 Conclusion 216
References 217
8 High-levelsynthesisofdigitalintegratedcircuits
inthenanoscalemobileelectronicsera 219
8.1 Introduction 219
8.2 Fundamentalsonhighlevelsynthesis 222
8.2.1 OverviewonHLSdesignprocess 222
8.2.2 NeedforHLS 224
8.2.3 Schedulingalgorithms 225
8.2.4 Allocationandbinding 228
8.3 Power,energy,orleakageawareHLSfornanoscaleICs 229
8.3.1 Selectedpower,energy,orleakageawareHLSmethods 229
8.3.2 Effectsofloopmanipulationonpoweranddelay
ofthedesign 233
8.3.3 OtherdesignspaceexplorationapproachesduringHLS 239
8.4 Bio/nature-inspiredalgorithmsforDSEframework 241
8.4.1 Selectedbio/nature-inspiredapproaches 241
8.4.2 ABFOA-explorationprocess 243
8.4.3 Encoding/initializationofthedatapathbacterium 244
Contents ix
8.4.4 Encodingoftheauxiliarybacterium 245
8.4.5 Proposedmovementofbacterium 246
8.4.6 Modelsformetric 248
8.4.7 ResultsoftheBFOA-explorationprocess 248
8.5 HLSapproachesforsecureinformationprocessing 252
8.5.1 Relatedwork 252
8.5.2 Exploration process of hardwareTrojan secured datapath:
securityagainstuntrustedthirdpartydigitalIPs 253
8.5.3 ResultsofexplorationprocessofhardwareTrojan
secureddatapath 258
8.6 SelectedtoolsavailableforHLS 258
8.6.1 SelectedcommercialtoolsforHLS 259
8.6.2 SelectedfreeHLStools 260
8.7 ConclusionandfuturedirectionsofHLS 260
References 261
9 SPICElessRTLdesignoptimizationofnanoelectronic
digitalintegratedcircuits 267
9.1 Introduction 267
9.2 TheconceptofSPICElessRTLoptimizationduringHLS 271
9.3 TheissuesinRTLoptimizationofpowerdissipation
indigitalcircuits 272
9.4 PoweroptimizationatRTL:state-of-the-art 274
9.4.1 ExistingmethodsforRTLpoweroptimization 274
9.4.2 Multipleoxidethicknesstechnologyforgate-oxide
leakageoptimization 276
9.5 AspecificSPICElessRTLoptimizationapproach 278
9.5.1 TheoverallRTLoptimizationflow 278
9.5.2 ObjectivefunctionforRTLoptimization 279
9.5.3 AspecificheuristicalgorithmforRTLoptimization 281
9.6 SPICElesscharacterizationoftheRTLcomponentlibrary 285
9.6.1 Gate-oxideleakagemodeling 287
9.6.2 Propagationdelaymodeling 289
9.6.3 AnalyticalmodelingofRTLcomponents 291
9.7 ExperimentalresultsforthespecificRTLoptimization 293
9.8 Conclusionsandfuturedirectionsofresearch 298
Acknowledgments 299
References 299
10 Greenon-chipinductorsforthree-dimensionalintegrated
circuits:concepts,algorithmsandapplications 305
10.1 Introduction 305
10.2 Effectofvariousparametersofanon-chipinductor 307
10.2.1 Impactofprocessparameters 309
10.2.2 Designparameters 313