Multi-Chip Module Test Strategies

160 Pages·1997·9.464 MB·English

by  Yervant Zorian, V. D. Agrawal (auth.), Yervant Zorian (eds.)

MULTI-CHIP MODULE TEST
STRATEGIES
edited by
Yervant Zorian
Logic Vision, Inc.
Reprinted from
a Special Issue of
JOURNAL OF ELECTRONIC TESTING
Theory and Applications
VoI. 10, Nos. 1 & 2
April1997
~.
"
SPRINGER-SCIENCE+BUSINESS MEDIA, LLC
FRONTIERS IN ELECTRONIC TESTING
Consulting Editor
Vishwani D. Agrawal
Books in the series:
Testing and Testable Design of High-Density Random-Access Memories
P. Mazumder, K. Chakraborty
ISBN: 0-7923-9782-7
From Contamination to Defects, Faults and Yield Loss
J.B. Kbare, W. Maly
ISBN: 0-7923-9714-2
Efficient Branch and Bound Search with Applications to Computer-Aided
Design
X.Chen, M.L. Bushnell
ISBN: 0-7923-9673-1
Testability Concepts for Digital ICs: The Macro Test Approach
F.P.M. Beenker, R.G. Bennetts, A.P. Thijssen
ISBN: 0-7923-9658-8
Economics of Electronic Design, Manufacture and Test
M. Abadir, A.P. Ambler
ISBN: 0-7923-9471-2
IDDQ Testing of VLSI Circuits
R. Gulati, C. Hawkins
ISBN: 0-7923-9315-5
MULTI-CHIP MODULE TEST STRATEGIES
A Special Issue of lournal of Electronic Testing
Vol. 10, Nos. 1 & 2, February/April 1997
Foreword. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. V.D. Agrawal 5
Preface .......................................................................................... Y. Zorian 6
Introduction
Fundamentals ofMCM Testing and Design-for-Testability ....................................... Y. Zorian 7
Die Level Testing
Known Good Die .................................................................................. L. Gitg 15
Substrate Testing
A Survey of Test Techniques for MCM Substrates ............ M. Swaminathan, B. Kim and A. Chatterjee 27
Smart Substrate MCMs .......................................................... A. Gattiker and W Maly 39
Electron Beam Probing-A Solution for MCM Test and Failure Analysis ................................ .
· ............................................. R. Schmid, R. Schmitt, M. Brunner, O. Gessner and M. Sturm 55
Module Level Test
MCM Test Strategy Synthesis from Chip Test and Board Test Approaches ........................ A. Flint 65
Designing "Dual Personality" IEEE 1149.1 Compliant Multi-Chip Modules .................... N. larwala 77
An Effective Multi-Chip BIST Scheme ........................................... Y. Zorian and H. Bederr 87
MCM Test Applications
Design-for-Test in a Multiple Substrate Multichip Module ................ 1.A. lorgenson and R.I. Wagner 97
A Test Methodology for High Performance. MCMs .......................... T.M. Storey and B. McWilliam 109
Module Level Diagnosis
A Formalization of the IEEE 1149.1-1990 Diagnostic Methodology as Applied to Multichip Modules .....
· ................................................................................................. K. Posse 119
Multichip Module Diagnosis by Product-Code Signatures ................................................ .
· ........................................................... P. Nagvajara, I. Lin, P. Nitagupta and C. Wang 127
Simulation Techniques for MCMs
Simulation Techniques for the Manufacturing Test of MCMs ..................... M. Tegethoff and T. Chen 137
MCM Test Economics
Economic Analysis of Test Process Flows for Multichip Modules Using Known Good Die ............... .
" .. , ....................... ,. . ,.,.,., ..... ,., ................ c.F. Murphy, M.S. Abadir and P.A. Sandborn 151
Index ............................ , . , ..... , , , . , , .. , .. , , . , ......................... , .................. , .... , 167
ISBN 978-1-4613-7798-6 ISBN 978-1-4615-6107-1 (eBook)
DOI 10.1007/978-1-4615-6107-1
Library of Congress Cataloging-in-Publication Data
A C.I.P. Catalogue record for this book is available
from the Library of Congress.
Copyright © 1997 by Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers in 1997
Softcover reprint of the hardcover 1s t edition 1997
AlI rights reserved. No part of this publication may be reproduced, stored in
a retrieval system or transmitted in any form or by any means, mechanical,
photo-copying, recording, or otherwise, without the prior written permission of
the publisher, Springer-Science+Business Media, LLC.
Printed on acid-free pap er.
JOURNAL OF ELECTRONIC TESTING: Theory and Applications 10, 5 (1997)
© 1997 K1uwer Academic Publishers. Manufactured in The Netherlands.
Foreword
Electronic systems contain components (transistors, resistors, capacitors, etc.) and interconnections. Very large
systems are possible through the use of hierarchy of interconnections. This is the same principle used in telephone
systems and in road networks. For electronic systems, local interconnects are included in VLSl chips, while larger
ones are placed on printed circuit boards (PCBs). The PCB technology, now considered quite mature, has advantages
in testing. Special methods and equipment, like those developed for in-circuit test (lCT), can efficiently diagnose
a faulty PCB.
However, we are all too aware ofthe limitations of PCBs. They are bulky and slow. The manufacture of PCBs and
VLSl chips requires altogether different materials and processes. Of these the VLSl process is more advanced. Our
desire to have a VLSl alternative for the PCB has produced the multi-chip module (MCM). These are multi-level
interconnect Silicon wafers or ceramic substrates on which VLSl chips are directly bonded. This appears to be the
way electronic systems will be built in the future.
MCM test needs new methods. lCT is not useful here. Special chip to wafer bondings require new test methods.
So do high-density interconnects that must be tested for connectivity as well as for delay. Complications arise when
a faulty chip, already bonded on the wafer, is to be diagnosed.
This volume, edited by Yervant Zorian, contains selected articles on various aspects ofMCM testing. Very recent
and advanced work is included in original writing of the contributors. The purpose is two-fold. Readers designing
and building MCMs will be able to learn the current practices. And, researchers will find numerous test challenges
this new technology poses.
Beside being an original contributor, Zorian has been personally involved in promoting this new field. I thank
him for his diligent and tireless work is selecting, reviewing and assembling this volume.
Vishwani D. Agrawal
Consulting Editor, Frontiers in Electronic Testing Series
[email protected]
JOURNAL OF ELECTRONIC TESTING: Theory and Applications 10,6 (1997)
© 1997 Kluwer Academic Publishers. Manufactured in The Netherlands.
Preface
MCMs today consist of complex and dense VLSI devices mounted into packages that allow little physical access
to internal nodes. The complexity and cost associated with their test and diagnosis are major obstacles to their
use. This volume presents state-of-the-art test strategies for MCMs. It is meant to satisfy the needs of engineers
interested in practical implementations of MCM test solutions, researchers seeking new domains to expand their
knowledge, and designers looking for leading edge test and design-for-testability solutions for their next designs.
This volume comprises eight sections. It is designed to provide a comprehensive and well balanced coverage
of the MCM test domain. It establishes the necessary background on MCMs and MCM testing in Section 1 that
glues all the sections together. Then it places particular emphasis on three major levels of manufacturing test and
their corresponding Design-for-Testability techniques, namely, the bare dice level in Section 2, the substrate level
in Section 3, and the assembled module level in Section 4. The applications of such techniques are illustrated in
two case studies documented in Section 5. Section 6 addresses the key issue of diagnosing MCMs at the assembly
level. Section 7 discusses various simulation techniques for MCMs. Finally, Section 8 compares the trade-offs
related to diverse test solutions for MCMs and their economic impact on MCM fabrication.
I would like to take this opportunity to thank all the authors and referees for their contributions in creating this
very special volume. I would also like to express my gratitude for the continuous support and guidance provided
by Vishwani Agrawal. I hope this volume will satisfy your interest and provide you the MCM test knowledge that
you seek.
Yervant Zorian
Editor
[email protected]
JOURNAL OF ELECTRONIC TEStING: Theory and Applications 10,7-14 (1997)
© 1997 Kluwer Academic Publishers. Manufactured in The Netherlands.
Fundamentals of MCM Testing and Design-for-Testability
YERVA NT ZORIAN
LogicVision, 31B Chicopee Dr., Princeton, NJ 08540, USA
zorian@\vision.com
Received February 10, 1995; Revised October 5, 1996
Editor: V.D. Agrawal
Abstract. Products motivated by performance-driven and/or density-driven goals often use Multi-Chip Module
(MCM) technology, even though it still faces several challenging problems that need to be resolved before it becomes
a widely adopted technology. Among its most challenging problems is achieving acceptable MCM assembly yields
while meeting quality requirements. This problem can be significantly reduced by adopting adequate MCM test
strategies: to guarantee the quality of incoming bare (unpackaged) dies prior to module assembly; to ensure the
structural integrity and performance of assembled modules; and to help isolate the defective parts and apply the
repair process.
This paper describes today's MCM test problems and presents the corresponding test and design-for-testability
(DFT) strategies used for bare dies, substrates, and assembled MCMs.
Keywords: MCM testing, known good dies, design-for-testability
1. Introduction performing the same function. Examples of such ad
vantages are the use of multivendor components, to
Today's need for denser packaging technologies is mix different process technologies (bipolar, GaAs and
mainly driven by products requiring smaller phys CMOS, digital and analog, etc.), and to reduce the over
ical sizes and/or higher performances. The MCM all development cost and time.
technology is a key solution to meet such miniatur For the most part, today's MCM technology has
ization and performance requirements. Contrary to not yet settled into a set of standard materials and
the conventional packaging technology (i.e., boards techniques the way printed circuit board and surface
populated with packaged chips), an MCM typically mount technologies have. For instance, MCMs today
consists of a single package containing multiple bare use diverse types of chip-to-substrate attachment tech
dies (unpackaged chips) and/or discrete components. niques, such as wire bond, Tape Automated Bonding
The dies and components are built with different con (TAB), and flip-chip Mess]. Also to achieve high
figurations/sizes and connected to a· single dedicated density module-level interconnects, different substrate
substrate. In military equipment and advanced con types are used [2]. Examples of such substrate types
sumer products, MCMs are primarily used to come are: co-fired ceramic (MCM-C), which basically is a
up with small size products; whereas, telecommuni hybrid circuit technology with thick film screen print
cation equipment and high speed computers are typ ing; laminates (MCM-L), which is an advanced form
ically performance-driven applications, and often re of printed circuit board technology and is used for mid
quire MCMs to achieve very high speed operations [1]. range performance and low cost needs; and deposited
In addition to the size and performance gains, MCMs thin-film over silicon or metal base (MCM-D), which
offer other advantages if compared to single die devices is similar to integrated circuit technology. This is used
8 Zorian
Fig. 1. An example MCM containing four bare dies.
for high performance and density requirements, but is The above list clearly indicates the need for ade
associated with high cost [3]. Moreover for substrate quate solutions for MCM testability, repairability, and
to-board attachments multiple solutions are in use some electrical modeling.
based on peripheral input/outputs, and others based on This paper is organized as follows: Section 2 dis
surface input/outputs, such as Ball Grid Array and Land cusses the MCM test and diagnosis problems. Sec
Grid Array technologies [2]. Figure I shows an exam tion 3 describes the issues of testing unpackaged chips.
ple MCM consisting of four bare dies attached via wire Section 4 concentrates on substrate testing techniques.
bonding (chip-to-substrate attachment) to an MCM-C Section 5 analyzes module testing and illustrates DFT
substrate with peripheral input/outputs. based approaches. Finally, Section 6 summarizes the
Even though there is hardly any standardization in paper and provides some concluding remarks.
the MCM technology, and the MCM manufacturers
often use proprietary techniques, the current issues with 2. MCM Test and Diagnosis Problems
MCM technology are common among most existing
manufacturers [3]. Some of the important common The above issues of bare die quality, low assembly
ones are [4]: yield, and defective component identification are, in
fact, test and diagnosis problems. They are caused by
- the unsatisfiable quality of unpackaged chips (bare the limitations of conventional techniques used in chip
dies) and board testing [5, 6].
- the unavailability of their simulation models, For instance, the conventional test of unpackaged
-the low yield ofMCM assembly chips as performed by most IC suppliers today, consists
- the high cost of MCM manufacturing of a simple parametric test and a low speed functional
- the complexity of the rework process test at the wafer level to verify if a chip is alive. Such
a test is typically below the quality level required for
by which defective components can be diagnosed and bare dies because it does not contain the performance
replaced. and reliability tests.
Fundamentals of MCM Testing and Design-for-Testability 9
In general, if a bare die is found defecHve after its
assembly onto the MCM substrate, either the MCM
is repaired by removing the bad chip and replacing it
with a presumably good one, or the whole substrate is
scrapped with the rest of the chips. Both alternatives
are often expensive and undesirable. Hence, test strate
gies, that result in providing bare dies with high quality
prior to mounting them onto the MCM substrates are
Die
necessary. The use of known good die techniques [16],
structured testability approaches [4] or other options
[7, 8, 9], as summarized in Section 3, can be very ef
fective to help provide bad die detection before MCM
assembly. ~
l
Another problem appears during the test of assem
bled MCMs, if conventional board testing is used for
MCMs. Here the in-circuit testing (i.e., bed-of-nails)
faces two major obstacles. One is the difficulty of ac Module
cessing internal nodes in an MCM, due to high chip !
density and small interconnections [2, 3]. The other is
i
due to the speed limitations of automatic test equipment
,
I
used for boards. Hence, it is difficult to diagnose and
I
to apply performance test at the MCM level. Certain •
structured testability solutions discussed in Section 5
and described in [5, 10] and [11] help overcome these
problems. Fig. 2. MCM production flow.
Yet another issue is the ability to diagnose failed dies
or substrates at the module level [12]. The MCM man 3. Wafer and Bare Die Test
ufacturing process requires isolating the defective com
ponents. Hence, the module level test approach needs Conventionally, chip-level testing is done by chip man
to provide diagnostic capabilities during the MCM re ufacturers in two stages. First, at wafer level, they typi
pair process. Papers such as [12, 13] discuss test cally perform a wafer sort on the unpackaged chips [6].
approaches that can help resolve the limitations of con This consists of running a structural integrity test (func
ventional testing of boards. And papers such as [14] tional test) using functional or ATPG vectors at low
and [15] illustrate case studies. speed and an input/output parametric test. The second
The MCM production flow can be divided into four stage takes place after the chip is packaged [6,7]. This
major non-overlapping processes, as shown in Fig. 2. consists of a comprehensive performance and reliabil
They are: the process of fabricating the wafer, the pro ity test. In MCMs, since bare dies are attached directly
duction of individual bare dies; the fabrication of sub to a substrate, therefore the complete set of tests, as in
strates; and the assembly of bare dies and substrates the above two stages, need to be performed on unpack
to compose MCMs. Testing takes place during each aged chips. Such completely tested unpackaged chips
one of these four processes. The test related activities are called "Known Good Dies" [16]. Hence, a known
are represented by shaded boxes in Fig. 2. They can good die is a die fully functional over specifications and
be divided into four sets of activities that correspond a temperature range [16]. This means that, the test per
to the MCM production processes. They are: wafer formed on bare dies has to include the performance and
test, bare die test, substrate test and assembled mod reliability tests, which are conventionally done during
ule test and rework. Each of these test processes faces the second stage (i.e., at the packaged chip level) [16].
certain challenges and requires the adoption of specific As indicated, the low speed structural integrity
strategies to meet the MCM quality requirements and and input/output parametric tests for bare dies are
improve its yield. performed at the wafer level test. The input/output
10 Zorian
parametric test verifies that finished dies meet in On the other hand, the dies designed for TAB at
put/output voltage and leakage specifications. The use tachment can be tested for performance, after inner
of regular wafer probes for this test has been a standard lead bonding, by conventional test techniques before
procedure [16]. entering the assembly process. Hence, the defective
The structural integrity test for packaged chips pro TAB dies can be removed or repaired prior to assem
vides a stuck-at fault coverage usually in the range of bly. This maximizes MCM test yields. However, TAB
90%. Even though, it is desirable to raise this coverage devices have poor repairability, and are very expen
for packaged chips in order to improve the yield of IC sive; they may only be justified in volume operations
production, but improving fault coverage is far more [4]. Devices that are designed for TAB and wire-bond
important for bare dies. This is because, the MCM attachment are generally more difficult to replace than
yield is a composite function of the individual yields flip-chip devices.
of the bare dies it contains [14]. Hence, in order to meet However, because of its maximum interconnect den
the final MCM yield requirements a die fault coverage sity, minimum requirements for substrate real estate,
would probably need to be above 99+% [2, 3]. This can maximum performance, heat dissipation capability,
hardly be obtained for today's complex chips if a struc and repairability flip-chip dies would seem to be the
tured testability technique such as scan or BIST is not ideal choice. The major drawback of flip-chip is the
used during the design cycle of a chip [17]. If the chip difficulty of applying performance testing [10].
will be packaged in an MCM, this will be one of the ma Chip-level reliability test using burn-in is another
jor changes over the conventional chip design process. major reason to use carriers.
A performance test is needed to detect delay type Burn-in is required for chips to be detected if they
faults which are not manifested during the conven have infant mortality. Burn-in is usually done on pack
tionallow speed wafer level test. Bare dies often need aged dies, and can also be performed on TAB dies.
to be tested for such faults prior to MCM assembly. For dies designed with other types of attachments, in
If an MCM application is density-driven rather than order to guarantee bare die reliability, chip suppliers
performance-driven, performance testing of dies may will need further development in burn-in techniques
not be as crucial. But for performance-driven applica [19]. Several experimental approaches based on tem
tions, at-speed testing of dies is necessary. Even though porary die packaging have been reported, e.g., [8, 16,
technically it is possible to achieve full high speed test 20]. Some of these approaches still tend to be on the
with the existing wafer probes, but this is a very expen expensive side [16].
sive task [18]. A different approach to this problem In summary, the wafer testing for MCM bare dies
is packaging samples from each wafer lot and testing face three major difficulties: the first is the expected
the samples for performance, based on the fact that known good die quality which necessitates test vec
an individual wafer has a maximum spread of only a tor sets with very high fault coverages; the second is
few percent [6]. However, this approach does not have the speed limitations of existing wafer probes, hence
a good precision, and cannot be adopted for critical the problem with performance testing; and the third
MCM applications in terms of performance. Another is the problem of burn-in associated with the required
solution would be to mount the bare die in a (sacrifi reliability testing.
cial or permanent) carrier and apply the performance
test on it. A number of carrier based solutions have
been proposed recently [8, 16, 19]. Yet another solu 4. Substrate Testing
tion would be to invoke a built-in at-speed test in the
bare die. This requires a minimal improvement in the It is important to test the substrates for electrical in
high speed capabilities of existing tester probes. Such tegrity prior to attaching the dies. A substrate defect
a built-in at-speed testing solution is discussed in [10]. hurts MCM yield as much as, or more than, poor yield
The complexity of bare die testing differs from one ing die [6]. Substrate repair is often not possible and
attachment method to the other. The flip-chip attach, components are sometimes damaged during the re
where the die bond pads are distributed all over the moval process. Hence, failure to detect a substrate
active area of the die, and the wire-bonded dies can defect can be extremely expensive.
not be effectively tested at-speed by conventional test Typically, substrate testing failure types include
techniques until the assembly [4]. opens and shorts. Substrate testing is done either by