Mohsin Suharwerdi 2018 PHAECE 005 19012022

2.9 MB·English

by  MOhsin SUharwerdi

NATIONAL INSTITUTE OF TECHNOLOGY
HAZRATBAL 190006, J&K
PhD JRF-SRF Report
On
By
Mohsin Suharwerdi
2018PHAECE005 (Ph.D.)
Under the supervision of
Dr Gausia Qazi
Associate Professor
Department of Electronics & Communication Engineering
Autumn, 2022
TABLE OF CONTENTS

1 INTRODUCTION ..................................................................................................... 1
1.1 Image Sensors and Imaging ................................................................................ 1
1.2 CMOS Image Sensors (A TCAD perspective) ................................................... 1
2 FIGURES OF MERIT ............................................................................................... 5
2.1 Quantum Efficiency ............................................................................................ 5
2.2 Dynamic Range................................................................................................... 5
2.3 Signal to Noise Ratio .......................................................................................... 6
2.4 Dark Current ....................................................................................................... 6
3 DARK CURRENT MODEL...................................................................................... 7
3.1 Depletion Area Generation ................................................................................. 8
3.2 Field-Free Area Generation ................................................................................ 8
3.3 Transfer Gate Oxide Interface Generation .......................................................... 8
3.4 TCAD Validation of the Dark current Sources .................................................. 9
4 RESEARCH OBJECTIVES AND PROGRESS ..................................................... 13
4.1 Objective 1 ........................................................................................................ 13
4.2 Objective 2 ........................................................................................................ 13
4.3 Objective 3 (yet to be accomplished) ............................................................... 15
5 REFERENCES ......................................................................................................... 19
LIST OF FIGURES

.............................................. 2
Figure 2 (a) Layout of a typical image sensor, (b) Front-end electrical structure of the device.
............................................................................................................................................... 2
Figure 3 (a) Front-end structure used in the electrical simulation, (b) Back-end structure
used in the optical simulation. ............................................................................................... 3
Figure 4 Mixed-Mode CIS simulation with Read-out Spice Models (BSIM3 Level 8,
Vth=0.63V). .......................................................................................................................... 4
Figure 5 (a) Absolute Power flux density (Wm-2) (b) Optical generation of the device in EM
wave solver (cm-3s-1). ............................................................................................................ 4
Figure 6 Various image sensor figure of merits affecting the quality of an image (photo
courtesy-NIT, Srinagar) ........................................................................................................ 5
Figure 7 Trap assisted generation process (Donor and Acceptor types) ............................... 7
Figure 8 Various Dark current sources in a CIS PPD. .......................................................... 7
Figure 9 Arrhenius curve for the sensor with activation energy close to 0.56ev .................. 9
Figure 10 PPD Capacitance vs photogenerated electrons Two Regimes clearly visible . 10
Figure 11 Modeled PPD Capacitance: (a) Depletion (fits low illumination) (b) Diffusion
(fits high illumination). ....................................................................................................... 11
Figure 12 PPD Capacitance Analytical fit with change in Temperature ............................ 11
Figure 13 PPD Capacitance Analytical fit with change in (a) Trap Concentration (b) Trap
Cross-Section. ..................................................................................................................... 12
Figure 14 Remodeling of CMOS image sensor compact model to capture the dark current
generation effects. (a) Updated physics-based model, (b) Physical device (image sensor
pixel). .................................................................................................................................. 12
Figure 15 3D visualization of surface potential: (a) TG=On (b) TG=Off. ......................... 13
Figure 16 The PPD extension & Depletion limits under the TG (Dimensions in µm). ...... 14
Figure 17 Streamlines driven by the gradient of eQF (a) VOTG=0V (b) VOTG=1V. ............ 14
Figure 18 Dark current evolution & FWC reduction with TG voltage (VOTG). .................. 15
Figure 19 TCAD 2-D distributions of the doping concentration showing the simulated
device (a) with an enlargement of the TG gate over the PPD and (b) with an additional large
gate over the PPD [19]. ....................................................................................................... 16
Figure 20 TCAD simulation of the dark current before and after irradiation for various
designs [19]. ........................................................................................................................ 16
Figure 21 (a) and (b) Sketches of the top-view layouts and of the related cross sections of
four 4T-pixel blocks with STI, respectively, and (c) and (d) hybrid isolation [20]. ........... 17
Figure 22 DC distributions as measured on one representative sample for each test array
(186×84 pixels) of the STI-pixel and hybrid-isolation-pixel [20]. ..................................... 17
Figure 23 (a) Illustration of the plasma induced degradation mechanism (b) Minimum of the
interface states density DIT [18]. .......................................................................................... 18
1 INTRODUCTION

1.1 Image Sensors and Imaging

Cameras find applications in consumer devices like Digital cameras, Cell phones; in
scientific research like Infrared, UV, X-ray imaging; and in industrial products like
automobiles, security systems. The solid-state image sensor, which is the heart of the
camera, has evolved greatly since its invention in the 1970s. Although the two variants of
image sensors, viz. CCD (Charge Coupled Device) and CMOS (Complementary Metal
Oxide Semiconductor) were intro
applications far overweigh those of the former. The reason being the architectural
differences in signal read-out principle.
A CCD transfers the signal charge to the end of the output signal line as it is and
converts it into a voltage signal through an amplifier. In contrast, a CMOS image sensor
(CIS) converts the signal charge into a voltage signal at each pixel. This leads to Low power
consumption in the CMOS image sensors. In high-speed operation, the in-pixel
amplification configuration gives better gain-bandwidth than a configuration with one
amplifier on a chip. Although the recent development of CMOS image sensors requires
dedicated fabrication process technologies, CMOS image sensors are still based on standard
mixed signal processes unlike CCD sensors.
On the downside, in CCD image sensors, the signal charge is transferred
simultaneously, which gives low noise compared to its competitor. In CMOS sensors, this
issue is solved by the in-pixel amplification (active pixel) and other noise reduction
techniques discussed in the figure of merits section 2. The delayed read-out of different row
pixels -
by-row read-out of the pixel values. This issue is solved by the use of four-transistor
configuration with a transfer gate. Also due to additional transistors, the size of a CMOS
pixel is larger than a CCD pixel. Although CMOS fabrication technology advances have
benefited the development of CMOS image sensors, namely in shrinking the pixel size, yet
the size of a CCD is smaller than the 4T-APS (four-transistor Active Pixel CMOS Sensor).

1.2 CMOS Image Sensors (A TCAD perspective)

Passive pixel sensor (PPS) was the first commercially available MOS sensor [1], but
due to SNR issues, its development was halted. An APS was first realized using a photogate
(PG) as a photodetector and then by using a photodiode (PD) [1]. The sensitivity of a PG is
not good since polysilicon as a gate material is opaque at the visible wavelength region. A
three-transistor Active pixel sensor (3T-APS) although overcame the disadvantage of the
PPS, but there is a tradeoff relation between the full-well capacity ( ) and the
conversion gain ( ). A four-transistor configuration (4T-APS) solves this issue
using a Floating diffusion capacitance (FD), which is independent of the PPD, and a readout
transistor TX between them. For color information, four pixels (two green, one blue and one
3], represents one coordinate point of an image (Figure
1).

1
Figure 1

1.2.1 Structure & Doping distribution of the PPD (4T)

The layout (with layers) and Front-end electrical structure of a typical pinned
photodiode used in CMOS image sensors is shown in (Figure 2). The main elements are an
n-type buried signal charge storage well (SW) region sandwiched between a lower p-type
layer and a p+pinning layer at the top surface in contact with the lower active layer, a
transfer gate (TG), and an n+output floating diffusion (FD). In a 180 nm process, the
p+pinning layer might be about 100 nm thick, the n-layer about 2,500-5,000 nm thick, and
the p-layer a few microns thick. The pnp PPD sandwich can be built using a p on p+epi
substrate, or implemented by p-well in an n on n+epi substrate [4].

Figure 2 (a) Layout of a typical image sensor, (b) Front-end electrical structure of the
device.

The Back-end structure used in the optical simulation is shown in (Figure 3) vis-à-
vis the Front-end layers. The major steps of the design flow are:

2
1. Substrate formation.
2. Shallow trench isolation.
3. Polysilicon gate formation.
4. Photodiode buried profile implantation.

5. Lightly doped drain (LDD) implantations.
6. Spacer creation.
7. Highly doped drain (HDD) implantation.
8. Rapid thermal annealing.

9. Electrical interconnects formation.
10. Planarization layer deposition

11. Color filters deposition.
12. Microlens formation.

Figure 3 (a) Front-end structure used in the electrical simulation, (b) Back-end
structure used in the optical simulation.

The doping distribution is built from secondary ion mass spectrometry (SIMS)
doping profiles [5]. For more accurate results, TCAD simulation in 2D, or for smaller pixels
(e.g., 2.2 um pitch or less), simulation in 3D is required since 2D and 3D effects become
important [4]. The planarization layer reduces the optical path between the active surface
and the color filter [6].

1.2.2 Opto-Electrical simulation

TCAD optoelectrical simulation of a front side, linearly polarized plane wave (650
nm wavelength: red region) excited 4-Transistor CMOS image sensor (Figure 4) is
considered (MOS dimensions from [7]). A harmonic plane wave with intensity 0.1 W/cm2
perpendicular to surface is used as a light source. The red filter absorbs light with a
wavelength below 620 nm. Figure 5 shows the absolute power flux density (Wm-2) Optical
generation (cm-3s-1) of the device in EM wave solver.
In readout operation, signal charges in the PPD are transferred to FD by applying
readout pulse to TG, and potential change of FD is detected by the Source Follower
3
Amplifier (SFA). One readout sequence involves (1) sensor part (PPD) (2) signal charge
quantity measuring part (FD), and (3) scanning part (SFA).

Figure 4 Mixed-Mode CIS simulation with Read-out Spice Models (BSIM3 Level 8,
Vth=0.63V).

Figure 5 (a) Absolute Power flux density (Wm-2) (b) Optical generation of the device
in EM wave solver (cm-3s-1).

As capacitance of FD can be designed without any change to PPD performance, it is
possible to realize a higher charge voltage conversion factor, which is inversely
proportional to C . This is advantageous for the later signal processing from the viewpoint
FD
of signal-to-noise ratio. But a too low capacitor volume may lead to charge spill-back to
PPD and thus an inefficient charge transfer.
From the I-V characteristics of the drive transistor and load device, the constant
current source as a load device has the largest output change for a fixed input voltage change
than the transistor followed by resistor load, but the area of the former is largest. Therefore,
transistor is used as load device in most cases. Although the voltage gain of SFA is less than
unity, the amount of charge is greatly multiplied by the ratio of output capacitance to input
capacitance (100-10,000) of the SFA. This is important to drive the later circuit and reduce
the impact of noise.
4
2 FIGURES OF MERIT

An image sensor involves many figures of merit that affect the quality of the image
it captures (Figure 6).

Figure 6 Various image sensor figure of merits affecting the quality of an image
(photo courtesy-NIT, Srinagar)

2.1 Quantum Efficiency

sensor is the ratio of electrons produced in the
photodiode ( to the number of photons absorbed in the depletion region , i.e.,
(where, ). So, if (wavelength of incident light) = 0.65µm,
(incident optical power) = 0.49nW/µm-2, is around 48,150 photons. An of around
12,275 e-s gives a quantum efficiency of 25.5%. Modern image sensors report a quantum
efficiency of more than 90%, thanks to the back-side illumination technique.

2.2 Dynamic Range

The Dynamic Range (DR) of a pixel is the ratio of maximum ( ) to minimum
( ) detectable signal value, i.e., . So, if = 30,000 e-s and
= 3 e-s, DR becomes 80dB. It directly depends on the full-well capacity (FWC) of the
pixel. FWC is the number of charges that a photodiode accumulates and FWC =
. For a Pinned Photodiode capacitance ( ) of 6 fF, pinning voltage
( , the maximum potential of the PPD) of 1.5V and Barrier potential ( , between the
PPD and sense node) of 0.7V, the FWC is almost 30,000 e-s. A common DSLR camera
image sensor has a DR and FWC of 80dB and 70,000 e-s respectively. Techniques like in-
pixel lateral over-flow capacitors increase the FWC and indirectly the DR.

5
2.3 Signal to Noise Ratio

Signal to Noise ratio (SNR) is the most important parameter for the sensitivity of an
image sensor. It is the ratio of the signal received by the photodiode (S in e-s) to the various
noises added to the signal readout of the sensor (N in e-s), i.e., SNR = S/N. The noises added
to the signal may either be temporal (varies in time or space domain) or fixed-pattern noise
(FPN). Correlated Double Sampling (CDS) circuitry in the column pitch of pixels can
effectively remove the FPN noise.
The remaining temporal noise further consists of shot noise (Poisson noise due to
particle nature of light and discrete charges), thermal dark current noise (doubles for every
6 degree C), flicker or 1/f noise dominant at low-frequency operation, read noise (due to
downstream pixel electronics) like random telegraph noise (RTN) due to scaling of
transistors and kTC noise due to reset transistor connected to the sense node. Lowering the
device temperature helps reduce the thermal dependent noise components. Most modern
cameras report a read noise below 4 e-s and a value of above 80 SNR per pixel.

2.4 Dark Current

In the absence of light, some charge generation takes place in the PPD and its
surrounding area. This charge generation, which leads to a dark current in the sensor, is
expedited by various process defects in the device bulk or surface and/or different impurities
at the material interfaces. Being a temporal noise, the dark current increases linearly with
the integration time of the irradiation.
As it is a thermal noise, cooling the device reduces the dark current drastically. Most
of the image sensors report a dark current of 1 to 2 e-s at the room temperature. Although
many modern techniques employed have brought the dark current to a very low value, but
still these techniques are insufficient to reduce generation at all interface regions. Dark
current still remains a big hurdle for the modern scaled and radiation exposed image sensors.

6
3 DARK CURRENT MODEL

In a field-free area, due to the thermal equilibrium, product of electron concentration
( ) and hole concentration ( ) is a constant ( ) ( is the intrinsic carrier concentration of
the semiconductor). Therefore, at low temperature (low energy), rate of generation and
recombination balance each other leading to a net zero carrier increase. On the other hand,
in a depletion region (e.g., reverse biased photodiode) due to a high electric field (ionized
impurities), the thermal equilibrium is disturbed leading to more rate of minority carrier
generation than recombination. Due to the high electric field, these generated charges
effectively drift and are collected in the potential well. At high temperature (high energy),
the dark carriers may also be generated in the field-free area, but due to the absence of an
electric field rarely diffuse to the potential well.
In case of various process defects in the device bulk or surface and/or different
impurities at the material interfaces, the dark current drastically increases. This is due to the
impurities with energy states between the valence and conductance band which act as steps
facilitating the transition of electrons between the valance and conductance bands (Figure
7).

Figure 7 Trap assisted generation process (Donor and Acceptor types)

In case of non-thermal equilibrium, the traps with energies E close to the intrinsic
t
Fermi level energy E of the semiconductor are the major contributors to the dark current
F
generation. Figure 8 shows different dark current sources in a CIS PPD. It is known that the
trap density increases at the surface and interfaces between different materials due to
impurities and process defects. Hence an important part of the dark current generation
occurs at the level of the PPD surface and the Si-SiO interface under the transfer gate and
2
at the level of interfaces with shallow trench channel (STI).

Figure 8 Various Dark current sources in a CIS PPD.
7