Modelling Methods for Testability Analysis of Analog Integrated Circuits Based on Pole-Zero Analysis

182 Pages·2004·1.2 MB·English

Modelling Methods for Testability Analysis of Analog
Integrated Circuits Based on Pole-Zero Analysis
Der Fakultät für Ingenieurwissenschaften der
Universität Duisburg-Essen
zur Erlangung des akademischen Grades eines
Doktor-Ingenieur
(Dr.-Ing.)
vorgelegte Dissertation
von
Hasan Albustani
aus
Hama/Syrien
Referent: Prof. Dr.-Ing. Axel Hunger
Korreferent: Prof. Dr-.Ing. Bernd Straube
Tag der mündlichen Prüfung: 06 August 2004
Abstract
Analog and mixed-signal circuits are gaining popularity in various applications such as tele-
communication,multimedia,biomedicalapplicationsandothers.Testingofthesecircuitshasa
major impact on product cost and time-to-market. Furthermore, the trend of integrating com-
plete analog/digital systems on a single chip has resulted in new testing challenges for such
systems.
Testability analysis for analog circuits provides valuable information for designers and test
engineers. Such information includes a number of testable and nontestable elements of a cir-
cuit, ambiguity groups, and nodes to be tested. This information is useful for solving the fault
diagnosis problem.
In order to verify the functionality of analog circuits, a large number of specifications have to
be checked. However, checking all circuit specifications can result in prohibitive testing times
onexpensiveautomatedtestequipment.Therefore,thetestengineerhastoselectafinitesubset
of specifications to be measured. This subset of specifications must result in reducing the test
time and guaranteeing that no faulty chips are shipped.
This research develops a novel methodology for testability analysis of linear analog circuits
basedonpole-zeroanalysisandonpole-zerosensitivityanalysis.Basedonthismethodology,a
newinterpretationofambiguitygroupsisprovidedrelyingonthecircuittheory.Thetestability
analysis methodology can be employed as a guideline for constructing fault diagnosis equa-
tions and for selecting the test nodes.
We have also proposed an algorithm for selecting specifications that need to be measured. The
elementtestabilityconceptwillbeintroduced.Thisconceptprovidesthedegreeofdifficultyin
testing circuit elements. The value of the element testability can easily be obtained using the
polesensitivities.Then,specificationswhichneedtobemeasuredcanbeselectedbasedonthis
concept. Consequently, the selected measurements can be utilized for reducing the test time
without sacrificing the fault coverage and maximizing the information for fault diagnosis.
Acknowledgments
I would like to take this opportunity to thank Prof. Dr.-Ing. B. Straube from Fraunhofer Insti-
tute Branch Lab Design Automation in Dresden for his support and patience. I would like also
tothankallmembersoftheTestandVerificationgroup,especially,Dr.-IngW.Vermeirnforhis
guidance and valuable advice throughout this research.
I would like to express my gratitude to Prof. Dr.-Ing. A. Hunger for his supervision.
Finally, I would like to thank my wife Maram and my son Adir for their encouragement and
support.
Table of Contents
Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. AnalogTestPhilosophy................................ 1
1.2. MotivationandProblemDefinition ...................... 3
1.3. Organization......................................... 5
Chapter 2 Circuit Modeling and Simulation . . . . . . . . . . . . . . . 7
2.1. Introduction.......................................... 7
2.2. CircuitModeling..................................... 7
2.3. SimulationTechniques ................................ 10
2.3.1. Event-DrivenSimulation.......................... 10
2.3.2. Time-ContinuousSimulation....................... 11
2.3.3. Mixed-ModeSimulation .......................... 11
2.4. CircuitSimulation .................................... 12
2.4.1. CircuitTopology................................ 12
2.4.2. CircuitEquationsFormulationandSolution.......... 14
2.4.3. AnalogCircuitAnalyses.......................... 16
2.4.3.1. DCAnalysis............................. 16
2.4.3.1. ACSmallSignalAnalysis.................. 17
2.4.3.1. TransientAnalysis........................ 18
2.4.3.1. SensitivityAnalysis ....................... 21
2.5. SymbolicModeling.................................... 23
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Chapter 3 An Introduction to Testing of Analog Circuits . . . . . . . 25
3.1. DifficultieswithTestingofAnalogCircuits................ 25
3.2. TestFlow........................................... 27
3.4. FaultClassification................................... 30
3.3. TestingTechniques................................... 31
3.2.1. Specification-DrivenTest......................... 31
3.2.2. Fault-DrivenTest............................... 33
3.5. AnalogTestIssues .................................... 34
3.5.1. AnalogFaultmodeling............................ 34
3.5.2. AnalogFaultSimulation.......................... 36
3.5.3. TestSignalGeneration........................... 37
3.5.4. DSP-BasedTesting .............................. 39
3.5.5. DesignforTestability(DfT)....................... 41
3.5.5.1. Reconfiguration-BasedDfT................. 41
3.5.5.2. Accessibility-BasedDfT.................... 41
3.5.6. Built-InSelf-Test(BIST).......................... 44
3.5.7. FaultDiagnosis................. ................ 46
3.5.8. TestabilityAnalysis.............................. 48
3.5.9. TestandMeasurementSelection.................... 52
Chapter 4 Testability Analysis for Analog Circuits . . . . . . . . . . . . 54
4.1. Introduction.......................................... 54
4.2. Methodology ........................................ 56
4.2.1. CircuitModeling................................. 57
4.2.1.1. ModifiedNodalAnalysis................... 57
4.2.1.2. State-VariableEquations................... 58
4.2.2. Pole-ZeroAnalysis............................... 60
4.2.3. Pole-ZeroSensitivity.............................. 64
4.2.4. TestabilityMeasure.............................. 67
4.2.5. AmbiguityGroupAnalysis ........................ 71
4.2.6. TestabilityAnalysisand Controllability/Observability.. 74
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4.3. SimulationExamples.................................. 75
4.3.1. The7-RCLadderCircuit.......................... 75
4.3.2. Continuous-Time State-Variable Filter . . . . . . . . . . . . 78
4.3.3. LeapfrogFilter................................... 83
4.3.4. The5-Pole(100Hz)Low-PassFilter................. 85
4.4. GeneralizationoftheTestabilityAnalysisAlgorithm........ 87
4.5. Summary... ....................................... 89
Chapter 5 Element Testability and Measurement Selection for
Second- Order Circuits . . . . . . . . . .. . . . . . . . . . . . . . . . . 91
5.1. Introduction.......................................... 91
5.2. TheAlgorithm........................................ 92
5.2.1 Mathematical Representation of Prototype
Second-Order Circuits........................... 93
5.2.5 Pole and Zero Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . 97
5.2.6 ElementTestabilityandMeasurementSelection....... 97
5.3. SimulationExamples.................................. 98
5.3.1 Continuous-TimeState-VariableFilter............... 98
5.3.2 Sallen-KeyBandpassFilter........................ 106
5.4. Summary............................................ 112
Chapter 6 Element Testability and Measurement Selection for
Higher-Order Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.1. Introduction.......................................... 113
6.2.TheAlgorithm........................................ 113
6.2.1. DominantPoles................................. 115
6.2.2. Model-OrderReduction.......................... 116
6.2.2.1. MomentGeneration...................... 116
6.2.2.2. MomentMatching........................ 118
6.2.3. PoleandZeroSensitivityCalculationinAWE......... 119
6.2.4. ElementTestabilityandMeasurementSelection....... 122
6.3. SimulationExamples.................................. 123
6.3.1. RLCCircuit.................................... 123
6.3.2. LeapfrogFilter.................................. 127
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6.4. Discussion........................................... 131
6.5. Summary............................................ 131
Chapter 7 Testability Analysis of Nonlinear Circuits . . . . . . . . . . . 132
7.1. Introduction..... .................................... 132
7.2. TestabilityAnalysisAlgorithm.......................... 133
7.2.1. CircuitLinearizationandDescription............... 134
7.2.2. PoleandZeroAnalysis.......................... 135
7.2.3. PoleandZeroSensitivity......................... 135
7.2.4. AmbiguityGroups............................... 136
7.2.5. Frequency-DomainSpecifications.................. 136
7.2.5.1. TheLow-FrequencyResponse............. 138
7.2.5.2. TheHigh-FrequencyResponse............. 141
7.2.6. ParameterTestabilityandMeasurementSelection .... 139
7.3. SimulationExamples.................................. 140
7.3.1. TheSimpleCommon-EmitterAmplifier............. 140
7.3.2. The CMOSDifferentialAmplifier................. 146
7.3.3. TheOperationAmplifierµA741................... 149
7.4. Summary........................................... 151
Chapter 8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
8.1. OriginalContributions. ............................... 154
8.2. RecommendationsforFutureResearch ................... 155
Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
A.1. AdjointMethodsforSensitivityComputation.............. 156
A.2. SensitivityComputationUsingSaberSimulator............ 158
A.3. SensitivityProperties.... ............................. 160
A.4. Sensitivities of Natural Response, Time-Domain and
Frequency-DomainSpecificationsfor Second-OrderCircuits 161
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
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Chapter 1
Introduction
1.1. Analog Test Philosophy
Testing of analog and mixed signal circuits has become a challenge and gained more interest
inthelastdecadeformanyreasonsincludingincreasingtheapplicationsoftheanalogcircuits,
integrating the whole system on one chip, and the high cost of analog testing compared with
digital testing counterpart.
Thereasonforincreasingtheanalogcircuitapplicationsisduetosignalsinrealworldareana-
log in nature with a continuous amplitude and time scale. Thus, any electronic system which
interacts with the outer world has to contain some analog interface circuitry. Many domains
such as telecommunications, multimedia, and biomedical applications require such analog
interface circuitry. Analog and mixed-signal circuits such as amplifiers, filters, switches, ana-
log-to-digital, and digital-to-analog converters are required in many end-equipment applica-
tionssuchascellulartelephones,hard-diskdrives,modems,motorcontrollers,andmultimedia
audio and video products. Moreover, the analog circuits provide a good overall performance
for high-performance applications (high frequency and low power applications), low-noise
data-acquisition systems (e.g. in biomedical sensor applications), and parallel analog signal
processing (such as in neural networks with a huge number of neurons). The strategy for test-
ing these analog and mixed signal circuits (interface circuitry) is still needed.
In the past, a chip was just a component of a system; today, a chip is a system in itself. This
integration of a system including analog and digital circuits in a chip (system-on-a-chip SoC)
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has posed non-trivial problems in design and test areas. There are many factors that cause the
complexity in testing the system-on-a-chip (SoC). Such factors are [Claa03]: the lack of ade-
quatefaultmodels,incapabletoolsforcopingwiththecomplexityoftheSoC,lackofaccessi-
bility (lack of controllability and observability), lack of an industrial standard analog design
for testability (DfT) methodology, and raising the importance of the timing-related faults.
Thetestcostofanalogandmixed-signalcircuitshasnowincreasedincomparisonwithdigital
testcostasshowninFigure1-1[Robe01].Thehighanalogtestcostresultsfrommanyfactors
such as expensive test equipment, long test development time, and long test production time.
The development and production test time costs constitute a part of the development and pro-
duction costs of the integrated circuits (ICs), respectively. Both the development and produc-
tion test time are related to the time-to-market (TTM) which plays an important role for
competitive semiconductor companies.
Manufacturing
Manufacturing
(design, assembly & parts)
(design, assembly & parts)
Digital Test
Analog Test
Analog Test
Digital Test
Relative Product Costs Relative Product Costs
(Present) (Future)
Figure 1-1: Electronic Manufacturing/ Test Cost [Robe01]
The challenge which test engineers are faced with is to develop a test methodology in order to
reduce the test cost and to accelerate the time-to-market without sacrificing IC quality.
Consequently, the generation and evaluation of an effective test methodology is a very impor-
tantissueintheproductionofanICthathavingdirectconsequencesonthepriceandthequal-
ity of the final product.
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1.2. Motivation and Problem Definition
Testing can be defined as the process of verifying that an IC meets the specifications for what
was designed [Huer93a]. Thus, the primary need for testing is to perform the following two
sequential tasks:
(1) Checking the design characterizations: this task is calledprototype testing.
(2) Checking manufacturing defects: this task is called production testing.
Theobjectiveofprototypetestingistoverifythecircuitundertest(CUT)characterizations.If
the circuit under test is identified as faulty during design characterization before it is sent to
mass-production, it is desirable to diagnose the cause of the failure. Once faults are identified
and located, a circuit can then be redesigned to enhance the yield of the ICs.
Prior information is required before fault diagnosis can be attempted. Such information
includes optimal test points, optimal measurements, ambiguity groups, testable elements
(which can be isolated), and untestable elements (which are assumed to be nominal). This
information can be obtained by testability analysis of the circuit under test (CUT). The con-
cept of testability analysis is strictly tied to the concept of the element-value solvability prob-
lem, which gives information about the solvability of the test problem for linear analog
circuits. The degree of solvability of the circuit under test can be quantified using testability
measure concept. As a result, the testability measure allows us to know beforehand how many
faulty elements can be identified and how many elements have to be assumed fault-free. The
testability measure is quantitatively given by the rank of the sensitivity matrix (testability
matrix) constructed from the derivation of output parameters with respect to circuit elements.
In low testability circuits, where the testability measure is less than the number of the circuit
elements, the testability analysis is strictly tied to the ambiguity group concept. Ambiguity
groups consist of circuit elements that produce the same values of measurements. Therefore,
the ambiguity groups have to be identified before constructing the fault diagnosis equations.
The ambiguity groups can be determined by finding the null space of the testability matrix, in
other words by finding the linearly dependent columns of the testability matrix. The zero-
valuerowsofnullspacematrixcorrespondtothedefinitelytestableelementsandthenonzero-
value rows and not orthogonal correspond to the elements that belong to the same ambiguity
group. The null space of the testability matrix can be computed by QR factorization or by sin-
gular value decomposition (SVD) of the testability matrix.
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