Modeling and implementation of current-steering digital-to-analog converters

194 Pages·2016·3.26 MB·English

by  K Ola Andersson.

Linköping Studies in Science and Technology
Dissertation No.944
M I
ODELING AND MPLEMENTATION OF
C -S D - -A
URRENT TEERING IGITAL TO NALOG
C
ONVERTERS
K Ola Andersson
Department of Electrical Engineering
Linköpings universitet, SE-581-83 Linköping, Sweden
Linköping, May 2005
Modeling and Implementation of Current-Steering
Digital-to-Analog Converters
Copyright © 2005 K Ola Andersson
Department of Electrical Engineering
Linköpings universitet
SE-58183 Linköping
Sweden
ISBN 91-85297-96-8 ISSN0345-7524
Printed in Sweden by UniTryck, Linköping, 2005
Abstract
Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog
converters(DACs),areinterfacecircuitsbetweentheanaloganddigitaldomains.
They are used in, e.g., digital audio applications, data communication applica-
tions,andothertypesofapplicationswhereconversionbetweenanaloganddigi-
talsignalrepresentationisrequired.Thisworkcoversdifferentaspectsrelatedto
modeling, error correction, and implementation of DACs for communication
applications where the requirements on the circuits in terms of speed and linear-
ityarehard.TheDACarchitectureconsideredinthisworkisthecurrent-steering
DAC,whichisthemostcommonlyusedarchitectureforhigh-speedapplications.
Transistor-level simulation of complex circuits using accurate transistor models
require long simulation times. A transistor-level model of a DAC used in a sys-
temsimulationislikelytobeaseverebottlenecklimitingtheoverallsystemsim-
ulationspeed.Moreover,investigationsofstochasticparametervariationsrequire
multiple simulation runs with different parameter values making transistor-level
models unsuitable. Therefore, there is a need for behavioral-level models with
reasonably short simulation times. Behavioral-level models can also be used to
find the requirements on different building blocks on high abstraction levels,
enablingtheuseofefficienttop-downdesignmethodologies.Modelsofdifferent
nonideal properties in current-steering DACs are used and developed in this
work.
Staticerrorstypicallydominatesthelow-frequencybehavioroftheDAC.Oneof
the limiting factors for the static linearity of a current-steering DAC is mismatch
between current sources. A well-known model of this problem is used exten-
sively in this work for evaluation of different ideas and techniques for linearity
enhancement.Thehigh-frequencybehavioroftheDACistypicallydominatedby
dynamic errors. Models of two types of dynamic errors are developed in this
i
work. These are the dynamic errors caused by parasitic capacitance in wires and
transistorsandglitchescausedbyasymmetryinthesettlingbehaviorofacurrent
source.
The encoding used for the digital control word in a current steering DAC has a
large influence on the circuit performance, e.g., in terms static linearity and
glitches. In this work, two DAC architectures are developed. These are denoted
the decomposed and partially decomposed architectures and utilize encoding
strategies aiming at a high circuit performance by avoiding unnecessary switch-
ing of current sources. The developed architectures are compared with the well-
known binary-weighted and segmented architectures using behavioral-level sim-
ulations.
Itcanbe hardtomeetaDACdesignspecificationusingastraightforwardimple-
mentation.Techniquesforcompensationoferrorsthatcanbeappliedtoimprove
the DAC linearity are studied. The well-known dynamic element matching
(DEM) techniques are used for transforming spurious tones caused by matching
errors into white or shaped noise. An overview of these techniques are given in
this work and a DEM technique for the decomposed DAC architecture is devel-
oped. In ∆Σ modulation, feedback of the quantization error is utilized to spec-
trally shape the quantization noise to reduce its power within the signal band. A
technique based on this principle is developed for spectral shaping of DAC non-
linearityerrorsutilizingaDACmodelinafeedbackloop.Twoexamplesofutili-
zation of the technique are given.
Four different current-steering DACs implemented in CMOS technology are
developed to enable comparison between behavioral-level simulations and mea-
surements on actual implementations and to provide platforms for evaluation of
differenttechniquesforlinearityimprovement.Forexample,a14-bitDEMDAC
isimplementedandmeasurementresultsarecomparedwithsimulationresults.A
good agreement between measured and simulated results is obtained. Moreover,
a configurable 12-bit DAC capable of operating with different degrees of seg-
mentation and decomposition is implemented to evaluate the proposed decom-
posedarchitecture.Measurementresultsagreewithresultsfrombehavioral-level
simulations and indicate that the decomposed architecture is a viable alternative
to the commonly used segmented architecture.
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Acknowledgments
First of all, I would like to thank my supervisor, Prof. Mark Vesterbacka for his
guidance and enthusiasm. I would also like to thank all my colleagues at Elec-
tronics Systems, Linköping University, for contributing to a pleasant working
environment. Special thanks go to Lic. Eng. Robert Hägglund, Lic. Eng. Henrik
Ohlsson, and Ph.D. Oscar Gustafsson for interesting discussions on research and
life in general.
My former colleagues at Ericsson Microelectronics also deserve my gratitude.
Specifically, I would like to thank Ph.D. J.Jacob Wikner, M.Sc. NiklasU.
Andersson, and Ph.D. Mikael Karlsson Rudberg. I also thank Ph.D. Gunnar
BjörklundandM.Sc.MagnusHägglundforsupportingmyworkduringtheyears
I spent doing research at Ericsson Microelectronics.
Finally, I thank my wonderful family, especially my wife Helena and my daugh-
ter Elin, for always believing in me and supporting me.
The work was supported by the Microelectronics Research Center (MERC) at
Ericsson Microelectronics and the Center for Industrial Information Technology
(CENIIT) at Linköping University.
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Contents
Chapter 1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Digital-to-Analog Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1.1 Sampling and Reconstruction . . . . . . . . . . . . . . . . . . . . . . .1
1.1.2 Pulse-Amplitude Modulation . . . . . . . . . . . . . . . . . . . . . . .2
1.1.3 Ideal Reconstruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1.4 Reconstruction with Square Pulses . . . . . . . . . . . . . . . . . .3
1.1.5 The Ideal DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 Telecommunication Applications . . . . . . . . . . . . . . . . . . . . . . . .6
1.2.1 Digital Subscriber Line Applications . . . . . . . . . . . . . . . . .6
1.2.2 The Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.2.3 Effects of Nonideal Transmission . . . . . . . . . . . . . . . . . . .8
1.2.4 DACs for DSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.3 Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.3.1 Metrics in the Code Domain. . . . . . . . . . . . . . . . . . . . . . .12
1.3.2 Metrics in the Frequency Domain . . . . . . . . . . . . . . . . . .13
1.4 Converter Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.4.1 Nyquist-Rate and Oversampled Converters . . . . . . . . . . .17
1.4.2 Current-Steering DACs . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.4.3 Charge-Redistribution DACs . . . . . . . . . . . . . . . . . . . . . .20
1.4.4 R-2R Ladder DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.4.5 Resistor-String DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.4.6∆Σ DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.5 CMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
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1.5.1 Large-Signal Models . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.5.2 Small-Signal Models . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.5.3 Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.5.4 Device Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
1.5.5 CMOS Transistors in Current-Steering DACs . . . . . . . . .33
1.6 Outline of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
1.6.1 Chapter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
1.6.2 Chapter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
1.6.3 Chapter 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
1.6.4 Chapter 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
1.7 Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
1.7.1 Journal Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
1.7.2 Conference Publications . . . . . . . . . . . . . . . . . . . . . . . . . .39
1.7.3 Theses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
1.7.4 Patents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
1.8 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Chapter 2
Modeling of Current-Steering DACs . . . . . . . . . . . . . 45
2.1 Evaluation of Performance Metrics for Static Errors . . . . . .46
2.2 Modeling of Matching Errors . . . . . . . . . . . . . . . . . . . . . . . . . .47
2.2.1 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
2.2.2 Modeling of Random Matching Errors . . . . . . . . . . . . . .48
2.2.3 Modeling of Linearly Graded Matching Errors . . . . . . . .51
2.3 Modeling of Finite Output Impedance . . . . . . . . . . . . . . . . . .56
2.3.1 Finite Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.2 Finite Output Impedance . . . . . . . . . . . . . . . . . . . . . . . . .58
2.4 Modeling of Glitches due to Rise/Fall Asymmetry . . . . . . . . .68
2.4.1 Preliminaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
2.4.2 Model Derivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
2.4.3 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
2.4.4 Glitches in the Differential Output . . . . . . . . . . . . . . . . . .91
Chapter 3
Digital Encoding in Current-Steering DACs . . . . . . . 93
3.1 Binary-Weighted DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
3.2 Segmented DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
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3.3 Decomposed DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
3.3.1 1-Layer Decomposition . . . . . . . . . . . . . . . . . . . . . . . . . .96
3.3.2 Multi-Layer Decomposition . . . . . . . . . . . . . . . . . . . . . . .98
3.3.3 Properties of Decomposed DACs . . . . . . . . . . . . . . . . . . .99
3.4 Partially Decomposed DACs . . . . . . . . . . . . . . . . . . . . . . . . .100
3.5 Other Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
3.6 Comparison of Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
3.6.1 Influence of Matching Errors . . . . . . . . . . . . . . . . . . . . .105
3.6.2 Influence of Glitches . . . . . . . . . . . . . . . . . . . . . . . . . . .109
3.6.3 Simulation Result Summary . . . . . . . . . . . . . . . . . . . . . .114
3.7 Encoder Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
3.7.1 Decomposition Encoder Implementation . . . . . . . . . . . .114
3.7.2 Binary-to-Thermometer Encoder Implementation . . . . .115
Chapter 4
Correction and Compensation of Errors . . . . . . . . . 117
4.1 Dynamic Element Matching . . . . . . . . . . . . . . . . . . . . . . . . . .117
4.1.1 Generalized DEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
4.1.2 DEM Utilizing Switching Trees . . . . . . . . . . . . . . . . . . .120
4.1.3 Mismatch-Shaping DEM . . . . . . . . . . . . . . . . . . . . . . . .122
4.1.4 DEM in Decomposed DACs . . . . . . . . . . . . . . . . . . . . .123
4.2 Distributed Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
4.3 Modulation of Expected Errors . . . . . . . . . . . . . . . . . . . . . . .129
4.3.1 Basic Idea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
4.3.2 Spectral Shaping of Output Impedance Related Errors .131
4.3.3 Yield Enhancement of Binary-Weighted DACs . . . . . .132
Chapter 5
Test-Chip Implementations . . . . . . . . . . . . . . . . . . . . 139
5.1 Design and Measurement Strategies . . . . . . . . . . . . . . . . . . .139
5.1.1 Design Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
5.1.2 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
5.2 A 14-bit Segmented DAC in 0.35µm CMOS . . . . . . . . . . . .144
5.2.1 Chip Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
5.2.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . .145
5.3 A 14-bit PRDEM DAC in 0.35µm CMOS . . . . . . . . . . . . . .147
5.3.1 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
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5.3.2 Simulations and Comparison with Measurements . . . . .148
5.4 A 14-bit Dual DAC in 0.25µm CMOS . . . . . . . . . . . . . . . . .152
5.4.1 Architecture and Implementation . . . . . . . . . . . . . . . . . .152
5.4.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . .154
5.5 A 12-bit Configurable DAC in 0.35µm CMOS . . . . . . . . . .155
5.5.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
5.5.2 Pcell-Based Design Approach . . . . . . . . . . . . . . . . . . . .156
5.5.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
5.5.4 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . .166
Chapter 6
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
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