Modeling and Application of Flexible Electronics Packaging

297 Pages·2019·14.537 MB·English

by  YongAn Huang, Zhouping Yin, Xiaodong Wan

YongAn Huang · Zhouping Yin ·
Xiaodong Wan
Modeling and
Application
of Flexible
Electronics
Packaging
Modeling and Application of Flexible Electronics
Packaging
YongAn Huang Zhouping Yin
(cid:129) (cid:129)
Xiaodong Wan
Modeling and Application
of Flexible Electronics
Packaging
123
YongAnHuang ZhoupingYin
State Key Laboratoryof Digital State Key Laboratoryof Digital
Manufacturing Equipment andTechnology Manufacturing Equipment andTechnology
HuazhongUniversity of Science HuazhongUniversity of Science
andTechnology (HUST) andTechnology (HUST)
Wuhan, People’sRepublic ofChina Wuhan, People’sRepublic ofChina
Xiaodong Wan
State Key Laboratoryof Digital
Manufacturing Equipment andTechnology
HuazhongUniversity of Science
andTechnology (HUST)
Wuhan, People’sRepublic ofChina
ISBN978-981-13-3626-3 ISBN978-981-13-3627-0 (eBook)
https://doi.org/10.1007/978-981-13-3627-0
JointlypublishedwithSciencePress,Beijing,China
TheprinteditionisnotforsaleinChinaMainland.CustomersfromChinaMainlandpleaseorderthe
printbookfrom:SciencePress,Beijing,China.
LibraryofCongressControlNumber:2018968102
©SciencePressandSpringerNatureSingaporePteLtd.2019
Thisworkissubjecttocopyright.AllrightsarereservedbythePublishers,whetherthewholeorpart
of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations,
recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission
orinformationstorageandretrieval,electronicadaptation,computersoftware,orbysimilarordissimilar
methodologynowknownorhereafterdeveloped.
The use of general descriptive names, registered names, trademarks, service marks, etc. in this
publicationdoesnotimply,evenintheabsenceofaspecificstatement,thatsuchnamesareexemptfrom
therelevantprotectivelawsandregulationsandthereforefreeforgeneraluse.
Thepublishers,theauthors,andtheeditorsaresafetoassumethattheadviceandinformationinthis
book are believed to be true and accurate at the date of publication. Neither the publishers nor the
authorsortheeditorsgiveawarranty,expressorimplied,withrespecttothematerialcontainedhereinor
for any errors or omissions that may have been made. The publishers remain neutral with regard to
jurisdictionalclaimsinpublishedmapsandinstitutionalaffiliations.
ThisSpringerimprintispublishedbytheregisteredcompanySpringerNatureSingaporePteLtd.
Theregisteredcompanyaddressis:152BeachRoad,#21-01/04GatewayEast,Singapore189721,
Singapore
Foreword
Flexible electronics represent the next-generation microelectronics that offer the
electricalfunctionsofconventional,rigidICtechnologiesbutwiththeabilitytobe
stretched, compressed, twisted, bent, and deformed into arbitrary shapes. They
overcome the fundamental mismatch in mechanics and form and have enabled
applications that are impossible to achieve with hard, planar integrated circuits.
Theirrepresentativeapplicationsincludeepidermiselectronicsthatareconformalto
humanskin,wearablemicrofluidicdeviceforhealthmonitoringsystems,RFIDtags
made up of rigid chips, and flexible antennas. Some of these devices (e.g., RFID
tags) are obtained by packaging high-modulus, rigid, state-of-the-art chip-scale
elements(e.g.,ICchips,MEMS,sensors,andpowersources)thatarefabricatedon
the donor wafer onto flexible/stretchable substrates. Therefore, the chip-scale ele-
ments have to be peeled off from the donor wafer, picked up, and placed on the
receptor flexible/stretchable substrates, where the interfacial mechanics plays a
critical role in the process.
The transfer manipulation (peeling-picking-placing) of chips, such as resistor,
capacitor, sensor, and interconnector is a key technology for advanced packaging.
Majoradvancesintransfermanipulationofelectroniccomponentsanddeviceshave
beenmadeoverthepastdecade.Forflexibleelectronics,thechipstendtobemuch
smaller, thinner, or more flexible to meet the deformability and conformability. It
becomes challenging for transfer manipulation, especially in the large-scale
roll-to-roll production.
Thisbookisthefirstoneabouttheinterfacialmechanicsoftransfermanipulation
for flexible electronics packaging. It covers the state-of-the-art and comprehensive
workonmodeling,simulations,andexperimentsoftheauthors,fromthetheoretical
andexperimentalstudiesontheinterfacialmechanics,tothedesignandfabrication
of stamp for transfer manipulation, and the applications in roll-to-roll assembly of
flexibleelectronics.Multiplyprocessesaredevelopedforthetransfermanipulation
of the chips with wide ranges of the mechanical and interfacial properties for
flexible electronics, including single/multiple-needle peeling, conformal peeling,
laser-induced peeling, vacuum-based picking-up, and low residual stress
placing-on. The theoretical model and experimental verification are conducted
v
vi Foreword
collaboratively to reveal the underlying mechanisms and optimize the peeling
process. A competing index is proposed to characterize the competing fracture
mechanism, namely fracture of the chip and interfacial delamination of the adhe-
sive. These comprehensive analytical, computational, and experimental studies are
very useful for advanced packaging of flexible electronics, as have been demon-
strated in the flip-chip in RFID packaging, membrane electrode assembly in fuel
cell stack, and laser lift-off in flexible devices. This is an excellent reference book
for both academic research and industrial design offlexible electronics packaging.
Yonggang Huang
Member, US National Academy of Engineering
Foreign Member, Academia Europaea
Foreign Member, Chinese Academy of Sciences
Northwestern University
Evanston, IL, USA
Preface
Over the past decade, technological developments have enabled the flip-chip
packaging for applications in computing, communications, and consumer elec-
tronics. With the developing trends of electronic devices towards large-area and
ultra-thin direction, the demand for the flip-chip packaging continues to grow to
meet the requirements for performance, size, and flexibility, e.g., the flexible dis-
play, radio frequency identification (RFID), wearable electronics, and
bio-integrated electronics.
The transfer manipulation(peeling-picking-placing) ofmicroscale and thinchip
isoneofthekeytechnologiesofadvancedpackagingtoaccuratelytransferasingle
chip from the wafer to a target circuit. Especially as the chips tend to be much
thinner than before, a reliable peeling-picking-placing process is essential to the
electrical performance, cost-effectiveness, service reliability, and life span of
electronic devices. This book addresses important issues concerning the nonde-
structive peeling-picking-placing technique for ultra-thin chip, including
single/multi-needle peeling, conformal peeling, laser lift-off, and vacuum-based
picking-up and placing-on. The theoretical model, physical mechanism, and
experimental verification are conducted. The review on the developments of the
transfer manipulation is discussed in Chap. 1.
In Chap. 2, the interfacial peeling mechanism of the chip-on-substrate structure
subjected to a transversely concentrated load resulting from the single ejector
needle is first investigated, where the adhesive layer is neglected. A finite element
simulation technique is also performed to obtain the energy release rate (ERR) of
interfacial peeling. Then, an analytical model for the chip-adhesive-substrate
structure is established. The corresponding analytical solutions for internal forces,
displacements, and stresses are obtained. The theoretically and numerically esti-
mated ERR of interfacial peeling is used to indicate the peeling behavior at the
adhesive layer.
In Chap. 3, the fracture strength of the ultra-thin silicon chip is first evaluated
combining the geometrically nonlinear theory. The classical linear theory on the
three-point bending test is found failed to match the geometrically nonlinear
characteristics of ultra-thin silicon chip. The peeling behavior of the adhesive tape
vii
viii Preface
from the adherend is then investigated experimentally. A novel homemade
angle/speed controlled peeling platform is developed to assist in estimating the
adhesivefractureenergy,wherethestretchabilityoftheadhesivetapeisconsidered
in the evaluation model.
In Chap. 4, an analytical solution is first presented based on the chip-adhesive-
substrate structure model to determine the adhesive stresses in balanced and
unbalanced stiffened plate, single-strap, and single-lap joints under mixed force
loading and/or displacement boundary conditions. The adhesive stresses are
expressedintermsofgeometricdimensionsandmaterialproperties,combinedwith
integration constants obtained numerically. Then, a mechanical chip-adhesive-
substratemodelisproposedtopredictthepeelingbehaviorofaperiodicarrayofIC
chipsadhesivelybondedtoastretchedsubstrateviathemulti-segmentanalysis.The
process parameters (substrate tension), the geometric parameters (chip thickness,
and chip distance), and the material parameters (Young’s moduli of the chip and
substrate) are considered to predict the peeling status at the adhesive layer.
In Chap. 5, the interfacial peeling mechanism of chip-on-substrate and chip-
adhesive-substratestructuressubjectedtoatransverselyconcentratedloadresulting
fromsingleejectorneedleisfirstinvestigatedfromthefracture mechanicspointof
view. Effects of key factors including the chip size, initial crack length, and sub-
stratematerialareuncovered.AnalyticalexpressionsforadhesivestressesandERR
of interfacial peeling are derived by using structural parameters and integration
constants. Process limitation of the single-needle ejecting technique is discussed.
The competing relationship between the chip peeling and chip cracking in the
single-needle ejecting process isthen investigated combining thechip-on-substrate
structure.Themechanismofcompetingfractureisrevealedfundamentallyusingthe
proposed competing index. Finally, the finite element analysis is adopted to
investigate the contact-impact effect during the single-needle ejecting process
consideringtheimpactspeed,thedistancefromthecontactcenter,andthesubstrate
penetration.
InChap.6,ananalyticalmodelisfirstpresentedtoestimatethebendingnormal
stress of the chip layer and ERR of interfacial peeling in the multi-needle ejecting
process. A competing fracture model and failure criterion of the chip-adhesive-
substratestructurebasedonchippeelingandchipcrackingindexesareputforward
tosolvetheconflictbetweenthechippeelingandchipcrackingforultra-thinchips.
Improvementontheultra-thinchippeeling-offthroughthemulti-needleadoptionis
discussed and compared with the single-needle ejecting process. The process
windowispreliminarilyexploredconsideringthechipgeometry,thestrengthofthe
adhesive layer, and the layout of ejector needles. A modified multi-needle ejecting
process using independently controlled ejector needles is finally proposed to
improve the peelability of ultra-thin chips.
In Chap. 7, a mechanical model is first established to address the roll-to-roll
(R2R) conformal peeling of the device-adhesive-substrate structure. Analytical
expressionsofthepeelstressandshearstressattheintermediateadhesivelayerare
derivedundertheconformalconditionofthecurvedsurface.Theallowableranges
of thethickness of thedevice and substrate layers aredeterminedfor a safe device
Preface ix
peeling-off. A competition model is established combining the conformal criterion
to distinguish the device breakage and successful peeling-off. The peelability cri-
terionfortheconformalpeelingprocessisproposedthroughthetheoreticalanalysis
andexperimentalverification.Thedesignofthepeelbladeisstudiedcombiningthe
peel radius and validated through the R2R peeling experiment of RFID tags.
In Chap. 8, the laser lift-off (LLO) mechanism of ultra-thin polyimide (PI) film
from the rigid glass carrier is revealed experimentally. The ultra-thin PI film is
separated completely with low internal stress. Process parameters of the laser flu-
ence and irradiation time are considered to determine the process window. The
processmechanismisinterpretedcombiningthegasproductsgeneratedbythelaser
irradiation, interface adhesion strength, and interface microstructure.
In Chap. 9, a theoretical model of the chip-adhesive-substrate structure is first
developed to reveal the process mechanism of theultra-thin chip picking-up under
the condition of the vacuum adsorption with fixed adhesive tape length. An
improved model consideringtheeffective tape length isfurtherproposedusing the
bisection algorithm. The theoretical process window for the ultra-thin chip
picking-up is determined. The mechanism of the R2R transferring with low inter-
facialresidualstressistheninvestigated.Thecollaborativeoptimizationofmaterial
properties and structural parameters is performed. The feasibility of reducing the
interfacial residual stress is validated by using the R2R experimental platform.
Additionally, with respect to the chip placing-on process, a layerwise
thermal-mechanical model of the ultra-thin chip-on-flex structure considering the
adhesive curing and cooling is developed to predict the ultra-thin chip warpage.
We deeply acknowledge contributors of theoretical and experimental studies,
includingJiankuiChen,BoPeng,ZunxuLiu,JingBian,ZhoulongXu,HuiminLiu,
and Pengpeng Tang. In addition, we want to express our gratitude to the support
from the national natural science foundation of China (No. 51635007, 51705180).
Wuhan, China YongAn Huang
August 2018 Zhouping Yin
Xiaodong Wan
Contents
1 Advanced Electronic Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Adhesively Bonded Multilayer Structure . . . . . . . . . . . . . . . . . . . 5
1.3 Interfacial Peeling-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3.1 Needle Ejecting for Thin Chips. . . . . . . . . . . . . . . . . . . . 6
1.3.2 Conformal Peeling for Large-Area Devices . . . . . . . . . . . 8
1.3.3 LLO for Large-Area Flexible Electronics. . . . . . . . . . . . . 9
1.4 Vacuum-Based Chip Picking-up . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5 Vacuum-Based Chip Placing-on . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.6 Competing Fracture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.6.1 Competing Fracture Behavior . . . . . . . . . . . . . . . . . . . . . 16
1.6.2 Fracture Strength and Adhesive Fracture Energy . . . . . . . 16
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2 Interfacial Modeling of Flexible Multilayer Structures . . . . . . . . . . . 29
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2 Modeling of Chip-on-Substrate Structure . . . . . . . . . . . . . . . . . . . 29
2.2.1 Mechanical Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2.2 Analytical Evaluation on ERR of Interfacial Peeling . . . . 31
2.2.3 Virtual Crack Closure Technique (VCCT). . . . . . . . . . . . 33
2.2.4 Numerical Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.3 Modeling of Chip-Adhesive-Substrate Adhesively Bonded
Joints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.3.1 Adhesive Model on Overlapped Joints . . . . . . . . . . . . . . 34
2.3.2 Equilibrium Equations . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.3.3 Establishment of Differential Equation Set. . . . . . . . . . . . 38
2.3.4 Solutions for Internal Forces and Displacements . . . . . . . 40
2.3.5 Relationships Among Integration Constants. . . . . . . . . . . 44
2.3.6 Theoretical Calculation of ERR of Interfacial Peeling. . . . 46
xi