Model-based design for on-chip systems using and extending Marte and IP-XACT

216 Pages·2017·3.6 MB·English

by  Aamir Mehmood Khan

Model-based design for on-chip systems using and
extending Marte and IP-XACT
Aamir Mehmood Khan
To cite this version:
Aamir Mehmood Khan. Model-based design for on-chip systems using and extending Marte and IP-
XACT.EmbeddedSystems. UniversitéNiceSophiaAntipolis, 2010. English. ￿NNT:2010NICE4002￿.
￿tel-00834283￿
HAL Id: tel-00834283
https://theses.hal.science/tel-00834283
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UNIVERSITÉ DE NICE-SOPHIA ANTIPOLIS

ÉCOLE DOCTORALE STIC
SCIENCES ET TECHNOLOGIES DE L’INFORMATION ET DE LA COMMUNICATION

T H È S E

pour obtenir le titre de

Docteur en Sciences

de l’Université de Nice-Sophia Antipolis

Mention : Informatique

présentée et soutenue par

Aamir MEHMOOD KHAN

MODEL-BASED DESIGN FOR ON-CHIP SYSTEMS
USING AND EXTENDING MARTE AND IP-XACT

Thèse dirigée par Charles ANDRÉ et Frédéric MALLET

soutenue le 11 mars 2010

Jury :
M. Jean-Luc DEKEYSER Professeur Rapporteur, examinateur
M. François TERRIER Directeur de Recherche Rapporteur, examinateur
M. Charles ANDRÉ Professeur Examinateur
M. Frédéric MALLET Maître de conférences Examinateur
M. Pierre BRICAUD Directeur R&D SYNOPSYS Invité

To Mufti Saeed Khan Sahab and the Family Front.

Acknowledgments
Firstly, I would like to thank Mufti Saeed Khan for all his help and guidance
and especially my cousins ‘The Family Front’ for keeping the fun part of my
life alive. I say thanks to hec (Higher Education Commission) Pakistan for
providing me an opportunity to excel in life and serve better my homeland. I
also thank sfere (Soci´et´e Fran¸caise d’Exploration des Ressource Educatives)
for guiding me and making my stay in France easier. I am thankful to the Uni-
versity of Nice, Sophia-Antipolis for the management of my studies and for the
training by the ced (College des E´tudes Doctoral) in which I participated. I pay
my gratitude to the members of cimpaca (Centre Int´egr´e de Micro´electronique
Provence-Alpes-Coˆte d’Azur) design platform for providing an access to the De-
signWare ip Room and all other relevant tools. Especially I would like to thank
Mr. Pierre Bricaud for kindly arranging special lectures on Synopsys Tools.
I say thanks to inria Sophia-Antipolis for welcoming me and for having
provided me with all its resources. Thanks to our project assistant, Patricia
Lachaume for her help and advice in administrative and daily life. I express
gratitude to each member of the aoste project for the time spent with them
and for their support. I thank Benoˆıt Ferrero for helping me on the technical
aspects of my work. I thank Jean-Francois Le Tallec for the discussions and
suggestions regarding SystemC and tlm. I thank Julien Boucaron, Anthony
Coadou and Luc Hogie for having lively discussions. I thank Julien DeAntoni
and Marie-Agn`es Peraldi Frati for giving me their valuable suggestions at the
meetings. I say thanks to my friends Uzair Khan, Sheheryar Malik and Shafqat-
ur-Rehman for having valuable discussions during the coffee breaks. I thank
Najam-ul-Islam for helping me in every aspect of my life and keeping a warm
company with his jolly nature.
And especially, I would like to thank Charles Andr´e, Fr´ed´eric Mallet and
Robert de Simone, my thesis supervisors, for helping, guiding and supervising
my work. They are my best mentors in all aspects of my studies and research
work. I am grateful to Jean-Luc Dekeyser and Franc¸ois Terrier for being my
thesis reviewers. Thank you both for your feedback and the corrections you
suggested. Your constructive criticism was really helpful.

Abstract
On-chip systems (also known as System-on-chip or soc) are more and more
complex. soc design heavily relies on reuse of building blocks, called ips (In-
tellectual Property). These ips are built by different designers working with
different tools. So, there is an urgent demand for interoperability of ips, that
is, ensuring format compatibility and unique interpretation of the descriptions.
ip-xact is a de facto standard defined in the context of electronic system design
to provide portable representations of (electronic) components and ips. It suc-
ceeds in syntactic compatibility but neglects the behavioral aspects. uml is a
classical modeling language for software engineering. It provides several model
elements to cover all aspects of a design (structural and behavioral). We advo-
cate a conjoint use of uml and ip-xact to achieve the required interoperability.
More specifically, we reuse the uml Profile for marte to extend uml elements
with specific features for embedded and real-time systems. marte Generic Re-
source Modeling (grm) package is extended to add ip-xact structural features.
marte Time Model extends the untimed uml with an abstract concept of time,
adequate to model at the Electronic System Level.
The first contribution of this thesis is the definition of an ip-xact domain
model. This domain model is used to build a uml Profile for ip-xact that
reuses, as much as possible, marte stereotypes and defines new ones only when
required. A model transformation has been implemented in atl to use uml
graphical editors as front-ends for the specification of ips and to generate ip-
xact code.
The second contribution addresses the modeling of the ip time properties and
constraints. uml behavioral diagrams are enriched with logical clocks and clock
constraints using the marte Clock Constraint Specification Language (ccsl).
The ccsl specification can serve as a “golden model” for the expected time be-
havior and the verification of candidate implementations at different abstraction
levels (rtl or tlm). Time properties are verified through the use of a dedicated
library of observers.
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R´esum´e
Les Syst`emes sur puce (soc) sont de plus en plus complexes. Leur concep-
tion repose largement sur la r´eutilisation des blocs, appel´es ip (Intellectual Pro-
perty). Ces ip sont construites par des concepteurs diff´erents travaillant avec
des outils diff´erents. Aussi existe-t-il une demande pressante concernant l’in-
terop´erabilit´e des ip, c’est-a`-dire d’assurer la compatibilit´e des formats et l’uni-
cit´e d’interpr´etation de leurs descriptions. ip-xact constitue un standard de facto
d´efini dans le cadre de la conception de syst`emes ´electroniques pour fournir des
repr´esentations portables de composants (´electroniques) et d’ip. ip-xact a r´eussi
a` assurer la compatibilit´e syntaxique, mais il a n´eglig´e les aspects comportemen-
taux. uml est un langage de mod´elisation classique pour le g´enie logiciel. Il four-
nit des ´el´ements de mod`ele propres a` couvrir tous les aspects structurels et com-
portementaux d’une conception. Nous proˆnons une utilisation conjointe d’uml
et d’ip-xact pour r´ealiser la n´ecessaire interop´erabilit´e. Plus pr´ecis´ement, nous
r´eutilisons le profil uml pour marte pour´etendre uml avec des caract´eristiques
temps r´eel embarqu´ees. Le paquetage Mod´elisation G´en´erique de Ressources de
marte est ´etendu pour prendre en compte des sp´ecificit´es structurelles d’ip-
xact. Le Mod`ele de temps de marte ´etend le mod`ele atemporel d’uml avec
le concept de temps logique bien adapt´e `a la mod´elisation au niveau syst`eme
´electronique.
La premi`ere contribution de cette th`ese est la d´efinition d’un mod`ele de do-
maine pour ip-xact. Ce mod`ele de domaine est utilis´e pour construire un profil
umlpourip-xactquir´eutiliseautantquepossiblelesst´er´eotypesdemarteeten
d´efinit de nouveaux uniquement en cas de besoin. Une transformation de mod`ele
a´et´e mise en œuvre dans ATL permettant d’utiliser des´editeurs graphiques uml
comme front-end pour la sp´ecification d’ip et la g´en´eration des sp´ecifications ip-
xact correspondantes. Inversement, des fichiers ip-xact peuvent ˆetre import´es
dans un outil uml par une autre transformation de mod`eles.
La deuxi`eme contribution porte sur la mod´elisation de propri´et´es et de con-
traintestemporellesportantsurdesip.Lesdiagrammescomportementauxd’uml
sont enrichis avec des horloges logiques et des contraintes d’horloge exprim´ees
dans le langage de specification de contraintes d’horloge (ccsl) de marte. La
sp´ecification ccsl peut alors servir de mod`ele de r´ef´erence pour le com-
(cid:28) (cid:29)
portement temporel attendu et la v´erification des impl´ementations `a diff´erents
niveaux d’abstraction (rtl ou tlm). Les propri´et´es temporelles sont v´erifi´ees en
utilisant une biblioth`eque sp´ecialis´ee d’observateurs.
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