Microprocessors and Microsystems 2005: Vol 29 Index

2005·1.7 MB·English

MICROPROCESSORS AND
MICROSYSTEMS
Volume Indices 29 (2005)
Issue 1 pp 1-46 Issues 6 pp 247-305
Issues 2-3 pp 47-131 Issue 7 pp 307-358
Issue 4 pp 133-187 Issues 8-9 pp 359-420
Issue 5 pp 189-246
Issue 10 pp 421-462
Article index L3: An FPGA-based multilayer maze routing An FPGA platform for on-line topology
accelerator exploration of spiking neural networks
Number 1 J. A. Nestor 87 A. Upegui, C. A. Pena-Reyes,
Pseudo-online testing methodologies for E. Sanchez 211
An efficient VLSI implementation of IDEA
encryption algorithm using VHDL various components of field Multimedia extensions for general purpose
M. Thaduri, S.-M. Yoo, R. Gaede 1 programmable gate arrays microprocessors: a survey
An adaptive adjusting mechanism for agent L. Kalyan Kumar, A. S. Ramani, N. T. Slingerland, A. J. Smith 225
A. J. Mupid, V. Kamakoti 99
distributed blackboard architecture
Y. C. Jiang, Z. Y. Xia, Y. P. Zhong, A 5-10 GHz SiGe BiCMOS FPGA with new Number 6
configurable logic block
S.Y. Zhang 9 C. You, J.-R. Guo, R. P. Kraft, M. Chu, A complete platform and toolset for system
Fabrication of 128 x 128 element optical P. Curran, K. Zhou, B. Goda, implementation on fine-grain
switch array by micromachining
J. F. McDonald 121 reconfigurable hardware
technology V. Kalenteridis, H. Pournara, K. Siozos,
S. B. Wang, S. B. Zhou, G. Huang,
K. Tatas, N. Vassiliadis, |. Pappas,
B. F. Xiong, S. H. Chen, X. J. Yi 21 Number 4 G. Koutroumpezis, S. Nikolaidis,
An infrastructure for designing custom Hardware—software co-simulation of S. Siskos, D. J. Soudris,
embedded wide counterflow pipelines bus-based reconfigurable systems A. Thanailakis 247
B. R. Childers, J. W. Davidson 27 K. N. Vikram, V. Vasudevan 133 A distributed decomposition policy for
A pixel cache architecture with selective Memory reference caching for activity computational grid resource allocation
placement scheme based on z-test result reduction on address buses optimization based on utility functions
K.-W. Lee, W.-C. Park, |.-S. Kim, T. Givargis, D. Eppstein 145 C. Li,L. Li 261
T.-D. Han 41 Experimental parallel implementation of a Path-based next N trace prefetch in trace
wavelet-based still image encoder processors
Number 2 & 3 K. Haapala, V. Lappalainen, K.-f. Wang, Z.-z. Ji, M.-z. Hu 273
T. D. Hamalainen 155 A novel defense model for dynamic topology
Advances in FPGA tools and techniques
A comparison-based diagnosis algorithm network based on mobile agent
M. A. Vega-Rodriguez,
tailored for crossed cube multiprocessor Y. C. Jiang, Z. Y. Xia, S. Y. Zhang 289
J. M. Sanchez-Pérez, J. A.G omez-
systems Microprocessor-based FPGA
Pulido 47
X. Yang, G. M. Megson, implementation of SPIHT image
Automatic mapping of C to FPGAs with the
D. J. Evans 169 compression subsystems
DEFACTO compilation and synthesis
Performance enhancement of embedded P. Corsonello, S. Perri, P. Zicari,
system
software based on new register allocation G. Cocorullo 299
P. Diniz, M. Hall, J. Park, B. So,
technique
H. Ziegler 51
J.-Y. Lee, S.-l. Cho, I.-C. Park 177 Number 7
System-level performance evaluation of
reconfigurable processors Self-organizing maps for embedded
Number 5
R. Enzier, C. Plessi, M. Platzner 63 processor selection
Microprocessor and FPGA interfaces for A Petri-net based distributed monitoring B. Martin-del-Brio, A. Bono-Nuez,
in-system co-debugging in field system using PIC microcontrollers N. Medrano-Marqués 307
programmable hybrid systems M. R. Frankowiak, R. |. Grosvenor, An AES crypto chip using a
M. A. Aguirre, J. N. Tombs, P. W. Prickett 189 high-speed parallel pipelined
V. Baena-Lecuyer, J. L. Mora, Formal verification of fault-tolerant software architecture
J. M. Carrasco, A. Torralba, design: the CSP approach S.-M. Yoo, D. Kotturi, D. W. Pan,
L. G. Franquelo 75 W. L. Yeung, S. A. Schneider 197 J. Blizzard 317
PIT: S0141-9331(04)00083-9
Il Index / Microprocessors and Microsystems 29 (2005) I-V
Design and implementation of an FPGA- Bidarte,U. 421 Martin, J.L. 375
based multiple-colour LED display board Blizzard, J. 317 Martin-del-Brio, B. 307
W. Kurdthongmee 327 Bono-Nuez, A. 307 McDonald, J. F. 121
Optimizing SMT processors for IP-packet Medrano-Marqués, N. 307
processing Carrasco. J. M. 75 Megson, G.M. 169
B. Robatmili, N. Yazdani, Chen. S.H. 21 Meneses, J.M. 393
M. Nourani 337 Childers. B. R. 27 Milne,G. 435
Novel architecture for QAM modulator— Cho. S.-l. 177 Mora, J.L. 75
demodulator and its generalization to Choi. 8.-S. 451 Moreo,A.T. 411
multicarrier modulation Chu.M. 121 Mupid, A.J. 99
A. Banerjee, A.S. Dhar 351 Cocorullo.G. 299. 381 Muro, J.S. 411
Corsonello, P. 299, 381
Number 8 & 9 Cuadrado.C. 375 Nestor, J. A. 87
Curran, P. 121 Nikolaidis, S. 247
Recent advances in computer vision and image Nourani. M. 337
processing using reconfigurable hardware
M. A. Vega-Rodriguez, J. M. Sanchez- Davidson, J. W. 27
Pérez, J. A. Gomez-Pulido 359 Dhar, A.S. 351 Pan,D.W. 317
FPGA based EBCOT architecture forJPEG 2000 Diniz, P. 51 Pappas, |. 247
M. Gangadhar, D. Bhatia 363 Park, I.-C. 177
Implementation of a modified Fuzzy Enzier.R. 63 Park, J. 51
C-Means clustering algorithm for real-time 145 Park, W.-C. 41
ae Eppstein, D. Pené a-Reyes,C.A. 211
appacations Evans, D. J. 169 nn 2 y 299, 381
J. Lazaro, J. Arias, J. L. Martin, erri, S. ;
C. Cuadrado, A. Astarloa 375 Frankowiak. M.R. 189 Pnliateznter., M. ee 63
A high-performance fully reconfigurable a io. L.G. 75 ?
FPGA-based 2D convolution processor ee Pournara, H. 247
S. Perri, M. Lanuzza, P. Corsonello, Prickett, P.W 189
G. Cocorullo 381 Gaede, R. 1
The rapid prototyping experience of an H.263 Gangadhar, M. 363 Ramani, A. S. 99
video coder onto FPGA Garrido, M. J. 393 Robatmili,B. 337
M. J. Garrido, C. Sanz, M. Jiménez, Givargis, T. 145
J. M. Meneses 393 Gomez-Pulido, J. A. 47, 359 Sanchez, E. 211
A pipelined array architecture for Euclidean Goda, B. 121 Sanz,C. 393
distance transformation and its FPGA Grosvenor, R.|. 189 Schneider, S.A. 197
implementation Guo, J.-R. 121 Siozos, K. 247
N. Sudha 405 Siskos, S. 247
Experiences on developing computer vision Haapala, K. 155 Slingerland, N. T. 225
hardware algorithms using Xilinx system Hall. M. 51 Smith, A. J. 225
generator Han, T.-D. 41 Sanchez-Pérez, J. M. 47, 359
A. T. Moreo, P. N. Lorente, F. S. Valles, Hamalainen. T.D. 155 So,B. 51
J. S. Muro, C. F. Andrés 411 Hu. M.-z. 273 Soudris, D. J. 247
Huang, G. 21 Sudha, N. 405
Number 10
Multiprocessor SoPC-Core for FAT volume Ji, Z.-2. 273 Tatas, K. 247
computation Jiang, Y.C. 9, 289 Thaduri, M. 1
A. Astarloa, U. Bidarte, J. Lazaro, Jiménez, M. 393 Thanailakis, A. 247
A. Zuloaga, J. Arias 421 Tombs, J.N. 75
Programming paradigms for reconfigurable Kalenteridis, V. 247 Tonia, #. 75
computing Kalyan Kumar, L. 99
G. Lee, G. Milne 435 Kamakoti, V. 99 Upegui, A. 211
Cost effective mixed-type value predictor Kim. |.-S. 41
using distributed ciassification method Kotturi. D. 317 Valles, F.S. 411
B.-S. Choi 451 Koutroumpezis, G. 247 Vassiliadis, N. 247
Kraft.R.P. 121 Vasudevan, V. 133
Kurdthongmee, W. 327 Vega-Rodriguez, M. A. 47, 359
Author Index Vikram, K.N. 133
Lanuzza,M. 381
Aguirre, M.A. 75 Lappalainen, V. 155 Wang, K.-f. 273
Andrés, C.F. 411 Lee,G. 435 Wang, S.B. 21
Arias, J. 375, 421 bee JY. 177
Astarloa,A. 375, 421 Lee. K.-W. 41 Xia, Z. Y. 9, 289
Li,C. 261 Xiong, B. F. 21
Baena-Lecuyer, V. 75 Lik. 264
Banerjee, A. 351 Lorente,P.N. 411 Yang, X. 169
Bhatia,D. 363 Lazaro, J. 375, 421 Yazdani,N. 337
Index / Microprocessors and Microsystems 29 (2005) I-V
Yeung, W.L. 1 Comparison model Embedded software
Yi, XS. 21 A comparison-based diagnosis algorithm Performance enhancement of embedded
Yoo, S.-M. 1, 317 tailored for crossed cube multiprocessor software based on new register allocation
You,C. 121 systems 169 technique 177
Computer vision Embedded systems
Experiences on developing computer Memory reference caching for activity
Zhang, S. Y. 9, 289 vision hardware algorithms using Xilinx reduction on address buses 145
Zhong, Y.P. 9 system generator 411 Encryption algorithm
Zhou, K. 121 Convolution An AES crypto chip using a high-speed
Zhou, S.B. 21 A high-performance fully reconfigurable parallel pipelined architecture 317
Zicari,P. 299 FPGA-based 2D convolution Energy-efficient CLB architecture
Ziegler, H. 51 processor 381 A complete platform and toolset for
Zuloaga, A. 421 Co-simulation system implementation on fine-grain
System-level performance evaluation of reconfigurable hardware 247
reconfigurable processors 63 Euclidean distance transform
Hardware-software co-simulation A pipelined array architecture for
Keyword Index of bus-based reconfigurable Euclidean distance transformation and its
systems 133 FPGA implementation 405
128 x 128 element Cost reduction Evolvable hardware
Fabrication of 128 x 128 element optical Cost effective mixed-type value predictor An FPGA platform for on-line
switch array by micromachining using distributed classification topology exploration of spiking neural
technology 21 method 451 networks 211
Agent cooperation Counterflow pipelines
An adaptive adjusting mechanism for An infrastructure for designing custom
agent distributed blackboard embedded wide counterflow Fault detection and location
architecture 9 pipelines 27 Pseudo-online testing
Agents communication Crossed cube methodologies for various
An adaptive adjusting mechanism for A comparison-based diagnosis algorithm components of field programmable
agent distributed blackboard tailored for crossed cube multiprocessor gate arrays 99
architecture 9 systems 169 Fault tolerance
Architectural synthesis Current mode iogic Formal verification of fault-tolerant
An infrastructure for designing custom A 5-10GHz SiGe BICMOS FPGA with software design: the CSP
embedded wide counterflow new configurable logic block 121 approach 197
pipelines 27 Field programmable gate array
Arithmetic encoder A 5-10GHz SiGe BiCMOS FPGA with
FPGA based EBCOT architecture for Data encryption new configurable logic block 121
JPEG 2000 363 An efficient VLSI implementation of IDEA Field programmable gate array
encryption algorithm using VHDL 1 Design and implementation of an FPGA-
Design automation based multiple-colour LED display
Behavioral synthesis and estimation
Automatic mapping of C to FPGAs with board 327
Automatic mapping of C to FPGAs with
the DEFACTO compilation and synthesis Field programmable gate arrays (FPGAs)
the DEFACTO compilation and synthesis
system 51 Pseudo-online testing methodologies for
system 51
Design framework various components of field
Built-in self-test (BIST)
An infrastructure for designing custom programmable gate arrays 99
Pseudo-online testing methodologies for
embedded wide counterflow Field-programmable gate array
various components of field
pipelines 27 Programming paradigms for
programmable gate arrays 99
Diagnosis algorithm reconfigurable computing 435
Bus encoding
A comparison-based diagnosis algorithm Field-programmable gate arrays
Memory reference caching for activity
tailored for crossed cube multiprocessor System-level performance evaluation of
reduction on address buses 145
systems 169 reconfigurable processors 63
Bus-based
Distributed blackboard Field-programmable-gate-arrays (FPGAs)
Hardware-—software co-simulation of bus-
An adaptive adjusting mechanism for Automatic mapping of C to FPGAs with
based reconfigurable systems 133 agent distributed blackboard the DEFACTO compilation and synthesis
architecture 9 system 51
CAN bus Dynamic reconfiguration Formal verification
A Petri-net based distributed monitoring An FPGA platform for on-line topology Formal verification of fault-tolerant
system using PIC microcontrollers 189 exploration of spiking neural software design: the CSP
Circal networks 211 approach 197
Programming paradigms for Dynamic topology network FPGA
reconfigurable computing 435 A novel defense model for dynamic An FPGA platform for on-line topology
Co-debug topology network based on mobile exploration of spiking neural
Microprocessor and FPGA interfaces for agent 289 networks 211
in-system co-debugging in field FPGA based EBCOT architecture for
programmable hybrid systems 75 JPEG 2000 363
Co-design Embedded Block Coding with Optimized Implementation of a modified Fuzzy C-
Microprocessor and FPGA interfaces Truncation Means clustering algorithm for real-time
for in-system co-debugging in FPGA based EBCOT architecture for applications 375
field programmable hybrid systems 75 JPEG 2000 363
A pipelined array architecture for
Multiprocessor SoPC-Core for FAT Embedded FPGA Euclidean distance transformation and its
volume computation 421 Hardware—software co-simulation of bus- FPGA implementation 405
Co-design environments based reconfigurable systems 133 Multiprocessor SoPC-Core for FAT
Experiences on developing computer Embedded processors volume computation 421
vision hardware algorithms using Xilinx Self-organizing maps for embedded The rapid prototyping experience of an
system generator 411 processor selection 307 H.263 video coder onto FPGA 393
IV Index / Microprocessors and Microsystems 29 (2005) I-V
FPGA design Instruction-level parallelism Microcontroller-based system
L3: An FPGA-based multilayer maze Cost effective mixed-type value predictor Design and implementation of an FPGA-
routing accelerator 87 using distributed classification based multiple-colour LED display
Microprocessor-based FPGA method 451 board 327
implementation of SPIHT image Integrated circuits Microprocessor and microcontroller
compression subsystems 299 Microprocessor-based FPGA selection
FPGA-based hardware implementation implementation of SPIHT image Self-organizing maps for embedded
Experiences on developing computer compression subsystems 299 processor selection 307
vision hardware algorithms using Xilinx Interconnect architecture Microprocessors
system generator 411 A complete platform and toolset for Multimedia extensions for general
Fuzzy C-Means system implementation on fine-grain purpose microprocessors: a survey 225
Implementation of a modified Fuzzy C- reconfigurable hardware 247 Mobile agent
Means clustering algorithm for real-time Internet A novel defense model! for dynamic
applications 375 A Petri-net based distributed monitoring topology network based on mobile
system using PIC microcontrollers 189 agent 289
Model checking
Gate-array lon beam sputtering Formal verification of fault-tolerant
An ew5 -1co0nGfHizgu raSbilGee lBoigiCc MbOlSo ck FPG1A21 with tsFweaibctrhcinhco altaoirgoryna y ofb2 y11 2m8i crx o1m2a8c heilneimnegn t optical Modsuofltuwsa rem uldtesiipglni:e r the CSP approach 197
Graphical user interface An efficient VLSI implementation of IDEA
A complete platform and toolset for IP Core
encryption algorithm using VHDL 1
system implementation on fine-grain Multiprocessor SoPC-Core for FAT Monitoring system
reconfigurable hardware 247 volume computation 421 A Petri-net based distributed monitoring
Grid resource allocation IP-lookup system using PIC microcontrollers 189
A distributed decomposition policy for Optimizing SMT processors for IP-packet MQ encoder
computational grid resource allocation processing 337 FPGA based EBCOT architecture for
optimization based on utility JPEG 2000 363
functions 261 Java Multi agents
Programming paradigms for An adaptive adjusting mechanism for
H.263 reconfigurable computing 435 agent distributed blackboard
The rapid prototyping experience of an JPEG 2000 architecture 9
H.263 video coder onto FPGA 393 FPGA based EBCOT architecture for Multimedia extensions
Hardware acceleration JPEG 2000 363 Multimedia extensions for general
purpose microprocessors: a survey 225
L3: An FPGA-based multilayer maze
routing accelerator 87
Hardware description language LED display board Network defense
Programming paradigms for Design and implementation of an FPGA- A novel defense model for dynamic
reconfigurable computing 435 based multiple-colour LED display topology network based on mobile
board 327 agent 289
Hardware implementation
An AES crypto chip using a high-speed Lee algorithm Network processor
L3: An FPGA-based multilayer maze Optimizing SMT processors for IP-packet
parallel pipelined architecture 317
routing accelerator 87 processing 337
High-performance
A 5-10GHz SiGe BiCMOS FPGA with Low power design Network security
new configurable logic block 121 Memory reference caching for activity Anovel defense model for dynamic topology
reduction on address buses 145 network based on mobile agent 289
Hybrid reconfigurable processors
System-level performance evaluation of Low power FPGA Network topology
reconfigurable processors 63 A complete platform and toolset for An adaptive adjusting mechanism for
Hybrid system system implementation on fine-grain agent distributed blackboard
reconfigurable hardware 247 architecture 9
Microprocessor and FPGA interfaces for
Low-power-design Neural hardware
in-system co-debugging in field
A 5-10GHz SiGe BICMOS FPGA with An FPGA platform for on-line topology
programmable hybrid systems 75
new configurable logic block 121 exploration of spiking neural
networks 211
image coding Neural networks
Experimental parallel implementation of a Market Self-organizing maps for embedded
wavelet-based still image encoder 155 A distributed decomposition policy for processor selection 307
Microprocessor-based FPGA computational grid resource allocation
implementation of SPIHT image optimization based on utility Optimization
compression subsystems 299 functions 261 A distributed decomposition policy for
image MatLab computational grid resource allocation
A pipelined array architecture for Experiences on developing computer optimization based on utility
Euclidean distance transformation and its vision hardware algorithms using Xilinx functions 261
FPGA implementation 405 system generator 411
Image processing Memory access Parallel implementation
A high-performance fully reconfigurable Performance enhancement of embedded Experimental parallel implementation of a
FPGA-based 2D convolution software based on new register allocation wavelet-based still image encoder 155
processor 381 technique 177 Parallel pipelined design
Implementation of a modified Fuzzy C- Microarchitecture An AES crypto chip using a high-speed
Means clustering algorithm for real-time Cost effective mixed-type value predictor parallel pipelined architecture 317
applications 375 using distributed classification Parallelizing compiler technology and
Infrared optical switch array method 451 data dependence analysis
Fabrication of 128 x 128 element optical Microcontroller Automatic mapping of C to FPGAs with
switch array by micromachining A Petri-net based distributed monitoring the DEFACTO compilation and synthesis
technology 21 system using PIC microcontrollers 189 system 51
Index / Microprocessors and Microsystems 29 (2005) I-V
Partial reconfiguration Reconfiguration Temperature coefficient of resistance
Pseudo-online testing methodologies for Hardware-—software co-simulation of bus- Fabrication of 128 x 128 element optical
various components of field based reconfigurable systems 133 switch array by micromachining
programmable gate arrays 99 Redundant codes technology 21
Performance evaluation Memory reference caching for activity Temporal parallelism
Cost effective mixed-type value predictor reduction on address buses 145 An efficient VLSI implementation of IDEA
using distributed classification method 451 Register access encryption algorithm using VHDL 1
Performance metric Performance enhancement of embedded Thread and SMT
Path-based next N trace prefetch in trace software based on new register allocation Optimizing SMT processors for IP-packet
processors 273 technique 177 processing 337
Petri-net Register allocation Throughput
A Petri-net based distributed monitoring Performance enhancement of embedded An AES crypto chip using a high-speed
system using PIC microcontrollers 189 software based on new register allocation parallel pipelined architecture 317
Photolithography technique 177 Topology evolution
Fabrication of 128 x 128 element optical Rendering processor An FPGA platform for on-line topology
switch array by micromachining A pixel cache architecture with selective exploration of spiking neural
technology 21 placement scheme based on z-test networks 211
Pipelining result 41 Trace processor
A pipelined array architecture for Rendering Path-based next N trace prefetch in trace
Euclidean distance transformation and its Design and implementation of an FPGA-based processors 273
FPGA implementation 405
multiple-colour LED display board 327
Pixel cache
RISC Utility
A pixel cache architecture with selective The rapid prototyping experience of an
placement scheme based on z-test A distributed decomposition policy for
result 41 H.263 video coder onto FPGA 393 computational grid resource allocation
Prefetch mechanism optimization based on utility
Path-based next N trace prefetch in trace Safety critical applications functions 261
processors 273 Pseudo-online testing methodologies for
Price various components of field Value predictor
A distributed decomposition policy for programmable gate arrays 99 Cost effective mixed-type value predictor
computational grid resource allocation Segmentation using distributed classification
optimization based on utility Implementation of a modified Fuzzy C- method 451
functions 261 Means clustering algorithm for real-time Vanadium oxide thin films
Profiling applications 375 Fabrication of 128 x 128 element optical
Performance enhancement of embedded SiGe switch array by micromachining
software based on new register allocation A 5-10GHz SiGe BiCMOS FPGA with technology 21
technique 177 new configurable logic block 121 VHDL
Programmable logic array Single instruction multiple data circuits System-level performance evaluation of
A 5-10GHz SiGe BiCMOS FPGA with A high-performance fully reconfigurable reconfigurable processors 63
new configurable logic block 121 FPGA-based 2D convolution Multiprocessor SoPC-Core for FAT
Pseudo-online testing processor 381 volume computation 421
Pseudo-online testing methodologies for Single instruction multipie data Programming paradigms for
various components of field Multimedia extensions for general reconfigurable computing 435
programmable gate arrays 99 purpose microprocessors: a survey 225 VLSI! implementation
SoC An efficient VLSI implementation of IDEA
Rapid prototyping Hardware-software co-simulation of bus- encryption algorithm using VHDL 1
Microprocessor and FPGA interfaces for based reconfigurable systems 133 VLSI routing
in-system co-debugging in field Software design L3: An FPGA-based multilayer maze
programmable hybrid systems 75 Formal verification of fault-tolerant routing accelerator 87
Rapid system prototyping software design: the CSP approach 197
The rapid prototyping experience of an SoPC Wavelet transform
H.263 video coder onto FPGA 393 Multiprocessor SoPC-Core for FAT Experimental parallel implementation of a
Reconfigurable computing volume computation 421 wavelet-based still image encoder 155
Automatic mapping of C to FPGAs with Spiking neuron
the DEFACTO compilation and synthesis An FPGA platform for on-line topology
system 51 exploration of spiking neural Xilinx system generator
Reconfigurable computing networks 211 Experiences on developing computer
System-level performance evaluation of Standard ML vision hardware algorithms using Xilinx
reconfigurable processors 63 Programming paradigms for system generator 411
Programming paradigms for reconfigurable computing 435
reconfigurable computing 435 System-level fault diagnosis Z-test
Reconfigurable-system A comparison-based diagnosis algorithm A pixel cache architecture with selective
A 5-10GHz SiGe BiCMOS FPGA with tailored for crossed cube multiprocessor placement scheme based on z-test
new configurable logic block 121 systems 169 result 41