Microprocessors and Microsystems 2004: Vol 28 Index

2004·2.9 MB·English

MICROPROCESSORS AND
MICROSYSTEMS
Volume Indices 28 (2004)
Issue 1 pp 1-46 Issue 7 pp 351--399
Issue 2 pp 47-94 Issue 8 pp 401-475
Issue 3 pp 95—146 Issue 9 pp 477-518
Issue 4 pp 147-191 Issue 10 pp 519-594
Issues 5-6 pp 193-350
Article index A parallel implementation of exact Euclidean An FPGA-based queue management system
distance transform based on exact for high speed networking devices
Number 1 dilations A. Nikologiannis, |. Papaefstathiou,
A time-triggered transducer network based O. M. Bruno, L. da Fontoura Costa 107 G. Kornaros, C. Kachris 223
A VHDL-Forth Core for FPGAs
on an enhanced IEEE 1451 model FPGA implementation and experimental
P. Doyle, D. Heffernan, D. Duma 1 R. E. Haskell, D. M. Hanna 115 evaluation of a multizone network cache
Reconfigurable co-processor for Kanerva’s
REFLIX: a processor core with native support for P. Berube, M. MacGregor,
sparse distributed memory
control-dominated embedded applications J. N. Amaral 237
M. T. P. Silva, A. P. Braga,
Z. Salcic, P. Roop, M. Biglari-Abhari, An FPGA implementation of a GF(p) ALU for
W. S. Lacerda 127
A. Bigdeli 13 encryption processors
Clock synchronisation on multiple TTCAN
Programming Windows NT device drivers to A. Daly, W. Marnane, T. Kerins,
network channels
operate non-interruptingembeddeddevices E. Popovici 253
C. Ryan, D. Heffernan, G. Leen 135
T. Karin, S. Weiss 27 FPGA implementation of parametric
A carrier peak synchronous direct digital loudspeaker system
demodulation technique and its FPGA Number 4
F. A. Karnapi, W. S. Gan, Y. K.
implementation Embedding a superscalar processor onto a Chong 261
K. Banerjee, B. Dam, K. Majumdar, chip multiprocessor A Simulink-based hybrid codesign tool for
R. Banerjee, D. Patranabis 37 C.-C.Wu 147 rapid prototyping of FPGA’s in signal
Digital lock in amplifier: study, design and processing systems
Number 2 development with a digital signal processor L. M. Reyneri 273
J. Gaspar, S. F. Chen, A. Gordiillo,
Multimedia synchronization based on aspect A hybrid design-time/run-time scheduling
M. Hepp, P. Ferreyra, C. Marqués 157
oriented programming flow to minimise the reconfiguration
The AIDA toolset for design and
A. Furfaro, L. Nigro, F. Pupo 47 overhead of FPGAs
implementation analysis of distributed
DRAM performance as a function of its real-time control systems J. Resano, D. Verkest, D. Mozos,
structure and memory stream locality S. Vernalde, F. Catthoor 291
O. Redell, J. El-khoury, M. Tomgren 163
J. Alakarhu, J. Niittylahti 57 Exploring the design-space for FPGA-based Codesign methodology for computer vision
Formula-based abstractions and symbolic implementation of RSA applications
execution for model checking programs A. Cilardo, A. Mazzeo, L. Romano, J. Albaladejo, D. de Andrés, L. Lemus,
A. Santone, G. Vaglini 69 G. P. Saggese 183 J. Salvi 303
Template-based automatic data flow code FPGA-based fault injection into switch-level
generation for mediaprocessors Number 5 models
M. S. Grow, D. Kim, Y. Kim 77
A. Ejlali, S.G hassem Miremadi 317
Main sequences genetic scheduling for Editorial
A fast parallel implementation of elliptic curve
multiprocessor systems using task M. A. Vega-Rodriguez, J. M. Sanchez-
point multiplication over GF(2””)
duplication Perez, J. A.G omez-Pulido 193
W. Yao, J. You, B. Li 85 FPGA-based implementation of recursive F. Rodriguez-Henriquez, N. A. Sagqib,
algorithms A. Diaz-Pérez 329
V. Sklyarov 197 Scheduling driven circuit partitioning
Number 3
Case study of a functional genomics application algorithm for multiple FPGAs using time-
Dynamic and selective low power data TLB for an FPGA-based coprocessor multiplexed, off-chip, multi-casting
system T. Van Court, M. C. Herbordt, interconnection architecture
J.-H. Lee, G.-H. Park, S.-D. Kim 95 R. J. Barton 213 Y.-S. Kwon, C.-M. Kyung 341
PII: S0141-9331(04)00137-1
IV Index / Microprocessors and Microsystems 28 (2004) III-VIII
Number 7 Flexible architecture for the implementation Das, N. 401
of the two-dimensional discrete wavelet Das, S.K. 417
A simple scheme for PSK demodulation transform (2D-DWT) oriented to FPGA Dattagupta, J. 401
P. Balasubramanian,
devices de Andrés, D. 303
P. M. Aravindakshan, K. Parameswaran,
R. J. Colom-Palero, R. Gadea-Girones, Dhar, S. 427
V. K. Agrawal 351
F. J. Ballester-Merelo Diaz-Pérez, A. 329
Anovel algorithm for weighted average voting M. Martinez-Peiro 509 Ding, W. 467
used in fault tolerant computing systems
Dong, Y. 547
G. R. Latif-Shabgahi 357
A methodology for reconfigurable hardware Number 10 Doyle, P. 1
Duma, D. 1
design based upon evolutionary computation Editorial
F. Fernandez, J. |. Hidalgo, J. Lanchares, S. Liu 519 Ejlali, A. 317
J. M. Sanchez 363 Mitigation of DoS attacks through QoS Elbeshti, M. 499
A cache block reuse prediction scheme regulation Elkateeb, A. 499
J. Jalminger, P. Stenstrém 373 A. Garg, A. L. Narasimha Reddy 521 Elkeelany, O. 387
SPEED: Stand-alone programmable Defend mobile agent against malicious hosts El-khoury, J. 163
ethernet enabled devices in migration itineraries Er,M.J. 491
O. Elkeelany, G. Chaudhry 387 Y. C. Jiang, Z. Y. Xia, Y. P. Zhong,
S. Y. Zhang 531 Fernandez, F. 363
Number 8 A security framework for protecting traffic Ferreyra, P. 157
between collaborative domains
Editorial Y. Dong, C. Choi, Z.-L. Zhang 547 Furfaro, A. 47
J. Dattagupta, N. Das 401
Malguki: an RSS! based ad hoc location Design-space exploration of the most widely Gadea-Girones, R. 509
algorithm used cryptography algorithms Gan, W. S. 261
J. Arias, A. Zuloaga, J. Lazaro, J. Andreu, |. Papaefstathiou, V. Papaefstathiou, Garg, A. 521
C. Sotiriou 561
A. Astarloa 403 Gaspar, J. 157
A real-time heuristic search technique for High speed architectures for Leviathan: a George, A.D. 477
fixed channel allocation (FCA) in mobile binary tree based stream cipher Gomez-Pulido, J. A. 193
D. Sonecha, B. Yang, R. Karri,
cellular communications Gordillo, A. 157
S. Mandal, D. Saha, A. Mahanti 411 D. A. McGrew 573 Grow, M.S. 77
Energy cost analysis of IPSec on handheld
Dynamic multi-channel assignment using
devices
network flows in wireless data networks Hanna, D.M. 115
P.Ni,Z. Li 585
S. K. Das, O. Koyuncu 417 Haskell, R.E. 115
Distributed routing schemes for ad hoc Heffernan, D. 1, 135
networks using a-SPR sets Hepp, M. 157
S. Dhar, M. Q. Rieck, S. Pai, Author Index Herbordt, M.C. 213
E. J. Kim 427 Hidalgo, J. 1. 363
Loop detection in MPLS for wireless sensor Agrawal, V.K. 351 Hsieh, T.-Y. 457
networks Alakarhu, J. 57 Hussain, A. 499
V. Jolly, N. Kimura, S. Latifi, Albaladejo, J. 303
P. K. Srimani 439 Amaral, J.N. 237 lyengar,S.S. 467
A review of medium access protocols for Andreu, J. 403
mobile ad hoc networks with transmission Aravindakshan, P.M. 351 Jalminger, J. 373
power control Arias, J. 403 Jiang, Y.C. 531
L. M. Patnaik, S. H.R. Naqvi 447 Astarloa, A. 403 Jolly, V. 439
An architecture for power-saving
communications in a wireless mobile Balasubramanian, P. 351 Kachris, C. 223
ad hoc network based on location Ballester-Merelo, F. J. 509 Kannan, R. 467
information Banerjee, R. 37 Karin, T. 27
Y.-C. Tseng, T.-Y. Hsieh 457 BartonR,. J. 213 Karnapi, F. A. 261
Energy equivalence routing in wireless Berube, P. 237 Karri, RR. 573
sensor networks Bigdeli, A. 13 Kerins, T. 253
W. Ding, S. S. lyengar, R. Kannan, Biglari-Abhari, M. 13 Kim, D. 77
W. Rummler 467 Braga, A.P. 127 Kim, E. J. 427
Kim, S.-D. 95
Bruno,O.M. 107
Kim, Y. 77
Number 9
Kimura, N. 439
Catthoor, F. 291
Multicast performance modeling and Kornaros, G. 223
Chaudhry, G. 387
evaluation for high-speed unidirectional Koyuncu,O. 417
torus networks Chen, S.F. 157 Kwon, Y.-S. 341
S. Oral, A. D. George 477 Choi,C. 547 Kyung, C-M. 341
Control of a mobile robot using generalized Chong, Y.K. 261
dynamic fuzzy neural networks Cilardo, A. 183 Lazaro, J. 403
M. J. Er, T. P. Tan, S. Y. Loh 491 Colom-Palero, R. J. 509 Lacerda, W.S. 127
Scalable ATM network interface design using Lanchares,J . 363
parallel RISC processors architecture da Fontoura Costa, L. 107 Latif, S. 439
A. Elkateeb, P. Richardson, A. Shaout, Daly, A. 253 Latif-Shabgahi,G.R. 357
A. Hussain, M. Elbeshti 499 Dam, B. 37 Lee, J.H. 95
Index / Microprocessors and Microsystems 28 (2004) III-VIII
Leen,G. 135 Vaglini,G. 69 Automatic code generation
Lemus, L. 303 Van Court, T. 213 Template-based automatic data flow code
iB. 6 Vega-Rodriguez, M.A. 193 generation for mediaprocessors 77
Li, Z. 585 Verkest,D. 291
Liu, S. 519 Vernalde, S. 291 Benchmarking
Loh,S.Y. 491 Multicast performance modeling and
evaluation for high-speed unidirectional
Weiss, S. 27
MacGregor, M. 237 Wu, C.-C. 147 Bintaorryus trneeet works 477
Mahanti, A. 411
FPGA-based implementation of recursive
Majumdar, K. 37 Xia, Z. Y. 531 algorithms 197
Mandal, S. 411 High speed architectures for Leviathan: a
Marnane, W. 253 binary tree based stream cipher 573
Yang, B. 573
Marqués, C. 157 Bioinformatics
Martinez-Peiro, M. 509 Yao, W. 85 Case study of a functional genomics
Mazzeo, A. 183 You, J. 85 application for an FPGA-based
McGrew, D. A. 573 coprocessor 213
Miremadi,S.G. 317 Zhang, S. Y. 531
Mozos, D. 291 Zhang, Z.-L. 547 Cache
Zhong, Y.P. 531 FPGA implementation and experimental
Naqvi,S.H.R. 447 Zuloaga, A. 403 evaluation of a multizone network
cache 237
Ni,P. 585
Cache block reuse
Nigro, L. 47
Keyword Index Acache block reuse predictionscheme 373
Niittylahti, J. 57 m-calculus
Nikologiannis, A. 223 Ad hoc networks Defend mobile agent against malicious
A review of medium access protocols for hosts in migration itineraries 531
Oral,S. 477 mobile ad hoc networks with transmission Chip multiprocessor
power control 447 Embedding a superscalar processor onto
Pai,S. 427 Ad hoc wireless networks a chip multiprocessor 147
Codesign methodology
Papaefstathiou, |. 223, 561 Distributed routing schemes for ad hoc
Papaefstathiou, V. 561 networks using d-SPR sets 427 Codesign methodology for computer
Parameswaran, K. 351 Adaptation layer 3/4 and 5 Covmimsioonn aprpailli ctaetsito nbs enc3h0 3
Scalable ATM network interface design
Park, G.-H. 95 using parallel RISC processors A Simulink-based hybrid codesign tool for
Patnaik, L.M. 447 rapid prototyping of FPGA’s in signal
architecture 499
Patranabis, D. 37 AES processing systems 273
Popovici, E. 253 Design-space exploration of the most Compact genetic algorithm
Pupo, F. 47 widely used cryptography A methodology for reconfigurable
algorithms 561 hardware design based upon evolutionary
Reddy, A.L.N. 521 Agent fault-tolerance computation 363
Redell,O. 163 Defend mobile agent against malicious Computational coprocessor
hosts in migration itineraries 531 Case study of a functional genomics
RReesyanneor,i ,LJ.. M. 291 273 Agent integrity verification application for an FPGA-based
Defend mobile agent against malicious coprocessor 213
Richardson, P. 499 hosts in migration itineraries 531 Configurable logic blocks
Rieck, M.Q. 427 Analog cosimulation A methodology for reconfigurable
Rodriguez-Henriquez, A Simulink-based hybrid codesign tool for hardware design based upon evolutionary
Romano, L. 183 rapid prototyping of FPGA’s in signal computation 363
Cryptography
Roop, P. 13 processing systems 273
Rummiler, W. 467 Analytical modeling An FPGA implementation of a GF(p) ALU
Ryan, C. 135 Multicast performance modeling and for encryption processors 253
High speed architectures for Leviathan: a
evaluation for high-speed unidirectional
torus networks 477 binary tree basec' stream cipher 573
Saggese,G.P. 183 Cycle-accurate performance evaluation
Arithmetic
Saha,D. 411 An FPGA implementation of a GF(p) ALU Scalable ATM network interface design
Salcic, Z. 13 for encryption processors 253 using parallel RISC processors
Salvi, J. 303 AspectJ architecture 499
Sanchez, J.M. 363 Multimedia synchronization based on
Sanchez-Perez, J. M. aspect oriented programming 47 Data compression
Santone, A. 69 Aspect oriented programming FPGA-based implementation of recursive
Saqgib,N. A. 329 Multimedia synchronization based on algorithms 197
aspect oriented programming 47 Data flow
Shaout, A. 499
Associative memory Template-based automatic data flow code
Silva, M.T.P. 127 Reconfigurable co-processor for generation for mediaprocessors 77
Skliyarov, V. 197 Kanerva’s sparse distributed DES
Sonecha, D. 573 memory 127 Design-space exploration of the most
Sotiriou, C. 561 Asynchronous circuits widely used cryptography algorithms 561
Srimani, P. K. 439 Design-space exploration of the most Device drivers
Stenstrom, P. 373 widely used cryptography Programming Windows NT device drivers
algorithms 561 to operate non-interrupting embedded
ATM network interface devices 27
Tan, T.P. 491 Scalable ATM network interface design Digital bit
Torngren, M. 163 using parallel] RISC processors A simple scheme for PSK
Tseng, Y.-C. 457 architecture 499 demodulation 351
VI Index / Microprocessors and Microsystems 28 (2004) III-VIII
Digital signal processing Fault-tolerant Genetic programming
Digital lock in amplifier: study, design and Clock synchronisation on multiple TTCAN A methodology for reconfigurable
development with a digital signal network channels 135 hardware design based upon evolutionary
processor 157 Field-programmable gate arrays computation 363
Digital synchronous demodulation Exploring the design-space for FPGA- (p)
A carrier peak synchronous direct digital based implementation of RSA 183 An FPGA implementation of a GF(p) ALU
demodulation technique and its FPGA Scheduling driven circuit partitioning for encryption processors 253
implementation 37 algorithm for multiple FPGAs using time-
Direct memory access multiplexed, off-chip, multi-casting
Template-based automatic data flow code interconnection architecture 341 Handheld devices
generation for mediaprocessors 77 Field programmable gate array Energy cost analysis of IPSec on
Directed diffusion implementatior handheld devices 585
Energy equivalence routing in wireless FPGA implementation of parametric Hardware description language
sensor networks 467 loudspeaker system 261 SPEED: Stand-alone programmable
Discrete phase locked loop Field programmable gate arrays ethernet enabled devices 387
Digital lock in amplifier: study, design and Codesign methodology for computer Hierarchical finite state machines
development with a digital signal vision applications 303 FPGA-based implementation of recursive
processor 157 A methodology for reconfigurable algorithms 197
Distributed system hardware design based upon evolutionary High-level languages
A parallel implementation of exact computation 363 A Simulink-based hybrid codesign tool for
Euclidean distance transform based on Filtering mechanism rapid prototyping of FPGA’s in signal
exact dilations 107 Dynamic and selective low power data processing systems 273
Dominating set TLB system 95 HW/SW codesign
Distributed routing schemes for ad hoc Finite field arithmetic A Simulink-based hybrid codesign tool for
networks using d-SPR sets 427 A fast parallel implementation of elliptic curve rapid prototyping of FPGA’s in signal
DoS point multiplication over GF(2”) 329 processing systems 273
Mitigation of DoS attacks through QoS Flow network
regulation 521 Dynamic multi-channel assignment using
DPM network flows in wireless datanetworks 417 1EEE1451
Loop detection in MPLS for wireless Formula-based abstractions A time-triggered transducer network
sensor networks 439 Formula-based abstractions and symbolic based on an enhanced IEEE 1451
DRAM execution for model checking programs 69 model 1
DRAM performance as a function of its Forth core Image processing
structure and memory stream locality 57 A VHDL-Forth Core for FPGAs 115 A parallel implementation of exact
Dynamic channel assignment FPGA Euclidean distance transform based on
Dynamic multi-channel assignment using REFLIX: a processor core with native exact dilations 107
network flows in wireless datanetworks 417 support for control-dominated embedded Flexible architecture for the
applications 13 implementation of the two-dimensional
Elliptic curve A VHDL-Forth Core for FPGAs 115 discrete wavelet transform (2D-DWT)
An FPGA implementation of a GF(p) ALU An FPGA-based queue management oriented to FPGA devices 509
for encryption processors 253 system for high speed networking Implementation
Elliptic curve cryptography devices 223 The AIDA toolset for design and
A fast parallel implementation of elliptic A hybrid design-time/run-time scheduling implementation analysis of distributed
curve point multiplication over GF(2”) 1 flow to minimise the reconfiguration real-time control systems 163
Elliptic curve cryptosystems overhead of FPGAs 291 Instruction-level parallelism
An FPGA implementation of a GF(p) ALU FPGA-based fault injection into switch- Embedding a superscalar processor onto
for encryption processors 253 level models 317 achip multiprocessor 147
Embedded devices High speed architectures for Leviathan: a Interconnection architecture
Programming Windows NT device drivers binary tree based stream cipher 573 Scheduling driven circuit partitioning
to operate non-interrupting embedded FPGAs algorithm for multiple FPGAs using time-
devices 27 Reconfigurable co-processor for Kanerva’s multiplexed, off-chip, multi-casting
Embedded systems sparse distributed memory 127 interconnection architecture 341
REFLIX: a processor core with native FPGA application Internet application/service
support for control-dominated embedded Case study of a functional genomics A security framework for protecting traffic
applications 13 application for an FPGA-based between collaborative domains 547
An FPGA-based queue management system coprocessor 213 Interrupts
for high speed networking devices 223 FPGA implementation Programming Windows NT device drivers
Encryption A carrier peak synchronous direct digital to operate non-interrupting embedded
High speed architectures for Leviathan: a demodulation technique and its FPGA devices 27
binary tree based stream cipher 573 implementation 37 IP routing
Energy conservation FPGA prototype FPGA implementation and experimental
An architecture for power-saving FPGA implementation and experimental evaluation of a multizone network
communications in a wireless mobile evaluation of amultizone networkcache 237 cache 237
ad hoc network based on location
information 457
Gate-level modeling Java
Energy equivalence routing FPGA-based fault injection into switch- Multimedia synchronization based on
Energy equivalence routing in wireless level models 317 aspect oriented programming 47
sensor networks 467 Generalized dynamic fuzzy neural
Euclidean distance transform
networks
A parallel implementation of exact Karatsuba—Ofman multipliers
Control of a mobile robot using
Euclidean distance transform based on A fast parallel implementation of elliptic
exact dilations 107 generalized dynamic fuzzy neural curve point multiplication over GF(2”) 329
networks 491
Genetic algorithms
Fault tolerance Main sequences genetic scheduling for Leviathan
Codesign methodology for computer multiprocessor systems using task High speed architectures for leviathan: a
vision applications 303 duplication 85 binary tree based stream cipher 573
Index / Microprocessors and Microsystems 28 (2004) III-VIII
Linux Model checking Performance
Mitigation of DoS attacks through QoS Formula-based abstractions and symbolic A simple scheme for PSK
regulation 521 execution for model checking demodulation 351
Locality programs 69 Performance evaluation
DRAM performance as a function of its Montgomery multiplication Dynamic and selective low power data
structure and memory stream Exploring the design-space for FPGA- TLB system 95
locality 521 based implementation of RSA 183 A cache block reuse prediction
Location awareness Multicast communication scheme 373
An architecture for power-saving Multicast performance modeling and Phase locked loop
communications in a wireless mobile evaluation for high-speed unidirectional Digital lock in amplifier: study, design and
ad hoc network based on location torus networks 477 development with a digital signal
information 457 Multimedia synchronization processor 157
Lock in amplifier Multimedia synchronization based on Phase shift keying
Digital lock in amplifier: study, design and aspect oriented programming 47 A simple scheme for PSK
development with a digital signal Multiprocessor scheduling demodulation 351
processor 157 Main sequences genetic scheduling for Pipeline
Loop detection multiprocessor systems using task High speed architectures for Leviathan: a
Loop detection in MPLS for wireless duplication 85 binary tree based stream cipher 573
sensor networks 439 Multi-protocol label switching Power aware protocols
Low power computing Loop detection in MPLS for wireless Loop detection in MPLS for wireless
Energy cost analysis of IPSec on sensor networks 439 sensor networks 439
handheld devices 585 Multithreaded architecture Power saving
Low power consumption Embedding a superscalar processor onto An architecture for power-saving
Dynamic and selective low power data achip multiprocessor 147 communications in a wireless mobile
TLB system 95 ad hoc network based on location
Low power design information 457
Neighbor switching
SPEED: Stand-alone programmable Problem of malicious hosts
Energy equivalence routing in wireless
ethernet enabled devices 387 Defend mobile agent against malicious
sensor networks 467
hosts in migration itineraries 531
Network processors
MAP An FPGA-based queue management Processor core
Template-based automatic data flow code system for high speed networking REFLIX: a processor core with native
generation for mediaprocessors 77 support for control-dominated embedded
devices 223
Measuring locality Network ready devices applications 13
DRAM performance as a function of its SPEED: Stand-alone programmable Programmable logic device
structure and memory stream locality 57 ethernet enabled devices 387 Flexible architecture for the
Media access implementation of the two-dimensional
Network security
A review of medium access protocols for A security framework for protecting traffic discrete wavelet transform (2D-DWT)
mobile ad hoc networks with transmission between collaborative domains 547 oriented to FPGA devices 509
power control 447 Networks
Memory management
A time-triggered transducer network based
An FPGA-based queue management on an enhanced IEEE 1451 model 1 Quadrature carrier generation
system for high speed networking Mitigation of DoS attacks through QoS A carrier peak synchronous direct digital
devices 411 demodulation technique and its FPGA
regulation 521
Memory system design implementation 37
Neural networks
DRAM performance as a function of
Reconfigurable co-processor for
its structure and memory stream
locality 57 Kanerva’s sparse distributed Railway-interlocking systems
Meta-heuristics memory 127 A novel algorithm for weighted average
Novel algorithm
A real-time heuristic search technique for voting used in fault tolerant computing
A novel algorithm for weighted average
fixed channel allocation (FCA) in mobile systems 357
voting used in fault tolerant computing
cellular communications 223 Rapid prototyping
systems 357
Microarray data analysis A VHDL-Forth Core for FPGAs 115
Case study of a functional genomics Reactive systems
application for an FPGA-based Parallel REFLIX: a processor core with native
coprocessor 213 High speed architectures for Leviathan: a support for control-dominated embedded
Mobile ad hoc network (MANET) binary tree based stream cipher 573 applications 13
An architecture for power-saving Parallel algorithms Real-time
communications in a wireless mobile A parallel implementation of exact A time-triggered transducer network
ad hoc network based on location Euclidean distance transform based on based on an enhanced IEEE 1451
information 457 exact dilations 107 model 1
Mobile communication Parallel processing Real-time system
A real-time heuristic search Main sequences genetic scheduling for The AIDA toolset for design and
technique for fixed channel allocation multiprocessor systems using task implementation analysis of distributed
(FCA) in mobile cellular duplication 85 real-time control systems 163
communications 411 Parametric loudspeaker Reconfigurable computing
Mobile computing FPGA implementation of parametric Exploring the design-space for FPGA-
An architecture for power-saving loudspeaker system 261 based implementation of RSA 183
communications in a wireless mobile Partial reconfiguration Reconfigurable hardware
ad hoc network based on location A hybrid design-time/run-time scheduling A hybrid design-time/run-time scheduling
information 457 flow to minimise the reconfiguration flow to minimise the reconfiguration
Mobile robot control overhead of FPGAs 291 overhead of FPGAs 291
Controi of a mobile robot using Path rerouting Recursive algorithms
generalized dynamic fuzzy neural! Energy equivalence routing in wireless FPGA-based implementation of recursive
networks 491 sensor networks 467 algorithms 197
Vill Index / Microprocessors and Microsystems 28 (2004) III-VII
Redundant network channels Signal processing application Temporal logic
Clock synchronisation on multiple TTCAN FPGA implementation of parametric Formula-based abstractions and symbolic
network channels 135 loudspeaker system 261 execution for model checking
Replacement policy Simulation programs 69
FPGA implementation and experimental SPEED: Stand-alone programmable Time-multiplexing
evaluation of a multizone network ethernet enabled devices 387 Scheduling driven circuit partitioning
cache 237 Simulink HW compilation algorithm for multiple FPGAs using time-
Resource allocation A Simulink-based hybrid codesign multiplexed, off-chip, multi-casting
A real-time heuristic search technique tool for rapid prototyping of interconnection architecture 341
for fixed channel allocation (FCA) FPGA’s in signal processing Time-triggered
in mobile cellular systems 273 A time-triggered transducer network
communications 411 Soft threshold based on an enhanced IEEE 1451
Reuse prediction A novel algorithm for weighted average model 1
A cache block reuse prediction voting used in fault tolerant computing Time-triggered controller area network
scheme 373 systems 357 A time-triggered transducer network
Review Software systems based on an enhanced IEEE 1451
A review of medium access protocols for Formula-based abstractions and symbolic model 1
mobile ad hoc networks with transmission execution for model checking Clock synchronisation on multiple TTCAN
power control 447 programs 69 network channels 135
RISC architecture Solving partial differential equations TMS320C64x
Scalable ATM network interface design A Simulink-based hybrid codesign tool for Template-based automatic data flow code
using parallel RISC processors rapid prototyping of FPGA’s in signal generation for mediaprocessors 77
architecture 499 processing systems 273 Torus networks
Rivest-Shamir—Adieman cryptosystem Sorting Multicast performance modeling and
Exploring the design-space for FPGA- FPGA-based implementation of recursive evaluation for high-speed unidirectional
based implementation of RSA 183 algorithms 197 torus networks 477
Routing algorithm Specification Transducers
Distributed routing schemes for ad hoc The AIDA toolset for design and A time-triggered transducer network
networks using d-SPR sets 427 implementation analysis of distributed based on an enhanced IEEE 1451
Robust algorithms real-time control systems 163 model 1
Malguki: an RSSI based ad hoc location Speculative execution Translation lookaside buffer
algorithm 403 Embedding a superscalar processor onto Dynamic and selective low power data
RSSI location achip multiprocessor 147 TLB system 95
Malguki: an RSSI based ad hoc location Speed-up Transmission power control
algorithm 403 FPGA-based fault injection into switch- A review of medium access protocols for
RTP/RCTP level models 317 mobile ad hoc networks with transmission
Multimedia synchronization based on Spi-calculus power control 447
aspect oriented programming 47 Defend mobile agent against malicious
hosts in migration itineraries 531
UMTS spreader
SPM
Scalable coherent interface A Simulink-based hybrid codesign tool for
Loop detection in MPLS for wireless
Multicast performance modeling and rapid prototyping of FPGA’s in signal
sensor networks 439
evaluation for high-speed unidirectional processing systems 273
Stack-based microprocessor
torus networks 477
A VHDL-Forth Core for FPGAs 115
Scheduling
Steiner system VHDL
Scheduling driven circuit partitioning
Case study of a functional genomics A VHDL-Forth Core for FPGAs 115
algorithm for multiple FPGAs using time-
application for an FPGA-based High speed architectures for Leviathan: a
multiplexed, off-chip, multi-casting
coprocessor 213 binary tree based stream cipher 573
interconnection architecture 341
Stream cipher VHDL simulator
Security protocols
High speed architectures for Leviathan: a Scalable ATM network interface design
Design-space exploration of the most
binary tree based stream cipher 573 using parallel RISC processors
widely used cryptography
Structure learning architecture 499
algorithms 561
Energy cost analysis of IPSec on Control of a mobile robot using VLSI design
generalized dynamic fuzzy neural Flexible architecture for the
handheld devices 585
Sensor networks networks 491 implementation of the two-dimensional
Loop detection in MPLS for wireless Superscalar processor discrete wavelet transform (2D-DWT)
sensor networks 439 Embedding a superscalar processor onto oriented to FPGA devices 509
Service availability achip multiprocessor 147
A security framework for protecting Switch-level modeling Windows NT
traffic between collaborative FPGA-based fault injection into switch- Programming Windows NT device drivers
domains 547 level models 317 to operate non-interrupting embedded
Set covering problem Synthesis devices 27
Distributed routing schemes for ad hoc SPEED: Stand-alone programmable Wireless LAN
networks using d-SPR sets 427 ethernet enabled devices 387 Energy cost analysis of IPSec on
Shortest path routing handheld devices 585
Distributed routing schemes for ad hoc Task duplication Wireless network
networks using d-SPR sets 427 Main sequences genetic scheduling for An architecture for power-saving
Signal processing multiprocessor systems using task communications in a wireless mobile
Flexible architecture for the duplication 85 ad hoc network based on location
implementation of the Task scheduling information 457
two-dimensional discrete wavelet A hybrid design-time/run-time scheduling Wireless Sensor Networks
transform (2D-DWT) oriented to FPGA flow to minimise the reconfiguration Malguki: an RSSI based ad hoc location
devices 509 overhead of FPGAs 291 algorithm 403