Table Of Content

MICROPROCESSORS AND MICROSYSTEMS Volume Indices 26 (2002) Issue 1 pp 1-48 Issue 6 pp 253-300 Issue 2 pp 51-95 Issue 7 pp 301-339 Issue 3 pp 97-147 Issue 8 pp 341-398 Issue4 pp 151-198 Issues 9-10 pp 399-474 Issue 5 pp 199-252 Article index Improvement of energy-efficiency in off-chip A novel technique for eliminating iterative caches by selective prefetching based computation of polarity of micro- Number 1 J. Jalminger, P. Stenstr6m 107 rotations in CORDIC based sine—cosine Interconnection scheme for continuous- generators Parallel implementation of video encoder on quad DSP system media systems-on-a-chip T. Srikanthan, B. Gisuthan 243 O. Lehtoranta, T. Hamalainen, V. Lahtinen, K. Kuusilinna, T. Kangas, V. Lappalainen, J. Mustonen 1 T. Hamalainen 123 Number 6 PRONTO: a system for mobile robot Automatic large-scale integrated circuit navigation via CAD-model guidance synthesis using allocation-based Impact of data dependencies in real-time A. Gasteratos, C. Beltran, G. Metta, scheduling algorithm high performance computing G. Sandini 17 G. Papa, J. Sile 139 M. A. Hossain, U. Kabir, M. O. Tokhi 253 A6.7kbps vector sum excited linear prediction Dataflow computation with intelligent Number 4 memories emulated on field- on TMS320C54xX digital signal processor K. N. Dharani Kumar, K. M. M. Prabhu, Support for broadcast communication in programmable gate arrays (FPGAs) P.C.W.Sommen 27 multicomputer networks S. Ingersoll, S. G. Ziavras 263 A parallel solution to linear systems S. Loucif, M. Ould-Khaoua 151 Bluetooth based home automation system N. Sriskanthan, F. Tan, A. Karande 281 Y. F. Fung, M. F. Ercan, T. K. Ho, Non-linear spatial warping of endoscopic W.L. Cheung 39 images: an architectural perspective for OPTS: increasing branch prediction A CAD-oriented analytical model for real time applications accuracy under context switch frequency-dependent series resistance V. K. Asari, 161 M.-S. Lee, Y.-J. Kang, J.-W. Lee, and inductance of microstrip on-chip High-performance implementation of wavelet S.-R. Maeng 291 interconnect on silicon substrate algorithms on a standard PC H. Ymeri, B. Nauwelaers, K. Maex, J. Niittylahti, J. Lemmetti, J.H elovuo 173 Number 7 S. Vandenberghe, D. De Roest 45 Traffic shaper: required system for an ATM On fault-tolerant data replication in microprocessor adapter distributed systems Number 2 A. K. Koukos, A. F. Evangelatos 181 F. Tenzekhti, K. Day, M. Ould- DRAM simulator for design and analysis of A performance evaluation of cache injection Khaoua 301 digital systems in bus-based shared memory J. Alakarhu, J. Niittylahti 189 Rapid prototyping of DSP algorithms on multiprocessors VLIW TMS320C6701 DSP A. Milenkovic, V. Milutinovic 51 Number 5 K. H. Hong, W. S. Gan, Y. K. Chong, Performance analysis of a selectively T. F. Cheong, S.H. Tan 311 compressed memory system Linux-based experimental boundary scan A portable recorder for long-term fetal heart J.-S. Lee, S.-D. Kim, C.W eems 63 environment rate monitoring TTCAN: a new time-triggered controller area U. Kaé, R. Sedevcié, F. Novak, F. Ahmed, M. 1. Ibrahimy, M. A. Mohd Alli, network A. Biasizzo 199 E. Zahedi 325 G. Leen, D. Heffernan 77 Design of a distributed system architecture Achievement of secure Internet access to including an automatic code generator fieldbus systems Number 3 J. A. de Frutos, J. M. Giron-Sierra 207 T. Sauter, C. Schwaiger 331 Evaluation of dynamic branch predictors for Architecture of a fieldbus message scheduler modern ILP processors Number 8 coprocessor based on the planning N. A. Ismail, 215 paradigm Microprocessor adapter for ATM networks Design of an optimal folding mechanism for E. Martins, P. Neves, J. Fonseca 97 A. K. Koukos, A. F. Evagelatos 233 Java processors PII: SO141-9331(02)00091-1 476 Index / Microprocessors and Microsystems 26 (2002) 475-479 L.-R. Ton, L.-C. Chang, J.-J. Shann, Chung, C.-P. 341 Nah, K.H. 449 C.-P. Chung 341 Corral, J. M. R. 373 Nauwelaers, B. 45 A linear approximation based hybrid Neves, P. 97 approach for binary logarithmic Day, K. 301 Ng, S.Y. 449 De Francesco, N. 391 Niittylahti, J. 173, 189 conversion de Frutos, J. A. 207 Novak, F. 199 S. K. Lam, T. Srikanthan 353 De Roest, D. 45 Particle swarm optimization for task Dharani Kumar, K.N. 27 Ould-Khaoua, M. 151, 301 assignment problem A. Salman, |. Ahmad, S. Al-Madani 363 Er,M.J. 433, 449 Papa, G. 139 Application of bus emulation techniques to Ercan, M.F. 39 Prabhu, K.M.M. 27 the design of a PCI/MC68000 bridge Estévez, A.M. 373 J. M. R. Corral, A. C. Balcells, Evangelatos, A. F. 181, 233 Salman, A. 363 G. J. Moreno, A. M. Estévez, Sandini, G. 17 Fonseca, J. 97 Sauter, T. 331 A. L. Barranco 373 Fung, Y.F. 39 Schwaiger, C. 331 An abstract semantics tool for secure Sedevcic, R. 199 information flow of stack-based assembly Gan, W.S. 311 Shann, J.-J. 341 programs Gasteratos,A. 17 Silc, J. 139 C. Bernardeschi, N. De Francesco, George, A.D. 407 Silven, O. 463 G. Lettieri 391 Giron-Sierra, J. M. 207 Sommen, P.C.W. 27 Gisuthan, B. 243 Srikanthan, T. 243, 353, 399 Srisa-an, W. 421 Numbers 9-10 Hamalainen, T. 1, 123 Sriskanthan, N. 281 Heffernan, D. 77 Stenstrom, P. 107 Area-—time issues in the VLSI Heidari, R. 463 implementation of self organizing map Helovuo, J. 173 Tan, C.C. 433 neural networks Ho, T.K. 39 Tan,F . 281 B. Mailachalam, T. Srikanthan 399 Hong, K.H. 311 Tan, S.H. 311 Layered interactive convergence for Hossain, M.A. 253 Tenzeknhti, F. 301 distributed clock synchronization Tilak, R. 407 R. Tilak, A. D. George, R. W. Todd 407 Ibrahimy, M. 1. 325 Todd, R.W. 407 A performance perspective on the Active Ingersoll, S. 263 Tokhi, M.O. 253 Memory System Ismail, N. A. 215 Ton, L.-R. 341 W. Srisa-an, C.-T. Dan Lo, Jalminger, J. 107 Vandenberghe, S. 45 J.M. Chang 421 Jyrkka, K. 463 Design and development of an intelligent Weems, C. 63 controller for a pole-balancing robot Kabir, U. 253 M. J. Er, B. H. Kee, C. C. Tan 433 Kac, U. 199 Ymeri,H. 45 Real-time implementation of a dynamic fuzzy Kang, Y.-J. 291 neural networks controller for a SCARA Kangas, T. 123 Zahedi, E. 325 M. J. Er, C. B. Low, K. H. Nah, M. H. Lim, Karande, A. 281 Ziavras, S.G. 263 S.Y.Ng 449 Kee, B.H. 433 Kim, S.-D. 63 Component-based development of DSP Keyword Index Koukos, A. K. 181, 233 software for mobile communication Kuusilinna, K. 123 terminals Abstract interpretation K. Jyrkka, O. Silven, O. Ali-Yrkk6, Lahtinen, V. 123 An abstract semantics tool for secure R. Heidari, H. Berg 463 Lam, S.K. 353 information flow of stack-based assembly Lappalainen, V. 1 programs 391 Lee, J.-S. 63 Active vibration control Author Index Lee, J.-W. 291 Impact of data dependencies in real-time Lee, M.-S. 291 high performance computing 253 Ahmad, |. 363 Leen, G. 77 Active vision Ahmed, F. 325 Lehtoranta,O. 1 PRONTO: a system for mobile robot Alakarhu, J. 189 Lemmetti, J. 173 navigation via CAD-model guidance 17 Ali-Yrkko, O. 463 Lettieri, G. 391 Adaptive control Al-Madani, S. 363 Lim, M.H. 449 Real-time implementation of a dynamic Asari, V.K. 161 Lo,C.T.D. 421 fuzzy neural networks controller for a Loucif,S. 151 SCARA 449 Barranco, A.L. 373 Low, C.B. 449 Algorithms for real-time control Balcells, A.C. 373 Real-time implementation of a dynamic Beltran, C. 17 Maeng, S.-R. 291 fuzzy neural networks controller for a Berg, H. 463 Maex, K. 45 SCARA 449 Bernardeschi, C. 391 Mailachalam, B. 399 Architecture Biasizzo, A. 199 Martins, E. 97 Component-based development of DSP Metta, G. 17 software for mobile communication Chang, J.M. 421 Milenkovic, A. 51 terminals 463 Chang, L.-C. 341 Milutinovic, V. 51 ATM connection identification and Cheong, T. F. 311 Mohd Ali, M. A. 325 classification Cheung, W.L. 39 Moreno, G. J. 373 Microprocessor adapter for ATM Chong, Y.K. 311 Mustonen, J. 1 networks 233 Index / Microprocessors and Microsystems 26 (2002) 475-479 ATM header error control Cluster computing A CAD-oriented analytical model for Microprocessor adapter for ATM Layered interactive convergence for frequency-dependent series resistance networks 233 distributed clock synchronization 407 and inductance of microstrip on-chip ATM microprocessor adapter Code excited linear prediction interconnect on silicon substrate 45 Microprocessor adapter for ATM A 6.7 kbps vector sum excited linear Distributed systems networks 233 prediction on TMS320C54xX digital signal Design of a distributed system Traffic shaper: required system for an processor 27 architecture including an automatic code ATM microprocessor adapter 181 Comparative analysis generator 207 ATM network On fault-tolerant data replication in On fault-tolerant data replication in Microprocessor adapter for ATM distributed systems 301 distributed systems 301 networks 233 Component software PRONTO: a system for mobile robot ATM traffic shaper Component-based development of DSP navigation via CAD-model guidance 17 Microprocessor adapter for ATM software for mobile communication DRAM networks 233 terminals 463 DRAM simulator for design and analysis ATM traffic shaping mechanism Compressed memory system of digital systems 189 Traffic shaper: required system for an Performance analysis of a selectively DSP ATM microprocessor adapter 181 compressed memory system 63 Component-based development of DSP ATM transmitter and receiver Compression algorithm software for mobile communication Microprocessor adapter for ATM Performance analysis of a selectively terminals 463 networks 233 compressed memory system 63 Parallel implementation of video encoder Automatic circuit design Computer aided design on quad DSP system 1 Automatic large-scale integrated circuit PRONTO: a system for mobile robot Dynamic data replication synthesis using allocation-based navigation via CAD-model guidance On fault-tolerant data replication in scheduling algorithm 139 17 distributed systems 301 Automatic code generator Computer arithmetic Design of a distributed system A linear approximation based hybrid Effective rate architecture including an automatic code approach for binary logarithmic Traffic shaper: required system for an generator 207 conversion 353 ATM microprocessor adapter 181 Automotive networks Content addressable memories Embedded system(s) TTCAN: a new time-triggered controller Area-time issues in the VLSI A performance perspective on the Active area network 77 implementation of self organizing map Memory System 421 neural networks 399 Application of bus emulation techniques to Binary logarithmic conversion Context switch the design of a PCI/MC68000 A linear approximation based hybrid OPTS: increasing branch prediction bridge 373 approach for binary logarithmic accuracy under context switch 291 Endoscopic images conversion 353 Convergence Non-linear spatial warping of endoscopic Bluetooth technology Layered interactive convergence for images: an architectural perspective for Bluetooth based home automation distributed clock synchronization 407 real time applications 161 system 281 Co-ordinate rotation digital computer Energy-delay Boundary scan controller A novel technique for eliminating iterative Improvement of energy-efficiency in off- Linux-based experimental boundary scan based computation of polarity of micro- chip caches by selective prefetching 107 environment 199 rotations in CORDIC based sine—cosine Energy-efficiency Branch prediction generators 243 Improvement of energy-efficiency in off- OPTS: increasing branch prediction Coprocessors chip caches by selective prefetching 107 accuracy under context switch 291 Architecture of a fieldbus message EPOC folding model Branch predictor scheduler coprocessor based on the Design of an optimal folding mechanism Evaluation of dynamic branch predictors planning paradigm 97 for Java processors 341 for modern ILP processors 215 Evolutionary computation Bridge Data dependency Automatic large-scale integrated circuit Application of bus emulation techniques to Impact of data dependencies in real-time synthesis using allocation-based the design of aPCI/MC68000 bridge 373 high performance computing 253 scheduling algorithm 139 Broadcast communication Data forwarding Support for broadcast communication in A performance evaluation of cache Fault tolerance multicomputer networks 151 injection in bus-based shared memory Layered interactive convergence for Bus emulation multiprocessors 51 distributed clock synchronization 407 Application of bus emulation techniques to Dataflow computation On fault-tolerant data replication in the design of a PCI/MC68000 Dataflow computation with intelligent distributed systems 301 bridge 373 memories emulated on field- Fetal electrocardiogram programmable gate arrays (FPGAs) 263 A portable recorder for long-term fetal Cache architecture Digital signal processor heart rate monitoring 325 Performance analysis of a selectively A 6.7 kbps vector sum excited linear Fetal heart rate compressed memory system 63 prediction on TMS320C54xX digital signal A portable recorder for long-term fetal Cache coherence protocols processor 27 heart rate monitoring 325 A performance evaluation of cache Digital systems Fetal monitoring injection in bus-based shared memory Architecture of a fieldbus message A portable recorder for long-term fetal multiprocessors 51 scheduler coprocessor based on the heart rate monitoring 325 Caches planning paradigm 97 Fieldbus(es) Improvement of energy-efficiency in off- Direct memory access Achievement of secure Internet access to chip caches by selective prefetching Application of bus emulation techniques to fieldbus systems 331 107 the design of a PCI/MC68000 Architecture of a fieldbus message Clock synchronization bridge 373 scheduler coprocessor based on the Layered interactive convergence for Distributed series inductance and planning paradigm 97 distributed clock synchronization 407 resistance Design of a distributed system 478 Index / Microprocessors and Microsystems 26 (2002) 475-479 architecture including an automatic code Java fuzzy neural networks controller for a generator 207 A performance perspective on the Active SCARA 449 Field-programmable gate arrays Memory System 421 Dataflow computation with intelligent Java processor On-chip interconnect memories emulated on field- Design of an optimal folding mechanism A CAD-oriented analytical model for programmable gate arrays (FPGAs) 263 for Java processors 341 frequency-dependent series resistance Finite difference method Java Virtual Machine and inductance of microstrip on-chip Impact of data dependencies in real-time Design of an optimal folding mechanism interconnect on silicon substrate 45 high performance computing 253 for Java processors 341 On-line data compression Formal verification Performance analysis of a selectively An abstract semantics tool for secure k-ary n-cubes compressed memory system 63 information flow of stack-based assembly Support for broadcast communication in Open software programs 391 multicomputer networks 151 Component-based development of DSP Fuzzy inference system software for mobile communication Design and development of an intelligent Linear approximation terminals 463 controller for a pole-balancing robot A linear approximation based hybrid 433 approach for binary logarithmic Parallel algorithms Fuzzy systems conversion 353 A parallel solution to linear systems 39 Real-time implementation of a dynamic Linear predictive coding Parallel architectures fuzzy neural networks controller for a A 6.7 kbps vector sum excited linear Parallel implementation of video encoder SCARA 449 prediction on TMS320C54xX digital signal on quad DSP system 1 processor 27 Particle swarm optimization Gateway Linux device driver Particle swarm optimization for task Achievement of secure Internet access to Linux-based experimental boundary scan assignment problem 363 fieldbus systems 331 environment 199 PCI LU decomposition Application of bus emulation techniques to H.263 A parallel solution to linear systems 39 the design of a PC!I/MC68000 Parallel implementation of video encoder bridge 373 on quad DSP system 1 Magnetic potential Pentium Hardware support for garbage collection A CAD-oriented analytical model for High-performance implementation of A performance perspective on the Active frequency-dependent series resistance wavelet algorithms on a standard Memory System 421 and inductance of microstrip on-chip PC 173 High-level synthesis interconnect on silicon substrate 45 Performance comparison Automatic large-scale integrated circuit Manipulators Support for broadcast communication in synthesis using allocation-based Real-time implemeniation of a dynamic multicomputer networks 151 scheduling algorithm 139 fuzzy neural networks controller for a Performance evaluation High performance computing SCARA 449 DRAM simulator for design and analysis Impact of data dependencies in real-time Mark-sweep garbage collection of digital systems 189 high performance computing 253 A performance perspective on the Active Improvement of energy-efficiency in off- Home automation Memory System 421 chip caches by selective prefetching 107 Bluetooth based home automation Memory latency POC folding model system 281 A performance evaluation of cache Design of an optimal folding mechanism Hypergraphs injection in bus-based shared memory for Java processors 341 Support for broadcast communication in multiprocessors 51 Pole-balancing robot multicomputer networks 151 Memory management Design and development of an intelligent Hypermeshes Impact of data dependencies in real-time controller for a pole-balancing robot 433 Support for broadcast communication in high performance computing 253 Polynomial mapping multicomputer networks 151 Memory performance analysis Non-linear spatial warping of endoscopic Performance analysis of a selectively images: an architectural perspective for IEEE 1149.1 compressed memory system 63 real time applications 161 Linux-based experimental boundary scan Memory system Portable environment 199 DRAM simulator for design and analysis A portable recorder for long-term fetal Instruction level parallelism of digital systems 189 heart rate monitoring 325 A parallel solution to linear systems 39 Micro-controller Prefetching Intellectual property Bluetooth based home automation Improvement of energy-efficiency in off- Interconnection scheme for continuous- system 281 chip caches by selective prefetching 107 media systems-on-a-chip 123 Design and development of an intelligent Preventive flow control Intelligent memories controller for a pole-balancing robot 433 Traffic shaper: required system for an Dataflow computation with intelligent Microprocessor ATM microprocessor adapter 181 memories emulated on field- OPTS: increasing branch prediction Private caches programmable gate arrays (FPGAs) accuracy under context switch 291 A performance evaluation of cache 263 Mobile communications injection in bus-based shared memory Interactive convergence Component-based development of DSP multiprocessors 51 Layered interactive convergence for software for mobile communication Processor performance distributed clock synchronization 407 terminals 463 Evaluation of dynamic branch predictors Interconnection networks Modulo scheduling for modern ILP processors 215 Support for broadcast communication in Rapid prototyping of DSP algorithms on Prototyping multicomputer networks 151 VLIW TMS320C6701 DSP 311 Dataflow computation with intelligent Interconnection Multicomputers memories emulated on field- Interconnection scheme for continuous- Support for broadcast communication in programmable gate arrays (FPGAs) 263 media systems-on-a-chip 123 multicomputer networks 151 Internet Rapid prototyping Achievement of secure Internet access to Neural network systems Rapid prototyping of DSP algorithms on fieldbus systems 331 Real-time implementation of a dynamic VLIW TMS320C6701 DSP 311 Index / Microprocessors and Microsystems 26 (2002) 475-479 Real-time frequency-dependent series resistance Superscalar TTCAN: a new time-triggered controller and inductance of microstrip on-chip Evaluation of dynamic branch predictors area network 77 interconnect on silicon substrate 45 for modern ILP processors 215 Real-time control SIMD System-on-a-chip Impact of data dependencies in real-time High-performance implementation of Interconnection scheme for continuous- high performance computing 253 wavelet algorithms on a standard media systems-on-a-chip 123 Real-time message scheduling PC 173 Architecture of a fieldbus message Simulation scheduler coprocessor based on the DRAM simulator for design and analysis Task assignment problem planning paradigm 97 of digital systems 189 Particle swarm optimization for task Real-time systems Simulink assignment problem 363 A performance perspective on the Active Rapid prototyping of DSP algorithms on Task interaction graph Memory System 421 VLIW TMS320C6701 DSP 311 Particle swarm optimization for task Real-time workshop Sine-—cosine generator assignment problem 363 Rapid prototyping of DSP algorithms on A novel technique for eliminating iterative Time-triggered VLIW TMS320C6701 DSP 311 based computation of polarity of micro- TTCAN: a new time-triggered controller Robot navigation rotations in CORDIC based sine—cosine area network 77 PRONTO: a system for mobile robot generators 243 Time-triggered controller area network navigation via CAD-model guidance 17 Smart cards TTCAN: a new time-triggered controller Achievement of secure Internet access to area network 77 Scalable cache-coherent shared memory fieldbus systems 331 TMS320C6201 multiprocessors Snooping Parallel implementation of video encoder A performance evaluation of cache A performance evaluation of cache on quad DSP system 1 injection in bus-based shared memory injection in bus-based shared memory TMS320C6x multiprocessors 51 multiprocessors 51 Rapid prototyping of DSP algorithms on Scheduling and allocation Software implementation VLIW TMS320C6701 DSP 311 Automatic large-scale integrated circuit High-performance implementation of synthesis using allocation-based waveletalgorithmsonastandardPC 173 scheduling algorithm 139 Software-controlled cache prefetching Vector quantization Secure information flow A performance evaluation of cache Area-time issues in the VLSI An abstract semantics tool for secure injection in bus-based shared memory implementation of self organizing map information flow of stack-based assembly multiprocessors 51 neural networks 399 programs 391 Spatial warping Vector sum excited linear prediction Security Non-linear spatial warping of endoscopic A 6.7 kbps vector sum excited linear Achievement of secure Internet access to images: an architectural perspective for prediction on TMS320C54xX digital signal fieldbus systems 331 real time applications 161 processor 27 Self organizing map neural networks Speculative execution Video coding Area-time issues in the VLSI Evaluation of dynamic branch predictors Parallel implementation of video encoder implementation of self organizing map for modern ILP processors 215 on quad DSP system 1 neural networks 399 Split Decomposition Algorithm Virtual component interface Signal processing algorithms A novel technique for eliminating iterative Interconnection scheme for continuous- High-performance implementation of based computation of polarity of micro- media systems-on-a-chip 123 wavelet algorithms on a standard rotations in CORDIC based sine—cosine PC 173 generators 243 Signed-digit pre-computation Stack based assembly code Wavelet A novel technique for eliminating iterative An abstract semantics tool for secure High-performance implementation of based computation of polarity of micro- information flow of stack-based assembly wavelet algorithms on a standard rotations in CORDIC based sine—cosine programs 391 PC 173 generators 243 Stack operations folding Wireless network Silicon semiconducting substrate Design of an optimal folding mechanism Bluetooth based home automation A CAD-oriented analytical model for for Java processors 341 system 281