Microprocessors and Microsystems 1994: Vol 18 Index

5 Pages·1994·1.5 MB·English

MICROPROCESSORS AND
MICROSYSTEMS
Index to Volume 18 (1994)
No 1 pp 1-64 No 6 pp 305-368
No 2 pp 65-120 No 7 pp 369-424
No 3 pp 121-184 No 8 pp 425-496
No 4 pp 185-240 No 9 pp 497-568
No 5 pp 241-304 No 10 pp 569-632
Article index K. V. M. Deva Raju, S. V. Subba Rao, Real-time transputer simulation of the
K. V. Srinivasan and human peripheral hearing system
Number 1 K. Visvanathan 101 C. Swan, D. M. Howard and
16-bit DSP servo control with the A.M. Tyrrell 215
Training fully recurrent neural MC68HC 1621 Distributed event-driven simulation of
networks on a ring transputer array D. Wilson 109 a novel dynamic dataflow
G. Kechriotis and multiprocessor system—PATTSY
E.S. Manolakos 5 Number 3 V. Lakshmi Narasimhan and
Use of a single chip fixed-point DSP for A case study in specifying and testing A.C. Lewty 223
multiple speech channel vocoders architectural features Pentium processor thermal design
N. Tsakalos and E. Zigouris 12 P. Krishnan 123 guidelines
A counter-based Hough transform A performance comparison of several D. R. McCutchan and
system superscalar processor models with J. W. Reilly 231
T. Hanif and M. B. Sandler 19
A technique for the implementation of aJ. VLLeInWel l praoncde sNs.o rB agherzadeh 131 Number 5
low frequency digital filters with Transputer-based fault-tolerant and fail- Electronic design of a solar correlation
simple FAD-based hardware safe node for dual ring distributed tracker based on a video motion
P.A. Witting 27 railway signalling systems estimation processor
A DSP-based acoustic feedback K.V. Kumar and V. Chandra 141 E. Ballesteros, F. Lorenzo, T. Viera,
canceller for public address M. Reyes and J. A. Bonet 243
Investigating the effects of induced
systems A four-channel communications arbiter
faults in transputer systems
M.H. Er, T. H. Ooi, L. S. Li and for multiprocessor arrays
A. M. Mukherjee and A. M.
C.J. Liew 39 V. Lakshmi Narasimhan, K. Wood
Tyrrell 151
Live insertion considerations for Designing systems with objects, and T. Downs 253
Philips TTL bus-interface logic Design of an MS-DOS PC program
processes and modules
devices B.R. Kirk 165 profiler
Y.1.S. Shin 48 3 V systems spur evolution of the RS- K. V. Subramaniam and
M. J. Thazhuthaveetil 261
232 standard
Printing grey scale images on a fax
Number 2 T. Fleming 173
machine
The BSP400: a modular
Number 4 P. Zemick and E.L. Dagless 271
neurocomputer SYNC_WAVE: a high accuracy and low
J. N. H. Heemskerk, J. Hoekstra, Reverse scheduling—an effective overhead algorithm for clock
J. M. J. Murre, L. H. J. G. Kemna and method for scheduling tasks of synchronization in transputer
P.T.W.Hudson 67 parallel programs employing a networks
A multiprocessor system for visual divide-and-conquer strategy onto G. de Pietro and U. Villano 281
communications using distributed muitiprocessors Microprocessor supervisory
transputer arrays A Sreenivas, K. N. Balasubramanya circuits 291
W.-J. Duh, J. L. Wu and Murthy and C. Siva Ram Murthy 187
J.-H. Huang 79 RSM-—a restricted shared memory Number 6
Optimization of a control algorithm architecture for high speed inter- An adaptive switching architecture for
using a simulation package processor communication multiprocessor networks
A. S. White and G. Kelly 89 G. N. Khan, K. Mahmud, M. S. Iqbal N. Sriskanthan, A. Das, P. Loh and
Displaying digital images ina and H. U. Rashid 193 A.H. Leong 307
distributed processing environment Interfacing high-level and assembly Performance of the IMS A100 digital
1. Spence 95 language with microcodes in 3-D signal processor for real-time
Multichannel real-time data acquisition image generation deconvolution
system using dual ported FIFO A. A. Wardak, G. A. King and T. Sanchez, J. J. Anaya and
buffers R. Backhouse 205 C. Fritsch 315
0141-9331/94/10/0627-05 © 1994 Butterworth-Heinemann Ltd
Microprocessors and Microsystems Volume 18 Number 10 December 1994 627
Index
Design of a robot control system Number 9 Downs, T. 253
architecture Duh, W.-J. 79
Task scheduling policies for real-time
N. Chen and G. A. Parker 323 Dzikowski, J.-U. 537
systems
Artificial neural networks ona
B. KourouSic-Seljak 501 Er, M.H. 39
reconfigurable, fault-tolerant, multi-
processor system A formally based hard real-time kernel Eswaran, C. 481
S. Cavalieri, A. Di Stefano and S. Bradley, W. Henderson, Evans, N.E. 473
D. Kendall and A. Robson 513
O. Mirabella 331
Computer-assisted exercise ECG Fawcett, B. K. 547
A modified discrete Fourier-cosine analysis: real-time scheduling Fine, R. 351
transform algorithm and its VLSI
within MS-DOS on PCs Fleming, T. 173
implementation
D. Zazula, A. Sostarié, D. Korze and Fritsch, C. 315
P. Tzionas, Ph. Tsalides and
D. Korosec 523
A. Thanailakis 343 Halang, W. A. 579
Using databases to support the
Considerations for selecting a DSP development of microcode Hanif, T. 19
processor (ADSP-2101 vs. J.-U. Dzikowski and Heemskerk, J. N.H. 67
TMS320C50) Hegde, A. 613
P. A. Rounce 537
R. Fine and G. McGuire 351 Henderson, W. 513
System-integration features and
developmenttools key to FPGA design Hoekstra, J. 67
B. K. Fawcett 547 Howard, D.M. 215
Number 7 Howse, J. 593
Huang, J.-H. 79
Number 10
A new fault-tolerant multi-transputer Hudli, A. V. 393
configuration for avionics two-lane Task scheduling in hard real-time Hudli, R. V. 393
systems embedded systems using hardware Hudson, P. T.W. 67
T. Torii and M.S. Chelian 371 cO-processors Hughes, T.S. 385
An intelligent distributed system for J.E. Cooling 571
real-time control of cone crushers A hardware supported operating Iqbal, M.S. 193
M. Moshgbar and R. M. Parkin 337 system kernel for embedded hard
Kechriotis, G. 5
Making formal specifications real-time applications
Kelly, C. 89
accessible through the use of M. Colnarié, W. A. Halang and
animation prototyping R.M. Tol 579 Kemna, L.H. J. G. 67
J. E. Cooling and T.S. Hughes 385 Structuring formal specifications—a Kendall, D. 513
Finding small feedback vertex sets for lesson relearned Khan, G.N. 193
King, G. A. 205
VLSI circuits R. Mitchell, M. Loomes and
Kirk, B.R. 165
A. V. Hudli and R. V. Hudli 393 J. Howse 593
Korosec, D. 523
Comparison of the performance of a Interupt Replay: a debugging method
KorouSsic-Seljak, B. 501
fuzzy controller with a PID controller for parallel programs with interrupts
for a heating process K. M. R. Audenaert and Korze, D. 523
Y.K. Wong and A.B. Rad 401 L.J. Levrouw 601 Krishnan, P. 123
Fuzzy logic and the Neuron Chip 409 Error detection and correction with the Kumar, K. V. 141
IDT49C466
Lakshmi Narasimhan, V.
A. Hegde 613
Lenell, J. 131
Number 8 Leong, A.H. 307
Levrouw, L. J. 601
Special section: Logic Synthesis Author index
Lewty, A.C. 223
Lik. S:. 39
Multi-level logic synthesis based on
Abrahams, M.S. 459 Liew, C.J. 39
decomposition
Adamski, M. 451 Lipp, H.M. 469
T. Luba 429
Amroun, A. 451 Loh, P. 307
MASCOT: Microarchitecture synthesis
Anaya, J.J. 315 Loomes, M. 593
of control paths
Audenaert, K. M.R. 601 Lorenzo, F. 243
A.J.W.M.ten Berg 439
Luba, T. 429
Parallel controller synthesis for Backhouse, R. 205
programmable logic devices
Bagherzadeh, N. 131 Mahmud, K. 193
J. Pardey, A. Amroun, M. Bolton and
Balasubramanya Murthy, K.N. 187 Manolakos,E.S. 5
M. Adamski 451 Ballesteros, E. 243 McCutchan, D.R. 231
Translation of VHDL for logic synthesis
M.S. Abrahams and Bolton, M. 451 McGuire, G. 351
Bonet, J. A. 243 Mcllroy, S. J. 473
ARTA.U SR~u—sahnt ono pen4 59f ramework for logic Bradley, S. 513 Mirabella, O. 331
synthesis Mitchell, R. 593
Cavalieri, S. 331 Moshgbar, M. 377
O. von Steuber and H.M. Lipp 469
Chandra, V. 141 Mukherjee, A.M. 151
Chelian, M.S. 371 Murre, J. M. J. 67
Research Chen, N. 323
An encoding telemeter for climatic Colnaric, M. 579 Ooi, T.H. 39
temperature monitoring using a Cooling, J. E. 385, 571
single chip microcontroller Pardey, J. 451
S.J. Mclilroy and N.E. Evans 473 Dagless,E.L. 271 Parker, G. A. 323
Systolic array implementation of Das, A. 307 Parkin, R. M. 377
artificial neural networks de Pietro, G. 281
K. Vijayan Asari and Deva Raju, K.V.M. 101 Rad, A.B. 401
C. Eswaran 481 Di Stefano, A. 331 Rashid, H. U. 193
628 Microprocessors and Microsystems Volume 18 Number 10 December 1994
Reilly, J. W. 231 CAE Divide-and-conquer
Reyes, M. 243 Field programmable gate arrays, Task graph, Multiprocessor
Robson, A. 513 Programmable logic 547 system 187
Rounce, P. A. 537 Centralized arbiter Dual-port memory
Rushton, A. 459 Timeout arbiter, Signal Fault-tolerant architectures, Inter-
synchronization 253 processor communication 193
Sanchez, T. 315 Circuit-switching architecture Dynamic peak detection
Sandler, M.B. 19 Multiprocessor, Fault- Counter-based Hough transform,
Siva Ram Murthy, C. 187 tolerance 307 Dedicated architecture 19
Sostari¢, A. 523 Climate monitoring
Spence, |. 95 Radio telemetry, Temperature EIA/TIA-562
Sreenivas, A. 187 monitoring 473 RS-232, Serial interface
Srinivasan, K. V. 101 Clock synchronization standards 173
Sriskanthan, N. 307 Parallel program performance Error correction
Subba Rao, S.V. 101 evaluation, Multicomputers 281 Error detection, IDT49C466 613
Subramaniam, K. V. 261 Co-processors Error detection
Swan, C. 215 Scheduling, Hardware 571 Error correction, IDT49C466 613
Operating system kernel, Real-
ten Berg, A. J. W.M. 439 time 579 FAD
Thanailakis, A. 343 Control Digital signal processing, MS2014 27
Thazhuthaveetil, M. J. 261 Fuzzy logic, Neuron Chip 409 FIFO
Tol, R. M. 579 Control design styles Data acquisition, Sustained
Torii, T. 371 control structures, Logic throughput 101
Tsakalos,N. 12 design 439 Fail-safe
Tsalides, Ph. 343 Control structures Fault tolerance, Transputers 141
Tyrrell, A.M. 151, 215 Control design styles, Logic Fault tolerance
Tzionas, P. 343 design 439 Fail-safe, Transputers 141
Control system
Circuit-switching architecture,
Viera, T. 243 Optimization, Simulation 89 Multiprocessor 307
Correlation tracker
Vijayan Asari, K. 481 Neural network simulation, Multi-
Villano, U. 281 Transputers, Image stabilizer 243 DSP architecture 331
Counter-based Hough transform
Visvanathan, K. 101 Transputer, Multi-processing 371
von Steuber, O. 469 Dedicated architecture, Dynamic Fault tolerant architectures
peak detection 19
Dual-port memory, Inter-processor
Wardak, A.A. 205 communication 193
DSP
White, A. S. 89 Fax machines
Deconvolution, Benchmarks 315
Wilson, D. 109 grey scale images, Surveillance 271
ADSP-2101, TMS 320C50 351
Witting, P. A. 27 Feedback vortex cover
DSP-based canceller
Wong, Y. K. 401 NP-complete problem, VLSI
Acoustic feedback canceller 39
Wood, K. 253 circuits 393
Data acquisition
Wu, J.-L. 79 Field programmable gate arrays
Sustained throughput, FIFO 101
Programmable logic, CAE 547
Databases
Zazula, D. 523 Formal methods
Zemick, P. 271 DatMaifclroow comduel tid-epvreolcoepssmienngt 537 Real-time, Performance
Zigouris,E. 12 prediction 513
Distributed event-driven simulation,
Formal specification
Unix system 223
Decomposition, Modifiability 593
Decomposition
Formal specifications
Keyword index Formal specification, Animation prototyping, Real-time
Modifiability 593
systems 385
Deconvolution
Futurebus+
Al DSP, Benchmarks 315
Interface standard, Application
Real-time control, Distributed Dedicated architecture
profiles 561
system architecture 377 Counter-based Hough transform,
Fuzzy logic
ADSP-2101 Dynamic peak detection 19
Intelligent control, PID tuning 401
DSP, TMS 320C50 351 Digital circuits
Neuron Chip, Control 409
Acoustic feedback cancelier Learning rule, Neural net 481
DSP-based canceller 39 Digital signal processing
Animation prototyping MS2014, FAD 27 Grey scale images
Fax machines, Surveillance 271
Formal specifications, Real-time Servo control, MC68HC16Z1 109
systems 385 Digital signal processors
Application profiles Speech coding algorithms, Real-time Hardware
Futurebus-+, Interface speech coder implementations 12 Scheduling, Co-processors 571
standard 561 Discrete Fourier-cosine transform Hardware malfunctions
Architecture Parallel architectures, VLSI 343 Transputers, Induced faults 151
SPARC, Specification 123 Distributed computing High-level language
Assembly language Image processing, X Windows 95 Assembly language,
Highi-level language, Distributed event-driven simulation Microcode 205
Microcode 205 Dataflow multi-processing, Unix
system 223 IDT49C466
Benchmarks Distributed system architecture Error detection, Error
DSP, Deconvolution 315 Real-time control, A1 377 correction 613
Microprocessors and Microsystems Volume 18 Number 10 December 1994 629
Index
Image processing NP-complete problem Radio telemetry
Distributed computing, X Feedback vertex cover, VLSI Temperature monitoring, Climate
Windows 95 circuits 393 monitoring 473
Image stabilizer Neural net Real-time
Correlation tracker, Digital circuits, Learning rule 481 Formal methods, Performance
Transputers 243 Neural network simulation prediction 513
induced faults Multi-DSP architecture, Fault- Operating system kernel, Co-
Transputers, Hardware tolerance 331 processors 579
malfunctions 151 Neural networks Real-time application
Intelligent control Neurocomputers, Multi-processor Transputers, Signal processing 215
Fuzzy logic, PID tuning 401 systems 67 Real-time control
inter-processor communication Neurocomputers Distributed system architecture,
dual-port memory, Fault-tolerant Multi-processor systems, Neural A1 377
architectures 193 networks 67 Real-time embedded computer
Interface standard Neuron Chip systems
Futurebus-+, Application Fuzzy logic, Control 409 Real-time executives, Task
profiles 561 scheduling policies 501
Interrupts Real-time executive
Objects
Parallel debugging, Replay 601 Multitasking, On-line exercise 523
Processes, Modules 165
Real-time executives
On-line exercise
LTC692 Real-time embedded computer
Real-time executive,
LTC693, Supervisory circuits 291 systems, Task scheduling
Multitasking 523
LTC693 policies 501
Open framework
LTC692, Supervisory circuits 291 Real-time speech coder im-
Logic synthesis, User interface 469
Learning rule plementations
Operating system kernel
Digital circuits, Neural net 481 Digital signal processors, Speech
Co-processors, Real-time 579
Logic decomposition coding algorithms 12
Optimization
PLA, PLD 429 Real-time system software
Control system, Simulation 89
Logic design Robot control, Transputer
Control structures, Control design programming 323
styles 439 PID tuning Real-time systems
Logic synthesis Intelligent control, Fuzzy logic 401 Animation prototyping, Formal
Open framework, User PLA specifications 385
interface 469 Logic decomposition, PLD 429 Recurrent neural networks
PLD Parallel processing, Transputer
MC68HC16Z1 Logic decomposition, PLA 429 arrays 5
Digital signal processing, Servo PLDs Replay
control 109 Parallel controllers, Petri nets 451 Parallel debugging, Interrupts 601
MS-DOS PC Parallel architectures Robot control
Program profiling 261 Discrete Fourier-cosine transform, Real-time system software,
MS2014 VLSI 343 Transputer programming 323
Digital signal processing, FAD 27 Parallel controllers
Microcode Petri nets, PLDs 451 SPARC
High-level language, Assembly Parallel debugging Architecture, Specification 123
language 205 Interrupts, Replay 601 Scheduling
Microcode development Parallel program performance Hardware, Co-processors 571
Databases 537 evaluation Serial-interface standards
Modifiability Clock synchronization, RS-232, EIA/TIA-562 173
Formal specification, Multicomputers 281 Servo control
Decomposition 593 Parallel processing Digital signal processing,
Modules Recurrent neural networks, MC68HC16Z1 109
Objects, Processes 165 Transputer arrays 5 Signal processing
Multi-DSP architecture Pentium Transputers, Real-time
Neural network simulation, Fault- Thermal design, Thermal application 215
tolerance 331 requirements 231 Signal synchronization
Multi-processing Performance prediction Centralized arbiter, Timeout
Fault tolerance, Transputer 371 Real-time, Formal methods 513 arbiter 253
Multi-processor systems Petri nets Simulation
Neurocomputers, Neural Parallel controllers, PLDs 451 Optimization, Control system 89
networks 67 Pipe-lining Specification
Multicomputers Superscalar, Very long instruction Architecture, SPARC 123
Clock synchronization, Parallel word (VLIW) 131 Speech coding algorithms
program performance Processes Digital signal processors, Real-time
evaluation 281 Objects, Modules 165 speech coder implementations 12
Multiprocessor Program profiling Superscalar
Circuit-switching architecture, Fault- MS-DOS PC 261 Very long instruction word (VLIW),
tolerance 307 Programmable logic Pipe-lining 131
Multiprocessor system Field programmable gate arrays, Supervisory circuits
Divide-and-conquer, Task graph 187 CAE 547 LTC692, LTC693 291
Multitasking RS-232 Surveillance
Real-time executive, On-line EIA/TIA-562, Serial interface Grey scale images, Fax
exercise 523 standards 173 machines 271
630 Microprocessors and Microsystems Volume 18 Number 10 December 1994
Sustained throughput Timeout arbiter Unix system
Data acquisition, FIFO 101 Centralized arbiter, Signal Distributed event-driven simulation,
Synthesis synchronization 253 Dataflow multi-processing 223
VHDL, Translation 459 Translation User interface
VHDL, Synthesis 459 Logic synthesis, Open
Transputer framework 469
Fault tolerance, Multi-
TMS 320C50 processing 371
VHDL
DSP, ADSP-2101 351 Transputer array
Synthesis, Translation 459
Task graph Video telephone 79
VLSI
Divide-and-conquer, Transputer arrays
Multiprocessor system 187 Parallel processing, Recurrent Discrete Fourier-cosine transform,
Parallel architectures 343
Task scheduling policies neural networks 5
VLSI circuits
Real-time embedded computer Transputer programming
systems, Real-time Real-time system software, Robot Feedback vertex cover, NP-
complete problem 393
executives 501 control 323
Very long instruction word (VLIW)
Temperature monitoring Transputers
Superscalar, Pipe-lining 131
Radio telemetry, Climate Fail-safe, Fault tolerance 141
Video telephone
monitoring 473 Induced faults, Hardware
Transputer array 79
Thermal design malfunctions 151
Pentium, Thermal Real-time application, Signal
requirements 231 processing 215 X Windows
Thermal requirements Correlation tracker, Image Image processing, Distributed
Pentium, Thermal design 231 stabilizer 243 computing 95
Microprocessors and Microsystems Volume 18 Number 10 December 1994 631