Table Of Content

MICROPROCESSORS AND MICROSYSTEMS Index to Volume 16 (1992) No 1 pp 1-56 No 6 pp 281-336 No 2 pp 57-112 No 7 pp 337-392 No 3 pp 113-168 No 8 pp 393-448 No 4 pp 169-224 No 9 pp 449-504 No 5 pp 225-280 No 10 pp 505-560 Author index Civit-Breu, A see Jimenez, G, 177 Gopalakrishnan, G and Akella, V, visi Clematis, A, Dodero, G and Gianuzzi, V, asynchronous systems: specification and Key: (AN) = application note Process checkpointing primitives for fault synthesis, 517 tolerance: definitions and examples, 15 Gray, J see Abnous, A, 187 Abnous, A, Christensen, C, Gray, J, Lenell, Clements, A see Briers, A C, 541 J, Naylor, A and Bagherzadeh, N, Design Cockshott, P see Barrie, P, 115 Hanke, C and Tharalson, G, Low skew and implementation of the ‘Tiny Risc’ Coraor, L D see Hulina, P T, 237 clock drivers and their system design microprocessor, 187 Cvijovic, M and Kunc, M, An approach to considerations (AN), 493 Akella, V see Gopalakrishnan, G, 517 the design of distributed real-time Hulina, P T, Kurian, L, John, E B and Allinson, N M and Sales, M J, CART - a operating systems, 81 Coraor, L D, Design and visi implementation cellular automata research tool, 403 of an access processor for a decoupled Anderson, A J, A transputer based Deka, R, Singh, B and Glover, | A, A two- architecture, 237 supervisor for adaptive signal processing, pass TMS320C25 for the Motorola 291 EXORMacs, 133 INMOS colour look-up tables (AN), 37 Arden, B see Youssef, A, 3 Devine, M L, Real time trignometric Izu, C, Arruabarrena, A and Beivide, R, Arruabarrena, A see Izu, C, 301 function evaluation, 417 Analysis and evaluation of message Diaz, F see Jimenez, G, 177 management functions for bidimensional Baer, J-L see Bertoni, J, 339 Dipert, B and Verner, D, Designing an transputer networks, 301 Bagherzadeh, N see Abnous, A, 187 updatable Bios using flash memory (AN), Balaji, K R see Ranganathan, N, 227 427 Jain, V K, Wills, } M and Wadekar, S A, Ball, E see Gibbs, D S, 59 Diwakar, H see Ranade, D, 263 Parallel processing architectures for Balsara, P T see Vaidyanathan, A, 321 Dodero, G see Clematis, A, 15 advanced signal processing, 471 Barlas, G D, Frangakis, G and Skordalakis, Doughman, G, Use of stack simplifies Janssens, B see Stunkel, C B, 249 E, TFGs: a transputer file and graphics M68HC11 programming (AN), 207 Jimenez, G, Sevillano, } L, Civit-Balcells, A, system for PC-hosted machines, 453 Dowling, E M see Vaidyanathan, A, 321 Diaz, F and Civit-Breu, A, risc-based Barrie, P, Cockshott, P, Milne, G J and Dowling, E M, Linebarger, D A, Tong, Y architectures for multiple robot systems, 177 Shaw, P, Design and verification of a and Munoz, M, An adaptive microphone John, E B see Hulina, P T, 237 highly concurrent machine, 115 array processing system, 507 Battiti, R and Tecchiolli, G, Parallel biased Kim, J, Park, J}a nd Kwon, W H, search for combinatorial optimization: Eswaran, C see Premalatha, G, 311 Architecture of a ladder solving processor genetic algorithms and Tabu, 351 Evans, N E see Wang, L-Q, 141 for programmable controllers, 369 Beivide, R see Izu, C, 301 Koztowski, K see Florek, A, 171 Bertoni, J, Baer, J-L and Wang, W-H, Farell, R see Tragoudas, S, 481 Kunc, M see Cvijovic, M, 81 Scaling shared-bus multi-processors with Farhat, H and From, S, Bounds on Kurian, L see Hulina, P T, 237 multiple buses and shared caches: a population coverage using test generation Kwon, W H see Kim, J, 369 performance study, 339 by fault sampling, 269 Bertossi, A A and Mancini, L, Fault-tolerant Florek, A, Koztowski, K, Wroblewski, W Lenell, J see Abnous, A, 187 tpt task scheduling in multiprocessor and Gapinski, J, Computer-controlled Li, Q and Rishe, N, CONNECT - an systems, 91 digital correlator and its application in architecture for a highly parallel system Briers, AC and Clements, A, Object- experimental physics, 171 based on building blocks, 67 oriented experiences with Eric, 541 Frangakis, G see Barlas, G D, 453 Linebarger, D A see Dowling, E M, 507 Burger, L, Strategies for testing and From, S see Farhat, H, 269 Lombardi, F see Salinas, J, 529 monitoring VMEbus installations (AN), 381 Fuchs, W K see Stunkel, C B, 249 Luque, E, Suppi, R and Sorribes, J, Burger, L J, Board level bus analysers for Designing parallel systems: a performance VMEbus and beyond (AN), 159 Gapinski, ) see Florek, A, 171 prediction problem, 25 Burns, )B see Wang, L-Q, 141 Gianuzzi, V see Clematis, A, 15 Gibbs, D S, Ball, E and Calvignac, G, A Makedon, F see Tragoudas, S, 481 Calvignac, G see Gibbs, D S, 59 content addressable memory for data Mancini, L see Bertossi, A A, 91 Christensen, C see Abnous, A, 187 communications, 59 Mick, } R, Introduction to ipt’s FourPort Civit-Balcells, A see Jimenez, G, 177 Glover, | A see Deka, R, 133 RAM (AN), 101 Vol 16 No 10 1992 Milne, G J see Barrie, P, 115 Sales, M J see Allinson, N M, 403 Vaidyanathan, A, Dowling, E M and Milway, M J, A serial tram: design and Salinas, )a nd Lombardi, F, A data path Balsara, P T, Design and implementation testing, 195 approach for testing microprocessors with of a multi-microprocessor architecture for Munoz, M see Dowling, E M, 507 a fault bound: the MC68000 case, 529 image processing, 321 Sevillano, ] L see Jimenez, G, 177 Vainio, O and Ovaska, S J, Real-time AC Shaw, P see Barrie, P, 115 motor modelling with the TMS320C25 Naylor, A see Abnous, A, 187 Shono, K see Takakubo, H, 395 signal processor, 125 Singh, B see Deka, R, 133 Van den Bout, D E see Thomae, D A, 283 Ovaska, S J see Vainio, O, 125 Skordalakis, E see Barlas, G D, 453 Verner, D see Dipert, B, 427 Sorribes, J see Luque, E, 25 Srinidhi, H N see Ranganathan, N, 227 Park, ] see Kim, J, 369 Stunkel, C B, Janssens, B and Fuchs, W K, Wadekar, S A see Jain, V K, 471 Plata, O G see Zapata, E L, 463 Address tracing of parallel systems via Wang, L-Q, Evans, N E and Burns, J B, A Premalatha, G and Eswaran, C, Personal TRAPEDS, 249 portable data acquisition system for fading computer based cardiac monitor, 311 Suppi, R see Luque, E, 25 evaluation in UHF radio channels, 141 Wang, W-H see Bertoni, J, 339 Ranade, D and Diwakar, H, Distributed Wills, )M see Jain, V K, 471 memory management on a multi- Takakubo, H and Shono, K, An image Wroblewski, W see Florek, A, 171 transputer system, 263 tracing approach using CMos variable Ranganathan, N, Balaji, K R and Srinidhi, H threshold logic, 395 N, A visi array processor chip for Tecchiolli, G see Battiti, R, 351 Youssef, A and Arden, B, Topology of computing joins in a relational database, Tharalson, G see Hanke, C, 493 efficiently controllable Banyan multistage 227 Thomae, D A and Van den Bout, D E, networks, 3 Ravikumar, C P, Parallel techniques for Automatic circuit partitioning in the solving large scale travelling salesperson Anyboard rapid prototyping system, 283 probleras, 149 Tong, Y see Dowling, E M, 507 Zapata, E L, Plata, O G and Rivera, F F, Rishe, N see Li, Q, 67 Tragoudas, S, Makedon, F and Farell, R, Design of parallel algorithms for a Rivera, F F see Zapata, E L, 463 Circuit partitioning into small sets, 481 distributed memory hypercube, 463 Keyword index Cellular automata Data format Maze solving, Image processing, 403 Cross-assembler, Digital signal 28F001BX Circuit partitioning microprocessor, 133 Flash memory, BIOS, 427 Rapid prototyping, Field programmable Data path testing 8087 coprocessor gate arrays, 283 Microprocessor testing, Functional Sine and cosine function evaluation, Heuristics, CAD, 481 testing, 529 High speed real time computing, 417 Clock drivers Data retention Access processors Low skew, System design, 493 Single chip microprocessor, Data Decoupled architecture, visi, 237 Colour look-up tables acquisition, 141 Adaptive signal processing rfl, Troubleshooting, 37 Decoupled architecture Transputer, Supervisor, 291 Combinatorial optimization Access processors, VLSI, 237 Address recognition Parallel computing, Genetic algorithms, Dedicated architecture Data communications, Content 351 Ladder solving processors, Programmable addressable memory, 59 Combinatorial search controllers, 369 Address traces Parallel algorithms, Intel iPSC/2, 149 Diagnosis Multicomputers, Multiprocessors, 249 Concurrent systems Cardiac monitors, Data acquisition, 311 Architecture simulation Configurable array logic, Field Diagnostic tools Object-oriented programming, Risc, 541 programmable gate arrays, 115 VMEbus, Bus analysers, 159 Architectures Configurable array logic Digital correlators Parallel systems, Performance Concurrent systems, Field programmable Microprocessor control, Interrupt- evaluation, 25 gate arrays, 115 driven software, 171 Parallel systems, Hybrid networks, 67 Content addressable memory Digital signal microprocessor Assembly language programming Data communications, Address Cross-assembler, Data format, 133 M68HC11, Stack operations, 207 recognition, 59 Discrete simulation Asynchronous circuits Convolution psp, Signal processors, 125 visi design, Formal specification, 517 Image processing, Multi-microprocessors, Distributed memory 321 Parallel programming, Hypercube Cross-assembler multicomputers, 463 BIOS Digital signal microprocessor, Data Distributed memory management Flash memory, 28F001BX, 427 format, 133 Transputers, RAM files, 263 Board layout and system noise Clock drivers, Low skew, 493 Fault simuiation Bus analysers DSP Test generation, Testability profile, 269 VMEbus, Diagnostic tools, 159 Signal processors, Discrete simulation, Fault tolerance 125 Replicated processing, Multiprocessor Data acquisition systems, 91 CAD Single chip microprocessor, Data Feature analysis Circuit partitioning, Heuristics, 481 retention, 141 Image tracing, Variable threshold logic, CMOS Cardiac monitors, Diagnosis, 311 395 RISC, VLSI, 187 Data communications Field programmable gate arrays Cardiac monitors Content addressable memory, Address Concurrent systems, Configurable array Data acquisition, Diagnosis, 311 recognition, 59 logic, 115 Microprocessors and Microsystems Circuit partitioning, Rapid prototyping, Microsystems Rapid prototyping 283 Interfacing, Transputers, 195 Circuit partitioning, Field programmable File and graphics servers Multi-microprocessors gate arrays, 283 Transputers, Petri nets, 453 Image processing, Convolution, 321 Real-time embedded systems Flash memory Multicomputer systems Multiprocessor operating systems, |/O BIOS, 28FOO1BX, 427 Message management, Message design, 81 Formal specification latency, 301 Relational databases VLSI design, Asynchronous circuits, 517 Multicomputers visi, Systolic arrays, 227 FourPort RAM Address traces, Multiprocessors, 249 Replicated processing System design, Parallel systems, 101 Multiple buses Fault tolerance, Multiprocessor systems, Functional testing Multiprocessor, Shared caches, 339 91 Microprocessor testing, Data path Multiple robots Routing control testing, 529 Multiprocessor control systems, RISC, Multistage interconnection networks, 177 Topology, 3 Multiprocessor control systems Genetic algorithms Multiple robots, risc, 177 Combinatorial optimization, Parallel Multiprocessor operating systems Shared caches computing, 351 Real-time embedded systems, I/O Multiprocessor, Multiple buses, 339 Signal processing design, 81 Parallel processing, Nonlinear functions, Multiprocessor systems Heuristics 471 Fault tolerance, Replicated processing, Circuit partitioning, CAD, 481 Microphone arrays, Speech acquisition, High speed real time computing 91 507 Multiprocessors Sine and cosine function evaluation, Signal processors 8087 coprocessor, 417 Address traces, Multicomputers, 249 psp, Discrete simulation, 125 Multiple buses, Shared caches, 339 Hybrid networks Sine and cosine function evaluation Multistage interconnection networks Architectures, Parallel systems, 67 Routing control, Topology, 3 High speed real time computing, 8086 Hypercube multicomputers microprocessor, 417 Parallel programming, Distributed Single chip microprocessor memory, 463 Nonlinear functions Data acquisition, Data retention, 141 Parallel processing, Signal processing, Software fault tolerance 1/O design 471 UNIX, Process checkpointing, 15 Multiprocessor operating systems, Real- Speech acquisition time embedded systems, 81 Microphone arrays, Signal processing, Object-oriented programming Image processing 507 Multi-microprocessors, Convolution, Architecture simulation, risc, 541 Stack operations 321 M68HC11, Assembly language Cellular automata, Maze solving, 403 Parallel algorithms programming, 207 Image tracing Combinatorial search, Intel iPSC/2, 149 Supervisor Variable threshold logic, Feature Parallel computing Transputer, Adaptive signal processing, analysis, 395 Combinatorial optimization, Genetic 291 Intel iPSC/2 algorithms, 351 System analysers Combinatorial search, Parallel Parallel processing VMEbus, Test strategies, 381 algorithms, 149 Signal processing, Nonlinear functions, System design Interfacing 471 FourPort RAM, Parallel systems, 101 Microsystems, Transputers, 195 Parallel programming Systolic arrays Interrupt-driven software Distributed memory, Hypercube visi, Relational databases, 227 Digital correlators, Microprocessor multicomputers, 463 control, 171 Parallel systems Test generation Performance evaluation, Architecture, Fault simulation, Testability profile, 269 Ladder solving processors 25 Test strategies Dedicated architecture, Programmable Architecture, Hybrid networks, 67 VMEbus, System analysers, 381 controllers, 369 FourPort RAM, System design, 101 Testability profile Low skew Performance evaluation Test generation, Fault simulation, 269 Clock drivers, System design, 493 Parallel systems, Architecture, 25 Topology Petri nets Multistage interconnection networks, M68HC11 Transputers, File and graphics servers, Routing control, 3 Assembly language programming, Stack 453 Transputer operations, 207 Process checkpointing Adaptive signal processing, Supervisor, Maze solving Software fault tolerance, UNIX, 15 291 Cellular automata, Image processing, Programmable controllers Transputers 403 Dedicated architecture, Ladder solving Microsystems, Interfacing, 195 Message latency processors, 369 Distributed memory management, RAM Multicomputer systems, Message files, 263 management, 301 RAM files File and graphics servers, Petri nets, 453 Message management Transputers, Distributed memory Troubleshooting Multicomputer systems, Message management, 263 Colour look-up tables, RFI, 37 latency, 301 RFI Microphone arrays Colour look-up tables, Troubleshooting, UNIX Speech acquisition, Signal processing, 37 Software fault tolerance, Process 507 RISC checkpointing, 15 Microprocessor control Multiple robots, Multiprocessor control Digital correlators, Interrupt-driven systems, 177 VLSI software, 171 VLSI, CMOS, 187 RISC, CMOS, 187 Microprocessor testing Object-oriented programming, Systolic arrays, Relational databases, Data path testing, Functional testing, 529 Architecture simulation, 541 227 Vol 16 No 10 1992 Decoupled architecture, Access pro- Moore and W Luk, EE&CSA Books, 1991 Comment/Editorial cessors, 237 A Clements, 388 2, 451 visi design Modula-2, The magic of; K Hopper, G Asynchronous circuits, Formal specifi- Holmes, W Rogers, Addison-Wesley, Conference reports cations, 517 1991 VMEbus J Gallacher, 331 C plus C++ in Action, Boston, USA, 10- Bus analysers, Diagnostic tools, 159 Object-oriented design with applications, 12 June 1992 System analysers, Test strategies, G Booth, Benjamin Cummings, 1991 J Cooling, 276 381 D Ince, 332 Modula-2 and Beyond, Second Variable threshold logic RISC architectures, ] C Heudin, C Panetto International Modula-2 Conference, Image tracing, Feature analysis, 395 (Eds), Chapman and Hall, 1992 Loughborough, UK, 11-13 September S Furber, 499 1991 Semi-conductor memories, testing; theory J Cooling, 276 and practice, A G van de Goor, John Book reviews Wiley, 1991 Newsfile J] Niven, 389 FPGAs, Developments in the design, 51, 58, 114, 170, 226, 282, 338, 394, 447, characteristics and applications of; W R Literature, 163, 386 450, 501, 506, 551 Microprocessors and Microsystems