Microprocessor Architectures. RISC, CISC and DSP

403 Pages·1995·22.44 MB·English

by  Steve Heath (Auth.)

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About the author:
Through his work with Motorola Semiconductors, the author has been
involved in the design and development of microprocessor-based systems
since 1982. These designs have included VMEbus systems, microcontrollers,
IBM PCs, Apple Macintoshes, and both CISC and RISC-based multiprocessor
systems, while using operating systems as varied as MS-DOS, UNIX,
Macintosh OS and real time kernels.
An avid user of computer systems, he has had over 60 articles and papers
published in the electronics press, as well as several books.
Microprocessor
Architectures
RISC, CISC and DSP
Second edition
Steve Heath
i N E W N ES
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First published 1995
©Steve Heath 1995
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TRADEMARKS/REGISTERED TRADEMARKS
Computer hardware and software brand names mentioned in this book are
protected by their respective trademarks and are acknowledged.
British Library Cataloguing in Publication Data
A catalogue record for this books is available
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ISBN 0 7506 2303 9
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Preface
' Why are there all these different processor architectures and
what do they all mean V
'Which processor will I use? and how should I choose it?'
There has been an unparalleled introduction of new
processor architectures in recent years which has widened the
choice available for designs, but also caused much confusion
with the claims and counterclaims. This has resulted in ques-
tions concerning the need for several different processor
types. The struggle for supremacy between complex instruc-
tion set computer architectures and those of reduced instruc-
tion set computer purveyors and the advent of powerful
digital signal processors has pulled the humble microproces-
sor into the realm of computer architectures, where the total
system is the key to understanding and successful implemen-
tations. The days of separate hardware and software engi-
neering are now numbered because of this close interaction
between hardware and software. The effect of one decision
now has definite repercussions with so many aspects through-
out the design.
Given the task of selecting an architecture or design
approach, both engineers and managers now require a knowl-
edge of the whole system and an explanation of the design
trade-offs and their effects. This is information that rarely
appears within data sheets or user manuals. This book fills
that knowledge gap by closely examining the developments
of Motorola's CISC, RISC and DSP processors and describing
the typical system configurations and engineering trade-offs
that are made. Section 1 provides a primer and history of the
three basic microprocessor architectures. Section 2 describes
the ways in which the architectures react with the system.
Chapter 6 covers memory designs, memory management and
cache memories. Chapter 7 examines interrupt and exception
handling and the effect on real-time applications. Chapter 8
examines basic multiprocessing ideas. Chapter 9 gives some
applications ideas which show how certain characteristics can
be exploited. Section 3 looks at some more commercial as-
pects. Chapter 10 covers semiconductor technology and what
it will bring, while Chapter 11 examines the changing design
cycle and its implications for the design process and commer-
cial success. Chapter 12 looks at future processor generations
and Chapter 13 describes the criteria that should be examined
XIV Preface
when selecting a processor. The appendices include further
information on benchmarking and binary compatibility stand-
ards.
Although these comments are as relevant today as they
were four years ago when the original edition of this book was
published, much has happened within the industry. Since
then the PowerPC architecture has appeared and RISC ap-
pears to be mounting a serious challenge to the supremacy of
CISC. So important are these issues that new material on the
PowerPC has been added and a whole chapter devoted to
understanding the RISC challenge, as well as the more normal
updating of material.
The examples have been based on Motorola's micro-
processor families, but many of the system considerations are
applicable to other processors with similar architectural char-
acteristics. To emphasize this point, this edition has addi-
tional information and comparisons to other designs and in
Appendix B, an overview of the other major processors that
are available such as the Intel 80x86 architecture and DEC
Alpha.
The material is based on several years of involvement
with users who have gone through the decision making
process and who have frequently asked the questions at the
beginning of this preface. To those of you that asked and
inspired the original and requested this edition, I thank you.
The application note on high integrity MC68020 and
MC68030 designs, the descriptions of the MC68040 processor
and silicon technology in Chapters 9,10 and 12 are based on
articles that I have written for Electronic Product Design.
Their permission to reprint the material is gratefully acknowl-
edged.
In addition, I would like to say thank you to several of
my colleagues at Motorola: to Pat Mc Andrew who has guided
and educated me through DSP — I look forward to working
with you again — and to John Letham, Ian Ferguson and
Mike Inglis for their support over the years! Special thanks
must again go to Sue Carter for yet more editing, intelligent
criticism and coffee when I need it.
Acknowledgements
The following trademarks mentioned within the text
are acknowledged:
MC6800, MC6809, MC6801, MC68000, MC68020, MC68030,
MC68040, MC68332, MC68302 MC68851, MC68881,
MC68882, MC68008, MC68HC000, MC68HC001, DSP56000,
DSP56001, DSP96000, MC88100, MC88110, MPC601,
MPC603, MPC604, and MC88200 are all trademarks of
Motorola,Inc.
PowerPC is a trademark of IBM.
UNIX is the trademark of AT&T.
VRTX is the trademark of Ready Systems, Inc.
OS-9 is the trademark of Microware.
pDOS is the trademark of Eyring Research.
PDP-11, VAX 11/780 and DEC are the trademarks of
Digital Equipment Corporation.
ÎAPX8086, ÎAPX80286, ÎAPX80386, ÎAPX80486 and Pentium
are trademarks of Intel Corporation.
While the information contained in this book has been
carefully checked for accuracy, the author assumes no
responsibility or liability for its use, or any infringement of
patents or other rights of third parties which would result.
As technical characteristics are subject to rapid change, the
data contained are presented for guidance and education
only. For exact detail, consult the manufacturers' data and
specification.
1 Complex instruction
set computers
8 bit microprocessors: the precursors of CISC
Ask what the definition of a CISC (complex instruction
set computer) processor is and often the reply will be based
around subjective comments like 'a processor that has an over
complex and inefficient instruction set', or even simply 'an
MC68000 or 8086'. The problem with these definitions is that
they fail to account for facts that more CISC microprocessors
are used than any other architecture, they provide more direct
hardware support for the software developer than any other
architecture and are often more suitable for applications than
either RISC (reduced instruction set computer) or DSP (digital
signal processor) alternatives. A CISC processor is better
described as a mature design where software compatibility
and help for software are the overriding goals.
Many of today's CISC processors owe their architec-
tural philosophy to the early 8 bit microprocessors either as a
foundation or as an example of how not to design a high
performance microprocessor. It is worthwhile reviewing these
early designs to act as an introduction and a backdrop to
further discussions.
A microprocessor can simply be described as a data
processor: information is obtained, modified according to a
predetermined set of instructions and either stored or passed
to other elements within the system. Each instruction follows
a simple set path of fetching an instruction, decoding and
acting on it, fetching data from external memory as necessary
and so on.
In detail, such events consist of several stages based
around a single or a succession of memory accesses. The basic
functional blocks within a typical 8 bit microprocessor are
depicted in the diagram. The stages needed to execute an
instruction to load an accumulator with a data byte are shown
in boldface type. Each stage is explained below.
Start of memory cycle 1.
Stage 1: Here the current program counter address
is used to fetch the next instruction from
system memory. This address is 16 bits in
size.
2 Microprocessor architectures
Stage 2: The 8 bit instruction is placed on to the data
bus and is loaded into the data routing
logic from where it is passed to the instruc-
tion decode logic.
Stage 3: The instruction decoder examines the
instruction, determines what operation is
required and how large the op code is. In
this example, the op code requires the data
value stored in the next byte location to be
loaded into an internal register. This uses
several control signals to start the next data
fetch and route the data successfully.
Microprocessor
Data
. EZ
Routing
Logic
Instruction
Register t 9
r
Decode/Control
Logic 1 Register
4,10
PROGRAM
Incremental COUNTER
Counter
• •
Address Latch
1,7
Stages involved with
instruction execution
Stage 4: An incremental counter increases the
program counter value by one so it points
to the next location.
Stage 5: The new program counter value is loaded
into the address latch, ready for the start of
a new memory cycle.
End of memory cycle 1.
Stage 6: The latched 16 bit address is placed on the
external address bus.
Stage 7: The next external memory cycle is started.
Stage 8: The 8 bit data is placed onto the data bus
by the system memory and is latched into
the data routing logic. This logic has been
told by the instruction decoder to route this
data through to the register.
Complex instruction set computers 3
Stage 9: The data is written into the register.
Stage 10: The instruction decode logic is told of the
successful data transfer, the counter
incremented by one, and the next address
stored in the program counter ready for the
next memory cycle.
End of memory cycle 2.
This succession of events is simply repeated to create
the processor flow.
8 bit microprocessor register models
The programmer has a very simple register model for
this type of processor. The model for the Motorola MC6800
8 bit processor is shown as an example. It has two 8 bit
accumulators used for storing data and performing arithme-
tic operations. The program counter is 16 bits in size and two
further 16 bit registers are provided for stack manipulations
and address indexing.
15 7 0
ACCUMULATOR A
ACCUMULATOR Β
INDEX REGISTER X
PROGRAM COUNTER
STACK POINTER
CONDITION CODE
REGISTER
The MC6800 program-
mers model
On first inspection, the model seems quite primitive
and not capable of providing the basis of a computer system.
There do not seem to be enough registers to hold data, let
alone manipulate it! What is often forgotten is that many of the
4 Microprocessor architectures
instructions, such as logical operations, can operate on direct
memory using the index register to act as pointer. This re-
moves the need to bring data into the processor at the expense
of extra memory cycles.
The stack pointer provides additional storage for the
programmer: it is used to store data like return addresses for
subroutine calls and provides additional variable storage
using a PUSH/POP mechanism. Data is PUSHed onto the
stack to store it, and POPed off to retrieve it. Providing the
programmer can track where the data resides in these stack
frames, it offers a good replacement for the missing registers.
Restrictions
An 8 bit value can provide an unsigned resolution of
only 256 bits, which makes it unsuitable for applications such
as financial, arithmetic, high precision servo control systems,
etc. The obvious solution is to increase the data size to 16 bits.
This would give a resolution of 65,536—an obvious improve-
ment. This may be acceptable for a control system but is still
not good enough for an accounting program, where a 32 bit
data value may have to be defined to provide sufficient
integer range. There is no difficulty with storing 8,16, 32 or
even 64 bits in external memory, even though this require
multiple bus accesses.
However, due to the register model, data larger than 8
bits cannot use the standard arithmetic instructions applica-
ble to 8 bit data stored in the accumulator. This means that
even a simple 16 bit addition or multiplication has to be
carried out as a series of instructions using the 8 bit model.
This reduces the overall efficiency of the architecture.
The code example is a routine for performing a simple
16 bit multiplication. It takes two unsigned 16 bit numbers and
produces a 16 bit product. If the product is larger than 16 bits,
only the least significant 16 bits are retained. The first eight or
so instructions simply create a temporary storage area on the
stack for the multiplicand, multiplier, return address and loop
counter. Compared to internal register storage, storing data in
stack frames is not as efficient due the increased external
memory access.
Accessing external data consumes machine cycles which
could be used to process data. Without suitable registers and
the 16 bit wide accumulator, all this information must be
stored externally on the stack. The algorithm used simply
performs a succession of arithmetic shifts on each half of the
multiplicand stored in the A and Β accumulators. Once this is
complete, the 16 bit result is split between the two accumula-
tors and the temporary storage cleared off the stack. The